source: rtems/cpukit/score/cpu/mips/ChangeLog @ f346774d

4.104.114.84.95
Last change on this file since f346774d was f346774d, checked in by Ralf Corsepius <ralf.corsepius@…>, on 01/01/05 at 10:31:38

2005-01-01 Ralf Corsepius <ralf.corsepius@…>

  • Makefile.am: Remove build-variant support.
  • Property mode set to 100644
File size: 14.7 KB
Line 
12005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
2
3        * Makefile.am: Remove build-variant support.
4
52004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
6        PR 730
7        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
8        for rtems-4.7
9
102004-04-09      Joel Sherrill <joel@OARcorp.com>
11
12        PR 605/bsps
13        * cpu.c: Do not use C++ style comments.
14
152004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
16        PR 601
17        * cpu_asm.S: Added __mips==32 support for R4000 processors running
18        32 bit code.  Fixed #define problems that caused fpu code to
19        always be included even when no fpu is present.
20
212004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
22
23        PR 598/bsps
24        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
25        status/control register on context switches. Missing this register
26        was causing intermittent floating point errors.
27
282003-09-04      Joel Sherrill <joel@OARcorp.com>
29
30        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
31        rtems/score/types.h: URL for license changed.
32
332003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
34
35        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
36
372003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
38
39        * configure.ac: Remove AC_CONFIG_AUX_DIR.
40
412002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
42
43        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
44        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
45
462002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
47
48        * configure.ac: Fix package name.
49
502002-11-04      Joel Sherrill <joel@OARcorp.com>
51
52        * idtcpu.h: Removed warning.
53
542002-11-01      Joel Sherrill <joel@OARcorp.com>
55
56        * idtcpu.h: Removed warnings.
57
582002-10-28      Joel Sherrill <joel@OARcorp.com>
59
60        * idtcpu.h: Removed warning by turning extra token at the end of
61        an endif into a comment.
62
632002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
64
65        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
66
672002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
68
69        * .cvsignore: Reformat.
70        Add autom4te*cache.
71        Remove autom4te.cache.
72
732002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
74
75        * cpu_asm.S: Clarified some comments, removed code that forced
76        SR_IEP on when returning from an interrupt.
77
782002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
79
80        * configure.ac: Add RTEMS_PROG_CCAS
81
822002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
83
84        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
85        Add AC_PROG_RANLIB.
86
872002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
88        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
89        deadlock caused by interrupt arriving while dispatching.
90       
912002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
92
93        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
94        Use ../../../aclocal.
95
962001-04-03      Joel Sherrill <joel@OARcorp.com>
97
98        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
99        * rtems/score/mipstypes.h: Removed.
100        * rtems/score/types.h: New file via CVS magic.
101        * Makefile.am, rtems/score/cpu.h: Account for name change.
102
1032002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
104
105        * configure.ac:
106        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
107        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
108        * Makefile.am: Remove AUTOMAKE_OPTIONS.
109
1102002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
111
112        * cpu_asm.S: Now compiles on 4600 and 4650.
113
1142002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
115
116        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
117        * rtems/score/cpu.h: Fixed register numbering in comments and made
118        interrupt enable/disable more robust.
119       
1202002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
121        * cpu_asm.S: Added support for the debug exception vector, cleaned
122        up the exception processing & exception return stuff.  Re-added
123        EPC in the task context structure so the gdb stub will know where
124        a thread is executing.  Should've left it there in the first place...
125        * idtcpu.h: Added support for the debug exception vector.
126        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
127        stack frame in an interrupt so context switch code can get the
128        userspace EPC when scheduling.
129        * rtems/score/cpu.h: Re-added EPC to the task context.
130
1312002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
132
133        * cpu_asm.S: Fixed exception return address, modified FP context
134        switch so FPU is properly enabled and also doesn't screw up the
135        exception FP handling.
136        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
137        returning from exceptions.
138        * iregdef.h: Added R_TAR to the stack frame so the target address
139        can be saved on a per-exception basis.  The new entry is past the
140        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
141        stuff.
142        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
143        to obtain FPU defines without syntax errors generated by the C
144        defintions.
145        * cpu.c: Improved interrupt level saves & restores.
146       
1472002-02-08      Joel Sherrill <joel@OARcorp.com>
148
149        * iregdef.h, rtems/score/cpu.h: Reordered register in the
150        exception stack frame to better match gdb's expectations.
151
1522001-02-05      Joel Sherrill <joel@OARcorp.com>
153
154        * cpu_asm.S: Enhanced to save/restore more registers on
155        exceptions.
156        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
157        register individually and document when it is saved.
158        * idtcpu.h: Added constants for the coprocessor 1 registers
159        revision and status.
160
1612001-02-05      Joel Sherrill <joel@OARcorp.com>
162
163        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
164
1652001-02-04      Joel Sherrill <joel@OARcorp.com>
166
167        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
168        in the previous patch that has now been confirmed.
169
1702001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
171
172        * cpu.c: Enhancements and fixes for modifying the SR when changing
173        the interrupt level.
174        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
175        managed on a per-task basis, improved handling of interrupt levels,
176        and made deferred FP contexts work on the MIPS.
177        * rtems/score/cpu.h: Modified to support above changes.
178
1792002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
180
181        * rtems/Makefile.am: Removed.
182        * rtems/score/Makefile.am: Removed.
183        * configure.ac: Reflect changes above.
184        * Makefile.am: Reflect changes above.
185
1862002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
187
188        * asm.h: Remove #include <rtems/score/targopts.h>.
189        Add #include <rtems/score/cpuopts.h>.
190        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
191
192
1932001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
194
195        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
196
1972001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
198
199        * Makefile.am: Add multilib support.
200
2012001-11-28      Joel Sherrill <joel@OARcorp.com>,
202
203        This was tracked as PR91.
204        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
205        is used to specify if the port uses the standard macro for this (FALSE).
206        A TRUE setting indicates the port provides its own implementation.
207
2082001-10-12      Joel Sherrill <joel@OARcorp.com>
209
210        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
211        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
212        Wayne Bullaughey <wayne@wmi.com>.
213
2142001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
215
216        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
217        * configure.in: Remove.
218        * configure.ac: New file, generated from configure.in by autoupdate.
219
2202001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
221
222        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
223        * Makefile.am: Use 'PREINSTALL_FILES ='.
224
2252001-07-03      Joel Sherrill <joel@OARcorp.com>
226
227        * cpu.c: Fixed typo.
228
2292000-05-24      Joel Sherrill <joel@OARcorp.com>
230
231        * rtems/score/mips.h: Added constants for MIPS exception numbers.
232        All exceptions should be given low numbers and thus can be installed
233        and processed in a uniform manner.  Variances between various MIPS
234        ISA levels were not accounted for.
235
2362001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
237
238        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
239        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
240
2412001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
242
243        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
244        the context initialization to account for floating point tasks. 
245        * rtems/score/mips.h: Added the routines mips_set_cause(),
246        mips_get_fcr31(), and mips_set_fcr31().
247        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
248
2492001-05-07      Joel Sherrill <joel@OARcorp.com>
250
251        * cpu_asm.S: Merged patches from Gregory Menke
252        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
253        stack usage and include nops in the delay slots.
254
2552001-04-20      Joel Sherrill <joel@OARcorp.com>
256
257        * cpu_asm.S: Added code to save and restore SR and EPC to
258        properly support nested interrupts.  Note that the ISR
259        (not RTEMS) enables interrupts allowing the nesting to occur.
260
2612001-03-14      Joel Sherrill <joel@OARcorp.com>
262
263        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
264        Removed unused variable _CPU_Thread_dispatch_pointer
265        and cleaned numerous comments.
266       
2672001-03-13      Joel Sherrill <joel@OARcorp.com>
268
269        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
270        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
271        Also reimplemented some assembly routines in C further reducing
272        the amount of assembly and increasing maintainability.
273
2742001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
275
276        * Makefile.am, rtems/score/Makefile.am:
277        Apply include_*HEADERS instead of H_FILES.
278
2792001-01-12      Joel Sherrill <joel@OARcorp.com>
280
281        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
282        register constraints from "general" to "register".
283
2842001-01-09      Joel Sherrill <joel@OARcorp.com>
285
286        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
287        to make it easier to conditionalize the code for various ISA levels.
288
2892001-01-08      Joel Sherrill <joel@OARcorp.com>
290
291        * idtcpu.h: Commented out definition of "wait".  It was stupid to
292        use such a common word as a macro.
293        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
294        * rtems/score/mips.h: Added include of <idtcpu.h>.
295        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
296
2972001-01-03      Joel Sherrill <joel@OARcorp.com>
298
299        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
300        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
301
3022000-12-19      Joel Sherrill <joel@OARcorp.com>
303
304        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
305        Previous code resulting in the interrupted immediately returning
306        to the caller of the routine it was inside.
307
3082000-12-19      Joel Sherrill <joel@OARcorp.com>
309
310        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
311        because it has not been allocated yet.
312
3132000-12-13      Joel Sherrill <joel@OARcorp.com>
314
315        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
316        * cpu_asm.S: Removed assembly language to vector ISR handler
317        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
318        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
319        longer a constant -- get the real value from libcpu.
320
3212000-12-13      Joel Sherrill <joel@OARcorp.com>
322
323        * cpu_asm.h: Removed.
324        * Makefile.am: Remove cpu_asm.h.
325        * rtems/score/mips64orion.h: Renamed mips.h.
326        * rtems/score/mips.h: New file, formerly mips64orion.h.
327        Header rewritten.
328        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
329        mips_disable_in_interrupt_mask): New macros.
330        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
331        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
332        few defines that were in <cpu_asm.h>.
333        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
334        MIPS ISA 3 is still in assembly for now.
335        (_CPU_Thread_Idle_body): Rewrote in C.
336        * cpu_asm.S: Rewrote file header.
337        (FRAME,ENDFRAME) now in asm.h.
338        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
339        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
340        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
341        leaves other bits in SR alone on task switch.
342        (mips_enable_interrupts,mips_disable_interrupts,
343        mips_enable_global_interrupts,mips_disable_global_interrupts,
344        disable_int, enable_int): Removed.
345        (mips_get_sr): Rewritten as C macro.
346        (_CPU_Thread_Idle_body): Rewritten in C.
347        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
348        placed in libcpu.
349        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
350        to libcpu/mips/shared/interrupts.
351        (general): Cleaned up comment blocks and #if 0 areas.
352        * idtcpu.h: Made ifdef report an error.
353        * iregdef.h: Removed warning.
354        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
355        number defined by libcpu.
356        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
357        to access SR.
358        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
359        (_CPU_Context_Initialize): Honor ISR level in task initialization.
360        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
361
3622000-12-06      Joel Sherrill <joel@OARcorp.com>
363
364        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
365        context should be 32 not 64 bits.
366
3672000-11-30      Joel Sherrill <joel@OARcorp.com>
368
369        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
370        correct name of _CPU_Context_switch_restore.  Added dummy
371        version of exc_utlb_code() so applications would link.
372
3732000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
374
375        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
376
3772000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
378
379        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
380
3812000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
382
383        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
384        Switch to GNU canonicalization.
385
3862000-10-24      Alan Cudmore <alanc@linuxstart.com> and
387        Joel Sherrill <joel@OARcorp.com>
388
389        * This is a major reworking of the mips64orion port to use
390        gcc predefines as much as possible and a big push to multilib
391        the mips port.  The mips64orion port was copied/renamed to mips
392        to be more like other GNU tools.  Alan did most of the technical
393        work of determining how to map old macro names used by the mips64orion
394        port to standard compiler macro definitions.  Joel did the merge
395        with CVS magic to keep individual file history and did the BSP
396        modifications. Details follow:
397        * Makefile.am: idtmon.h in mips64orion port not present.
398        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
399        * cpu.c: Comments added.
400        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
401        First attempt at exception/interrupt processing for ISA level 1
402        and minus any use of IDT/MON added.
403        * idtcpu.h: Conditionals changed to use gcc predefines.
404        * iregdef.h: Ditto.
405        * cpu_asm.h: No real change.  Merger required commit.
406        * rtems/Makefile.am: Ditto.
407        * rtems/score/Makefile.am: Ditto.
408        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
409        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
410        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
411
4122000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
413
414        * Makefile.am: Include compile.am.
415
4162000-08-10      Joel Sherrill <joel@OARcorp.com>
417
418        * ChangeLog: New file.
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