source: rtems/cpukit/score/cpu/mips/ChangeLog @ eaeb467

2002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>

        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
        * rtems/score/cpu.h: Fixed register numbering in comments and made
        interrupt enable/disable more robust.
        
2002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
        * cpu_asm.S: Added support for the debug exception vector, cleaned
        up the exception processing & exception return stuff.  Re-added
        EPC in the task context structure so the gdb stub will know where
        a thread is executing.  Should've left it there in the first place...
        * idtcpu.h: Added support for the debug exception vector.
        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
        stack frame in an interrupt so context switch code can get the
        userspace EPC when scheduling.
        * rtems/score/cpu.h: Re-added EPC to the task context.

2002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>

        * cpu_asm.S: Fixed exception return address, modified FP context
        switch so FPU is properly enabled and also doesn't screw up the
        exception FP handling.
        * idtcpu.h: Added C0_TAR, the MIPS target address register used for 
        returning from exceptions.
        * iregdef.h: Added R_TAR to the stack frame so the target address
        can be saved on a per-exception basis.  The new entry is past the
        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
        stuff.
        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
        to obtain FPU defines without systax errors generated by the C
        defintions.
        * cpu.c: Improved interrupt level saves & restores.
        
2002-02-08      Joel Sherrill <joel@OARcorp.com>

        * iregdef.h, rtems/score/cpu.h: Reordered register in the
        exception stack frame to better match gdb's expectations.

2001-02-05      Joel Sherrill <joel@OARcorp.com>

        * cpu_asm.S: Enhanced to save/restore more registers on 
        exceptions.
        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
        register individually and document when it is saved.
        * idtcpu.h: Added constants for the coprocessor 1 registers 
        revision and status.

2001-02-05      Joel Sherrill <joel@OARcorp.com>

        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.

2001-02-04      Joel Sherrill <joel@OARcorp.com>

        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
        in the previous patch that has now been confirmed.

2001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>

        * cpu.c: Enhancements and fixes for modifying the SR when changing
        the interrupt level.
        * cpu_asm.S: Fixed handling of FP enable bit so it is properly 
        managed on a per-task basis, improved handling of interrupt levels,
        and made deferred FP contexts work on the MIPS.
        * rtems/score/cpu.h: Modified to support above changes.

2002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * rtems/Makefile.am: Removed.
        * rtems/score/Makefile.am: Removed.
        * configure.ac: Reflect changes above.
        * Makefile.am: Reflect changes above.

2002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * asm.h: Remove #include <rtems/score/targopts.h>.
        Add #include <rtems/score/cpuopts.h>.
        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).


2001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * configure.ac: Use RTEMS_ENV_RTEMSCPU.

2001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * Makefile.am: Add multilib support.

2001-11-28      Joel Sherrill <joel@OARcorp.com>,

        This was tracked as PR91.
        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
        is used to specify if the port uses the standard macro for this (FALSE).
        A TRUE setting indicates the port provides its own implementation.

2001-10-12      Joel Sherrill <joel@OARcorp.com>

        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
        Wayne Bullaughey <wayne@wmi.com>.

2001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
        * configure.in: Remove.
        * configure.ac: New file, generated from configure.in by autoupdate.

2001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
        * Makefile.am: Use 'PREINSTALL_FILES ='.

2001-07-03      Joel Sherrill <joel@OARcorp.com>

        * cpu.c: Fixed typo.

2000-05-24      Joel Sherrill <joel@OARcorp.com>

        * rtems/score/mips.h: Added constants for MIPS exception numbers.
        All exceptions should be given low numbers and thus can be installed
        and processed in a uniform manner.  Variances between various MIPS
        ISA levels were not accounted for.

2001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>

        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.

2001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>

        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
        the context initialization to account for floating point tasks.  
        * rtems/score/mips.h: Added the routines mips_set_cause(),
        mips_get_fcr31(), and mips_set_fcr31().
        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.

2001-05-07      Joel Sherrill <joel@OARcorp.com>

        * cpu_asm.S: Merged patches from Gregory Menke
        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
        stack usage and include nops in the delay slots.

2001-04-20      Joel Sherrill <joel@OARcorp.com>

        * cpu_asm.S: Added code to save and restore SR and EPC to
        properly support nested interrupts.  Note that the ISR
        (not RTEMS) enables interrupts allowing the nesting to occur.

2001-03-14      Joel Sherrill <joel@OARcorp.com>

        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
        Removed unused variable _CPU_Thread_dispatch_pointer
        and cleaned numerous comments.
        
2001-03-13      Joel Sherrill <joel@OARcorp.com>

        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
        Also reimplemented some assembly routines in C further reducing
        the amount of assembly and increasing maintainability.

2001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * Makefile.am, rtems/score/Makefile.am: 
        Apply include_*HEADERS instead of H_FILES.

2001-01-12      Joel Sherrill <joel@OARcorp.com>

        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
        register constraints from "general" to "register".

2001-01-09      Joel Sherrill <joel@OARcorp.com>

        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
        to make it easier to conditionalize the code for various ISA levels.

2001-01-08      Joel Sherrill <joel@OARcorp.com>

        * idtcpu.h: Commented out definition of "wait".  It was stupid to
        use such a common word as a macro.
        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
        * rtems/score/mips.h: Added include of <idtcpu.h>.
        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.

2001-01-03      Joel Sherrill <joel@OARcorp.com>

        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.

2000-12-19      Joel Sherrill <joel@OARcorp.com>

        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
        Previous code resulting in the interrupted immediately returning
        to the caller of the routine it was inside.

2000-12-19      Joel Sherrill <joel@OARcorp.com>

        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
        because it has not been allocated yet.

2000-12-13      Joel Sherrill <joel@OARcorp.com>

        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
        * cpu_asm.S: Removed assembly language to vector ISR handler
        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
        longer a constant -- get the real value from libcpu.

2000-12-13      Joel Sherrill <joel@OARcorp.com>

        * cpu_asm.h: Removed.
        * Makefile.am: Remove cpu_asm.h.
        * rtems/score/mips64orion.h: Renamed mips.h.
        * rtems/score/mips.h: New file, formerly mips64orion.h.
        Header rewritten.
        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
        mips_disable_in_interrupt_mask): New macros.
        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
        few defines that were in <cpu_asm.h>.
        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
        MIPS ISA 3 is still in assembly for now.
        (_CPU_Thread_Idle_body): Rewrote in C.
        * cpu_asm.S: Rewrote file header. 
        (FRAME,ENDFRAME) now in asm.h.
        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
        leaves other bits in SR alone on task switch.
        (mips_enable_interrupts,mips_disable_interrupts,
        mips_enable_global_interrupts,mips_disable_global_interrupts,
        disable_int, enable_int): Removed.
        (mips_get_sr): Rewritten as C macro.
        (_CPU_Thread_Idle_body): Rewritten in C.
        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
        placed in libcpu.
        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
        to libcpu/mips/shared/interrupts.
        (general): Cleaned up comment blocks and #if 0 areas.
        * idtcpu.h: Made ifdef report an error.
        * iregdef.h: Removed warning.
        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
        number defined by libcpu.
        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
        to access SR.
        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
        (_CPU_Context_Initialize): Honor ISR level in task initialization.
        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.

2000-12-06      Joel Sherrill <joel@OARcorp.com>

        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
        context should be 32 not 64 bits.

2000-11-30      Joel Sherrill <joel@OARcorp.com>

        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
        correct name of _CPU_Context_switch_restore.  Added dummy
        version of exc_utlb_code() so applications would link.

2000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.

2000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.

2000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
        Switch to GNU canonicalization.

2000-10-24      Alan Cudmore <alanc@linuxstart.com> and
        Joel Sherrill <joel@OARcorp.com>

        * This is a major reworking of the mips64orion port to use 
        gcc predefines as much as possible and a big push to multilib
        the mips port.  The mips64orion port was copied/renamed to mips
        to be more like other GNU tools.  Alan did most of the technical
        work of determining how to map old macro names used by the mips64orion
        port to standard compiler macro definitions.  Joel did the merge
        with CVS magic to keep individual file history and did the BSP
        modifications. Details follow:
        * Makefile.am: idtmon.h in mips64orion port not present.
        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
        * cpu.c: Comments added.
        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
        First attempt at exception/interrupt processing for ISA level 1 
        and minus any use of IDT/MON added.
        * idtcpu.h: Conditionals changed to use gcc predefines.
        * iregdef.h: Ditto.
        * cpu_asm.h: No real change.  Merger required commit.
        * rtems/Makefile.am: Ditto.
        * rtems/score/Makefile.am: Ditto.
        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.

2000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * Makefile.am: Include compile.am.

2000-08-10      Joel Sherrill <joel@OARcorp.com>

        * ChangeLog: New file.