source: rtems/cpukit/score/cpu/mips/ChangeLog @ e4d4eb9

4.104.114.95
Last change on this file since e4d4eb9 was e4d4eb9, checked in by Joel Sherrill <joel.sherrill@…>, on 11/26/07 at 22:36:04

2007-11-26 Joel Sherrill <joel.sherrill@…>

  • rtems/score/cpu.h: Eliminate the clicks_per_microsecond field in the MIPS CPU Table and define another mechanism for drivers to obtain this information.
  • Property mode set to 100644
File size: 18.5 KB
Line 
12007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
2
3        * rtems/score/cpu.h: Eliminate the clicks_per_microsecond field in the
4        MIPS CPU Table and define another mechanism for drivers to obtain
5        this information.
6
72007-08-04      Ralf Corsépius <ralf.corsepius@rtems.org>
8
9        * rtems/score/cpu.h: Use uintptr_t instead of uint32_t.
10
112007-05-09      Ralf Corsépius <ralf.corsepius@rtems.org>
12
13        * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
14
152007-04-17      Ralf Corsépius <ralf.corsepius@rtems.org>
16
17        * rtems/score/cpu.h:
18          Use Context_Control_fp* instead of void* for fp_contexts.
19          Eliminate evil casts.
20
212006-11-17      Ralf Corsépius <ralf.corsepius@rtems.org>
22
23        * rtems/score/types.h: Remove unsigned64, signed64.
24
252006-06-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
26
27        * cpu.c: Added __mips==32 to fix build problems on those targets
28        caused by the Bruce Robinson.
29
302006-06-08 Bruce Robinson <brucer@pmccorp.com>
31
32        * cpu.c: Add int64 types for __mips==3 cpus, incorporate
33           mips_interrupt_mask() into mask computations
34        * cpu_asm.S: Add int64 register save/restores for __mips==3 cpus.  Adjustment
35           of mips1 vs mips3 macros.
36        * cpu.h: Add int64 types for __mips==3 cpus.
37       
382006-03-17      Ralf Corsepius <ralf.corsepius@rtems.org>
39
40        * cpu.c (_CPU_Initialize): Add fpu initialization.
41        * rtems/score/cpu.h: Setup CPU_*_ENDIAN from GCC's__MIPS{EL|EB}__.
42        (Partial merger of submission by Bruce Robinson <brucer@pmccorp.com>).
43
442006-01-16      Joel Sherrill <joel@OARcorp.com>
45
46        * rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
47        As a side-effect, grammar and spelling errors were corrected, spacing
48        errors were address, and some variable names were improved.
49
502005-11-18      Joel Sherrill <joel@OARcorp.com>
51
52        * rtems/score/cpu.h: Eliminate use of unsigned32.
53
542005-11-08      Ralf Corsepius <ralf.corsepius@rtems.org>
55
56        * rtems/score/types.h: Eliminate unsigned16, unsigned32.
57
582005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
59
60        * rtems/asm.h: Remove private version of CONCAT macros.
61        Include <rtems/concat.h> instead.
62
632005-04-26      Joel Sherrill <joel@OARcorp.com>
64
65        * rtems/asm.h: Eliminate warnings.
66
672005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
68
69        * Makefile.am: Split out preinstallation rules.
70        * preinstall.am: New (Split out from Makefile.am).
71
722005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
73
74        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
75        Header guards cleanup.
76
772005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
78
79        PR 754/rtems
80        * rtems/asm.h: New (relocated from .).
81        * asm.h: Remove (moved to rtems/asm.h).
82        * Makefile.am: Reflect changes above.
83
842005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
85
86        PR rtems/752
87        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
88        New header guards.
89        * idtcpu.h, iregdef.h: Remove.
90        * Makefile.am: Reflect changes above.
91
922004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
93
94        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
95        New header guards.
96
972005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
98
99        * rtems/score/types.h: Remove signed8, signed16, signed32,
100        unsigned8, unsigned16, unsigned32.
101
1022005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
103
104        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
105
1062005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
107
108        * rtems/score/types.h: #include <rtems/stdint.h>.
109
1102005-01-07      Joel Sherrill <joel@OARcorp.com>
111
112        * rtems/score/cpu.h: Remove warnings.
113
1142005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
115
116        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
117
1182005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
119
120        PR 739
121        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
122        when compiling cpu_asm.S.  Problem was a #define sneaked in in
123        version 1.11, no ill effects would have only affected R4000
124        builds.
125
1262005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
127
128        PR 737
129        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
130        slot when compiling cpu_asm.S
131
1322005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
133
134        * Makefile.am: Remove build-variant support.
135
1362004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
137
138        PR 730
139        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
140        for rtems-4.7.
141
1422004-04-09      Joel Sherrill <joel@OARcorp.com>
143
144        PR 605/bsps
145        * cpu.c: Do not use C++ style comments.
146
1472004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
148        PR 601
149        * cpu_asm.S: Added __mips==32 support for R4000 processors running
150        32 bit code.  Fixed #define problems that caused fpu code to
151        always be included even when no fpu is present.
152
1532004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
154
155        PR 598/bsps
156        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
157        status/control register on context switches. Missing this register
158        was causing intermittent floating point errors.
159
1602003-09-04      Joel Sherrill <joel@OARcorp.com>
161
162        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
163        rtems/score/types.h: URL for license changed.
164
1652003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
166
167        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
168
1692003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
170
171        * configure.ac: Remove AC_CONFIG_AUX_DIR.
172
1732002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
174
175        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
176        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
177
1782002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
179
180        * configure.ac: Fix package name.
181
1822002-11-04      Joel Sherrill <joel@OARcorp.com>
183
184        * idtcpu.h: Removed warning.
185
1862002-11-01      Joel Sherrill <joel@OARcorp.com>
187
188        * idtcpu.h: Removed warnings.
189
1902002-10-28      Joel Sherrill <joel@OARcorp.com>
191
192        * idtcpu.h: Removed warning by turning extra token at the end of
193        an endif into a comment.
194
1952002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
196
197        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
198
1992002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
200
201        * .cvsignore: Reformat.
202        Add autom4te*cache.
203        Remove autom4te.cache.
204
2052002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
206
207        * cpu_asm.S: Clarified some comments, removed code that forced
208        SR_IEP on when returning from an interrupt.
209
2102002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
211
212        * configure.ac: Add RTEMS_PROG_CCAS
213
2142002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
215
216        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
217        Add AC_PROG_RANLIB.
218
2192002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
220        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
221        deadlock caused by interrupt arriving while dispatching.
222       
2232002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
224
225        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
226        Use ../../../aclocal.
227
2282001-04-03      Joel Sherrill <joel@OARcorp.com>
229
230        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
231        * rtems/score/mipstypes.h: Removed.
232        * rtems/score/types.h: New file via CVS magic.
233        * Makefile.am, rtems/score/cpu.h: Account for name change.
234
2352002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
236
237        * configure.ac:
238        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
239        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
240        * Makefile.am: Remove AUTOMAKE_OPTIONS.
241
2422002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
243
244        * cpu_asm.S: Now compiles on 4600 and 4650.
245
2462002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
247
248        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
249        * rtems/score/cpu.h: Fixed register numbering in comments and made
250        interrupt enable/disable more robust.
251       
2522002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
253        * cpu_asm.S: Added support for the debug exception vector, cleaned
254        up the exception processing & exception return stuff.  Re-added
255        EPC in the task context structure so the gdb stub will know where
256        a thread is executing.  Should've left it there in the first place...
257        * idtcpu.h: Added support for the debug exception vector.
258        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
259        stack frame in an interrupt so context switch code can get the
260        userspace EPC when scheduling.
261        * rtems/score/cpu.h: Re-added EPC to the task context.
262
2632002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
264
265        * cpu_asm.S: Fixed exception return address, modified FP context
266        switch so FPU is properly enabled and also doesn't screw up the
267        exception FP handling.
268        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
269        returning from exceptions.
270        * iregdef.h: Added R_TAR to the stack frame so the target address
271        can be saved on a per-exception basis.  The new entry is past the
272        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
273        stuff.
274        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
275        to obtain FPU defines without syntax errors generated by the C
276        defintions.
277        * cpu.c: Improved interrupt level saves & restores.
278       
2792002-02-08      Joel Sherrill <joel@OARcorp.com>
280
281        * iregdef.h, rtems/score/cpu.h: Reordered register in the
282        exception stack frame to better match gdb's expectations.
283
2842001-02-05      Joel Sherrill <joel@OARcorp.com>
285
286        * cpu_asm.S: Enhanced to save/restore more registers on
287        exceptions.
288        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
289        register individually and document when it is saved.
290        * idtcpu.h: Added constants for the coprocessor 1 registers
291        revision and status.
292
2932001-02-05      Joel Sherrill <joel@OARcorp.com>
294
295        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
296
2972001-02-04      Joel Sherrill <joel@OARcorp.com>
298
299        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
300        in the previous patch that has now been confirmed.
301
3022001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
303
304        * cpu.c: Enhancements and fixes for modifying the SR when changing
305        the interrupt level.
306        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
307        managed on a per-task basis, improved handling of interrupt levels,
308        and made deferred FP contexts work on the MIPS.
309        * rtems/score/cpu.h: Modified to support above changes.
310
3112002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
312
313        * rtems/Makefile.am: Removed.
314        * rtems/score/Makefile.am: Removed.
315        * configure.ac: Reflect changes above.
316        * Makefile.am: Reflect changes above.
317
3182002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
319
320        * asm.h: Remove #include <rtems/score/targopts.h>.
321        Add #include <rtems/score/cpuopts.h>.
322        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
323
324
3252001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
326
327        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
328
3292001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
330
331        * Makefile.am: Add multilib support.
332
3332001-11-28      Joel Sherrill <joel@OARcorp.com>,
334
335        This was tracked as PR91.
336        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
337        is used to specify if the port uses the standard macro for this (FALSE).
338        A TRUE setting indicates the port provides its own implementation.
339
3402001-10-12      Joel Sherrill <joel@OARcorp.com>
341
342        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
343        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
344        Wayne Bullaughey <wayne@wmi.com>.
345
3462001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
347
348        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
349        * configure.in: Remove.
350        * configure.ac: New file, generated from configure.in by autoupdate.
351
3522001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
353
354        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
355        * Makefile.am: Use 'PREINSTALL_FILES ='.
356
3572001-07-03      Joel Sherrill <joel@OARcorp.com>
358
359        * cpu.c: Fixed typo.
360
3612000-05-24      Joel Sherrill <joel@OARcorp.com>
362
363        * rtems/score/mips.h: Added constants for MIPS exception numbers.
364        All exceptions should be given low numbers and thus can be installed
365        and processed in a uniform manner.  Variances between various MIPS
366        ISA levels were not accounted for.
367
3682001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
369
370        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
371        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
372
3732001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
374
375        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
376        the context initialization to account for floating point tasks. 
377        * rtems/score/mips.h: Added the routines mips_set_cause(),
378        mips_get_fcr31(), and mips_set_fcr31().
379        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
380
3812001-05-07      Joel Sherrill <joel@OARcorp.com>
382
383        * cpu_asm.S: Merged patches from Gregory Menke
384        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
385        stack usage and include nops in the delay slots.
386
3872001-04-20      Joel Sherrill <joel@OARcorp.com>
388
389        * cpu_asm.S: Added code to save and restore SR and EPC to
390        properly support nested interrupts.  Note that the ISR
391        (not RTEMS) enables interrupts allowing the nesting to occur.
392
3932001-03-14      Joel Sherrill <joel@OARcorp.com>
394
395        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
396        Removed unused variable _CPU_Thread_dispatch_pointer
397        and cleaned numerous comments.
398       
3992001-03-13      Joel Sherrill <joel@OARcorp.com>
400
401        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
402        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
403        Also reimplemented some assembly routines in C further reducing
404        the amount of assembly and increasing maintainability.
405
4062001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
407
408        * Makefile.am, rtems/score/Makefile.am:
409        Apply include_*HEADERS instead of H_FILES.
410
4112001-01-12      Joel Sherrill <joel@OARcorp.com>
412
413        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
414        register constraints from "general" to "register".
415
4162001-01-09      Joel Sherrill <joel@OARcorp.com>
417
418        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
419        to make it easier to conditionalize the code for various ISA levels.
420
4212001-01-08      Joel Sherrill <joel@OARcorp.com>
422
423        * idtcpu.h: Commented out definition of "wait".  It was stupid to
424        use such a common word as a macro.
425        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
426        * rtems/score/mips.h: Added include of <idtcpu.h>.
427        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
428
4292001-01-03      Joel Sherrill <joel@OARcorp.com>
430
431        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
432        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
433
4342000-12-19      Joel Sherrill <joel@OARcorp.com>
435
436        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
437        Previous code resulting in the interrupted immediately returning
438        to the caller of the routine it was inside.
439
4402000-12-19      Joel Sherrill <joel@OARcorp.com>
441
442        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
443        because it has not been allocated yet.
444
4452000-12-13      Joel Sherrill <joel@OARcorp.com>
446
447        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
448        * cpu_asm.S: Removed assembly language to vector ISR handler
449        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
450        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
451        longer a constant -- get the real value from libcpu.
452
4532000-12-13      Joel Sherrill <joel@OARcorp.com>
454
455        * cpu_asm.h: Removed.
456        * Makefile.am: Remove cpu_asm.h.
457        * rtems/score/mips64orion.h: Renamed mips.h.
458        * rtems/score/mips.h: New file, formerly mips64orion.h.
459        Header rewritten.
460        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
461        mips_disable_in_interrupt_mask): New macros.
462        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
463        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
464        few defines that were in <cpu_asm.h>.
465        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
466        MIPS ISA 3 is still in assembly for now.
467        (_CPU_Thread_Idle_body): Rewrote in C.
468        * cpu_asm.S: Rewrote file header.
469        (FRAME,ENDFRAME) now in asm.h.
470        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
471        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
472        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
473        leaves other bits in SR alone on task switch.
474        (mips_enable_interrupts,mips_disable_interrupts,
475        mips_enable_global_interrupts,mips_disable_global_interrupts,
476        disable_int, enable_int): Removed.
477        (mips_get_sr): Rewritten as C macro.
478        (_CPU_Thread_Idle_body): Rewritten in C.
479        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
480        placed in libcpu.
481        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
482        to libcpu/mips/shared/interrupts.
483        (general): Cleaned up comment blocks and #if 0 areas.
484        * idtcpu.h: Made ifdef report an error.
485        * iregdef.h: Removed warning.
486        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
487        number defined by libcpu.
488        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
489        to access SR.
490        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
491        (_CPU_Context_Initialize): Honor ISR level in task initialization.
492        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
493
4942000-12-06      Joel Sherrill <joel@OARcorp.com>
495
496        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
497        context should be 32 not 64 bits.
498
4992000-11-30      Joel Sherrill <joel@OARcorp.com>
500
501        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
502        correct name of _CPU_Context_switch_restore.  Added dummy
503        version of exc_utlb_code() so applications would link.
504
5052000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
506
507        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
508
5092000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
510
511        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
512
5132000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
514
515        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
516        Switch to GNU canonicalization.
517
5182000-10-24      Alan Cudmore <alanc@linuxstart.com> and
519        Joel Sherrill <joel@OARcorp.com>
520
521        * This is a major reworking of the mips64orion port to use
522        gcc predefines as much as possible and a big push to multilib
523        the mips port.  The mips64orion port was copied/renamed to mips
524        to be more like other GNU tools.  Alan did most of the technical
525        work of determining how to map old macro names used by the mips64orion
526        port to standard compiler macro definitions.  Joel did the merge
527        with CVS magic to keep individual file history and did the BSP
528        modifications. Details follow:
529        * Makefile.am: idtmon.h in mips64orion port not present.
530        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
531        * cpu.c: Comments added.
532        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
533        First attempt at exception/interrupt processing for ISA level 1
534        and minus any use of IDT/MON added.
535        * idtcpu.h: Conditionals changed to use gcc predefines.
536        * iregdef.h: Ditto.
537        * cpu_asm.h: No real change.  Merger required commit.
538        * rtems/Makefile.am: Ditto.
539        * rtems/score/Makefile.am: Ditto.
540        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
541        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
542        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
543
5442000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
545
546        * Makefile.am: Include compile.am.
547
5482000-08-10      Joel Sherrill <joel@OARcorp.com>
549
550        * ChangeLog: New file.
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