source: rtems/cpukit/score/cpu/mips/ChangeLog @ dc7f3476

4.104.114.84.95
Last change on this file since dc7f3476 was dc7f3476, checked in by Joel Sherrill <joel.sherrill@…>, on 01/07/05 at 14:35:38

Fix format.

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File size: 15.2 KB
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12005-01-07      Ralf Corsepius <ralf.corsepius@freenet.de>
2
3        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
4
52005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
6
7        PR 739
8        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
9        when compiling cpu_asm.S.  Problem was a #define sneaked in in
10        version 1.11, no ill effects would have only affected R4000
11        builds.
12
132005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
14
15        PR 737
16        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
17        slot when compiling cpu_asm.S
18
192005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
20
21        * Makefile.am: Remove build-variant support.
22
232004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
24
25        PR 730
26        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
27        for rtems-4.7.
28
292004-04-09      Joel Sherrill <joel@OARcorp.com>
30
31        PR 605/bsps
32        * cpu.c: Do not use C++ style comments.
33
342004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
35        PR 601
36        * cpu_asm.S: Added __mips==32 support for R4000 processors running
37        32 bit code.  Fixed #define problems that caused fpu code to
38        always be included even when no fpu is present.
39
402004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
41
42        PR 598/bsps
43        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
44        status/control register on context switches. Missing this register
45        was causing intermittent floating point errors.
46
472003-09-04      Joel Sherrill <joel@OARcorp.com>
48
49        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
50        rtems/score/types.h: URL for license changed.
51
522003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
53
54        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
55
562003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
57
58        * configure.ac: Remove AC_CONFIG_AUX_DIR.
59
602002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
61
62        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
63        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
64
652002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
66
67        * configure.ac: Fix package name.
68
692002-11-04      Joel Sherrill <joel@OARcorp.com>
70
71        * idtcpu.h: Removed warning.
72
732002-11-01      Joel Sherrill <joel@OARcorp.com>
74
75        * idtcpu.h: Removed warnings.
76
772002-10-28      Joel Sherrill <joel@OARcorp.com>
78
79        * idtcpu.h: Removed warning by turning extra token at the end of
80        an endif into a comment.
81
822002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
83
84        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
85
862002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
87
88        * .cvsignore: Reformat.
89        Add autom4te*cache.
90        Remove autom4te.cache.
91
922002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
93
94        * cpu_asm.S: Clarified some comments, removed code that forced
95        SR_IEP on when returning from an interrupt.
96
972002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
98
99        * configure.ac: Add RTEMS_PROG_CCAS
100
1012002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
102
103        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
104        Add AC_PROG_RANLIB.
105
1062002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
107        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
108        deadlock caused by interrupt arriving while dispatching.
109       
1102002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
111
112        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
113        Use ../../../aclocal.
114
1152001-04-03      Joel Sherrill <joel@OARcorp.com>
116
117        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
118        * rtems/score/mipstypes.h: Removed.
119        * rtems/score/types.h: New file via CVS magic.
120        * Makefile.am, rtems/score/cpu.h: Account for name change.
121
1222002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
123
124        * configure.ac:
125        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
126        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
127        * Makefile.am: Remove AUTOMAKE_OPTIONS.
128
1292002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
130
131        * cpu_asm.S: Now compiles on 4600 and 4650.
132
1332002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
134
135        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
136        * rtems/score/cpu.h: Fixed register numbering in comments and made
137        interrupt enable/disable more robust.
138       
1392002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
140        * cpu_asm.S: Added support for the debug exception vector, cleaned
141        up the exception processing & exception return stuff.  Re-added
142        EPC in the task context structure so the gdb stub will know where
143        a thread is executing.  Should've left it there in the first place...
144        * idtcpu.h: Added support for the debug exception vector.
145        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
146        stack frame in an interrupt so context switch code can get the
147        userspace EPC when scheduling.
148        * rtems/score/cpu.h: Re-added EPC to the task context.
149
1502002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
151
152        * cpu_asm.S: Fixed exception return address, modified FP context
153        switch so FPU is properly enabled and also doesn't screw up the
154        exception FP handling.
155        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
156        returning from exceptions.
157        * iregdef.h: Added R_TAR to the stack frame so the target address
158        can be saved on a per-exception basis.  The new entry is past the
159        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
160        stuff.
161        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
162        to obtain FPU defines without syntax errors generated by the C
163        defintions.
164        * cpu.c: Improved interrupt level saves & restores.
165       
1662002-02-08      Joel Sherrill <joel@OARcorp.com>
167
168        * iregdef.h, rtems/score/cpu.h: Reordered register in the
169        exception stack frame to better match gdb's expectations.
170
1712001-02-05      Joel Sherrill <joel@OARcorp.com>
172
173        * cpu_asm.S: Enhanced to save/restore more registers on
174        exceptions.
175        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
176        register individually and document when it is saved.
177        * idtcpu.h: Added constants for the coprocessor 1 registers
178        revision and status.
179
1802001-02-05      Joel Sherrill <joel@OARcorp.com>
181
182        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
183
1842001-02-04      Joel Sherrill <joel@OARcorp.com>
185
186        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
187        in the previous patch that has now been confirmed.
188
1892001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
190
191        * cpu.c: Enhancements and fixes for modifying the SR when changing
192        the interrupt level.
193        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
194        managed on a per-task basis, improved handling of interrupt levels,
195        and made deferred FP contexts work on the MIPS.
196        * rtems/score/cpu.h: Modified to support above changes.
197
1982002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
199
200        * rtems/Makefile.am: Removed.
201        * rtems/score/Makefile.am: Removed.
202        * configure.ac: Reflect changes above.
203        * Makefile.am: Reflect changes above.
204
2052002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
206
207        * asm.h: Remove #include <rtems/score/targopts.h>.
208        Add #include <rtems/score/cpuopts.h>.
209        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
210
211
2122001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
213
214        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
215
2162001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
217
218        * Makefile.am: Add multilib support.
219
2202001-11-28      Joel Sherrill <joel@OARcorp.com>,
221
222        This was tracked as PR91.
223        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
224        is used to specify if the port uses the standard macro for this (FALSE).
225        A TRUE setting indicates the port provides its own implementation.
226
2272001-10-12      Joel Sherrill <joel@OARcorp.com>
228
229        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
230        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
231        Wayne Bullaughey <wayne@wmi.com>.
232
2332001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
234
235        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
236        * configure.in: Remove.
237        * configure.ac: New file, generated from configure.in by autoupdate.
238
2392001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
240
241        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
242        * Makefile.am: Use 'PREINSTALL_FILES ='.
243
2442001-07-03      Joel Sherrill <joel@OARcorp.com>
245
246        * cpu.c: Fixed typo.
247
2482000-05-24      Joel Sherrill <joel@OARcorp.com>
249
250        * rtems/score/mips.h: Added constants for MIPS exception numbers.
251        All exceptions should be given low numbers and thus can be installed
252        and processed in a uniform manner.  Variances between various MIPS
253        ISA levels were not accounted for.
254
2552001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
256
257        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
258        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
259
2602001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
261
262        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
263        the context initialization to account for floating point tasks. 
264        * rtems/score/mips.h: Added the routines mips_set_cause(),
265        mips_get_fcr31(), and mips_set_fcr31().
266        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
267
2682001-05-07      Joel Sherrill <joel@OARcorp.com>
269
270        * cpu_asm.S: Merged patches from Gregory Menke
271        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
272        stack usage and include nops in the delay slots.
273
2742001-04-20      Joel Sherrill <joel@OARcorp.com>
275
276        * cpu_asm.S: Added code to save and restore SR and EPC to
277        properly support nested interrupts.  Note that the ISR
278        (not RTEMS) enables interrupts allowing the nesting to occur.
279
2802001-03-14      Joel Sherrill <joel@OARcorp.com>
281
282        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
283        Removed unused variable _CPU_Thread_dispatch_pointer
284        and cleaned numerous comments.
285       
2862001-03-13      Joel Sherrill <joel@OARcorp.com>
287
288        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
289        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
290        Also reimplemented some assembly routines in C further reducing
291        the amount of assembly and increasing maintainability.
292
2932001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
294
295        * Makefile.am, rtems/score/Makefile.am:
296        Apply include_*HEADERS instead of H_FILES.
297
2982001-01-12      Joel Sherrill <joel@OARcorp.com>
299
300        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
301        register constraints from "general" to "register".
302
3032001-01-09      Joel Sherrill <joel@OARcorp.com>
304
305        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
306        to make it easier to conditionalize the code for various ISA levels.
307
3082001-01-08      Joel Sherrill <joel@OARcorp.com>
309
310        * idtcpu.h: Commented out definition of "wait".  It was stupid to
311        use such a common word as a macro.
312        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
313        * rtems/score/mips.h: Added include of <idtcpu.h>.
314        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
315
3162001-01-03      Joel Sherrill <joel@OARcorp.com>
317
318        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
319        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
320
3212000-12-19      Joel Sherrill <joel@OARcorp.com>
322
323        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
324        Previous code resulting in the interrupted immediately returning
325        to the caller of the routine it was inside.
326
3272000-12-19      Joel Sherrill <joel@OARcorp.com>
328
329        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
330        because it has not been allocated yet.
331
3322000-12-13      Joel Sherrill <joel@OARcorp.com>
333
334        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
335        * cpu_asm.S: Removed assembly language to vector ISR handler
336        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
337        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
338        longer a constant -- get the real value from libcpu.
339
3402000-12-13      Joel Sherrill <joel@OARcorp.com>
341
342        * cpu_asm.h: Removed.
343        * Makefile.am: Remove cpu_asm.h.
344        * rtems/score/mips64orion.h: Renamed mips.h.
345        * rtems/score/mips.h: New file, formerly mips64orion.h.
346        Header rewritten.
347        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
348        mips_disable_in_interrupt_mask): New macros.
349        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
350        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
351        few defines that were in <cpu_asm.h>.
352        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
353        MIPS ISA 3 is still in assembly for now.
354        (_CPU_Thread_Idle_body): Rewrote in C.
355        * cpu_asm.S: Rewrote file header.
356        (FRAME,ENDFRAME) now in asm.h.
357        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
358        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
359        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
360        leaves other bits in SR alone on task switch.
361        (mips_enable_interrupts,mips_disable_interrupts,
362        mips_enable_global_interrupts,mips_disable_global_interrupts,
363        disable_int, enable_int): Removed.
364        (mips_get_sr): Rewritten as C macro.
365        (_CPU_Thread_Idle_body): Rewritten in C.
366        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
367        placed in libcpu.
368        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
369        to libcpu/mips/shared/interrupts.
370        (general): Cleaned up comment blocks and #if 0 areas.
371        * idtcpu.h: Made ifdef report an error.
372        * iregdef.h: Removed warning.
373        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
374        number defined by libcpu.
375        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
376        to access SR.
377        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
378        (_CPU_Context_Initialize): Honor ISR level in task initialization.
379        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
380
3812000-12-06      Joel Sherrill <joel@OARcorp.com>
382
383        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
384        context should be 32 not 64 bits.
385
3862000-11-30      Joel Sherrill <joel@OARcorp.com>
387
388        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
389        correct name of _CPU_Context_switch_restore.  Added dummy
390        version of exc_utlb_code() so applications would link.
391
3922000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
393
394        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
395
3962000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
397
398        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
399
4002000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
401
402        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
403        Switch to GNU canonicalization.
404
4052000-10-24      Alan Cudmore <alanc@linuxstart.com> and
406        Joel Sherrill <joel@OARcorp.com>
407
408        * This is a major reworking of the mips64orion port to use
409        gcc predefines as much as possible and a big push to multilib
410        the mips port.  The mips64orion port was copied/renamed to mips
411        to be more like other GNU tools.  Alan did most of the technical
412        work of determining how to map old macro names used by the mips64orion
413        port to standard compiler macro definitions.  Joel did the merge
414        with CVS magic to keep individual file history and did the BSP
415        modifications. Details follow:
416        * Makefile.am: idtmon.h in mips64orion port not present.
417        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
418        * cpu.c: Comments added.
419        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
420        First attempt at exception/interrupt processing for ISA level 1
421        and minus any use of IDT/MON added.
422        * idtcpu.h: Conditionals changed to use gcc predefines.
423        * iregdef.h: Ditto.
424        * cpu_asm.h: No real change.  Merger required commit.
425        * rtems/Makefile.am: Ditto.
426        * rtems/score/Makefile.am: Ditto.
427        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
428        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
429        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
430
4312000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
432
433        * Makefile.am: Include compile.am.
434
4352000-08-10      Joel Sherrill <joel@OARcorp.com>
436
437        * ChangeLog: New file.
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