source: rtems/cpukit/score/cpu/mips/ChangeLog @ dc3848d0

4.104.114.84.95
Last change on this file since dc3848d0 was dc3848d0, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 16, 2002 at 10:26:14 PM

2002-07-16 Greg Menke <gregory.menke@…>

  • cpu_asm.S: Added SR_IEO to context restore to fix isr disabled deadlock caused by interrupt arriving while dispatching.
  • Property mode set to 100644
File size: 12.8 KB
Line 
12002-07-16      Greg Menke <gregory.menke@gsfc.nasa.gov>
2
3        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
4        deadlock caused by interrupt arriving while dispatching.
5
62002-07-05      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
7
8        * configure.ac: RTEMS_TOP(../../../..).
9
102002-07-03      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
11
12        * rtems.c: Remove.
13        * Makefile.am: Reflect changes above.
14
152002-07-01      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
16
17        * configure.ac: Remove RTEMS_PROJECT_ROOT.
18
192002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
20
21        * configure.ac: Add RTEMS_PROG_CCAS
22
232002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
24
25        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
26        Add AC_PROG_RANLIB.
27
282002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
29
30        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
31        Use ../../../aclocal.
32
332001-04-03      Joel Sherrill <joel@OARcorp.com>
34
35        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
36        * rtems/score/mipstypes.h: Removed.
37        * rtems/score/types.h: New file via CVS magic.
38        * Makefile.am, rtems/score/cpu.h: Account for name change.
39
402002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
41
42        * configure.ac:
43        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
44        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
45        * Makefile.am: Remove AUTOMAKE_OPTIONS.
46
472002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
48
49        * cpu_asm.S: Now compiles on 4600 and 4650.
50
512002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
52
53        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
54        * rtems/score/cpu.h: Fixed register numbering in comments and made
55        interrupt enable/disable more robust.
56       
572002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
58        * cpu_asm.S: Added support for the debug exception vector, cleaned
59        up the exception processing & exception return stuff.  Re-added
60        EPC in the task context structure so the gdb stub will know where
61        a thread is executing.  Should've left it there in the first place...
62        * idtcpu.h: Added support for the debug exception vector.
63        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
64        stack frame in an interrupt so context switch code can get the
65        userspace EPC when scheduling.
66        * rtems/score/cpu.h: Re-added EPC to the task context.
67
682002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
69
70        * cpu_asm.S: Fixed exception return address, modified FP context
71        switch so FPU is properly enabled and also doesn't screw up the
72        exception FP handling.
73        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
74        returning from exceptions.
75        * iregdef.h: Added R_TAR to the stack frame so the target address
76        can be saved on a per-exception basis.  The new entry is past the
77        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
78        stuff.
79        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
80        to obtain FPU defines without syntax errors generated by the C
81        defintions.
82        * cpu.c: Improved interrupt level saves & restores.
83       
842002-02-08      Joel Sherrill <joel@OARcorp.com>
85
86        * iregdef.h, rtems/score/cpu.h: Reordered register in the
87        exception stack frame to better match gdb's expectations.
88
892001-02-05      Joel Sherrill <joel@OARcorp.com>
90
91        * cpu_asm.S: Enhanced to save/restore more registers on
92        exceptions.
93        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
94        register individually and document when it is saved.
95        * idtcpu.h: Added constants for the coprocessor 1 registers
96        revision and status.
97
982001-02-05      Joel Sherrill <joel@OARcorp.com>
99
100        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
101
1022001-02-04      Joel Sherrill <joel@OARcorp.com>
103
104        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
105        in the previous patch that has now been confirmed.
106
1072001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
108
109        * cpu.c: Enhancements and fixes for modifying the SR when changing
110        the interrupt level.
111        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
112        managed on a per-task basis, improved handling of interrupt levels,
113        and made deferred FP contexts work on the MIPS.
114        * rtems/score/cpu.h: Modified to support above changes.
115
1162002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
117
118        * rtems/Makefile.am: Removed.
119        * rtems/score/Makefile.am: Removed.
120        * configure.ac: Reflect changes above.
121        * Makefile.am: Reflect changes above.
122
1232002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
124
125        * asm.h: Remove #include <rtems/score/targopts.h>.
126        Add #include <rtems/score/cpuopts.h>.
127        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
128
129
1302001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
131
132        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
133
1342001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
135
136        * Makefile.am: Add multilib support.
137
1382001-11-28      Joel Sherrill <joel@OARcorp.com>,
139
140        This was tracked as PR91.
141        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
142        is used to specify if the port uses the standard macro for this (FALSE).
143        A TRUE setting indicates the port provides its own implementation.
144
1452001-10-12      Joel Sherrill <joel@OARcorp.com>
146
147        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
148        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
149        Wayne Bullaughey <wayne@wmi.com>.
150
1512001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
152
153        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
154        * configure.in: Remove.
155        * configure.ac: New file, generated from configure.in by autoupdate.
156
1572001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
158
159        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
160        * Makefile.am: Use 'PREINSTALL_FILES ='.
161
1622001-07-03      Joel Sherrill <joel@OARcorp.com>
163
164        * cpu.c: Fixed typo.
165
1662000-05-24      Joel Sherrill <joel@OARcorp.com>
167
168        * rtems/score/mips.h: Added constants for MIPS exception numbers.
169        All exceptions should be given low numbers and thus can be installed
170        and processed in a uniform manner.  Variances between various MIPS
171        ISA levels were not accounted for.
172
1732001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
174
175        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
176        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
177
1782001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
179
180        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
181        the context initialization to account for floating point tasks. 
182        * rtems/score/mips.h: Added the routines mips_set_cause(),
183        mips_get_fcr31(), and mips_set_fcr31().
184        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
185
1862001-05-07      Joel Sherrill <joel@OARcorp.com>
187
188        * cpu_asm.S: Merged patches from Gregory Menke
189        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
190        stack usage and include nops in the delay slots.
191
1922001-04-20      Joel Sherrill <joel@OARcorp.com>
193
194        * cpu_asm.S: Added code to save and restore SR and EPC to
195        properly support nested interrupts.  Note that the ISR
196        (not RTEMS) enables interrupts allowing the nesting to occur.
197
1982001-03-14      Joel Sherrill <joel@OARcorp.com>
199
200        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
201        Removed unused variable _CPU_Thread_dispatch_pointer
202        and cleaned numerous comments.
203       
2042001-03-13      Joel Sherrill <joel@OARcorp.com>
205
206        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
207        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
208        Also reimplemented some assembly routines in C further reducing
209        the amount of assembly and increasing maintainability.
210
2112001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
212
213        * Makefile.am, rtems/score/Makefile.am:
214        Apply include_*HEADERS instead of H_FILES.
215
2162001-01-12      Joel Sherrill <joel@OARcorp.com>
217
218        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
219        register constraints from "general" to "register".
220
2212001-01-09      Joel Sherrill <joel@OARcorp.com>
222
223        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
224        to make it easier to conditionalize the code for various ISA levels.
225
2262001-01-08      Joel Sherrill <joel@OARcorp.com>
227
228        * idtcpu.h: Commented out definition of "wait".  It was stupid to
229        use such a common word as a macro.
230        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
231        * rtems/score/mips.h: Added include of <idtcpu.h>.
232        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
233
2342001-01-03      Joel Sherrill <joel@OARcorp.com>
235
236        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
237        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
238
2392000-12-19      Joel Sherrill <joel@OARcorp.com>
240
241        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
242        Previous code resulting in the interrupted immediately returning
243        to the caller of the routine it was inside.
244
2452000-12-19      Joel Sherrill <joel@OARcorp.com>
246
247        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
248        because it has not been allocated yet.
249
2502000-12-13      Joel Sherrill <joel@OARcorp.com>
251
252        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
253        * cpu_asm.S: Removed assembly language to vector ISR handler
254        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
255        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
256        longer a constant -- get the real value from libcpu.
257
2582000-12-13      Joel Sherrill <joel@OARcorp.com>
259
260        * cpu_asm.h: Removed.
261        * Makefile.am: Remove cpu_asm.h.
262        * rtems/score/mips64orion.h: Renamed mips.h.
263        * rtems/score/mips.h: New file, formerly mips64orion.h.
264        Header rewritten.
265        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
266        mips_disable_in_interrupt_mask): New macros.
267        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
268        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
269        few defines that were in <cpu_asm.h>.
270        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
271        MIPS ISA 3 is still in assembly for now.
272        (_CPU_Thread_Idle_body): Rewrote in C.
273        * cpu_asm.S: Rewrote file header.
274        (FRAME,ENDFRAME) now in asm.h.
275        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
276        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
277        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
278        leaves other bits in SR alone on task switch.
279        (mips_enable_interrupts,mips_disable_interrupts,
280        mips_enable_global_interrupts,mips_disable_global_interrupts,
281        disable_int, enable_int): Removed.
282        (mips_get_sr): Rewritten as C macro.
283        (_CPU_Thread_Idle_body): Rewritten in C.
284        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
285        placed in libcpu.
286        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
287        to libcpu/mips/shared/interrupts.
288        (general): Cleaned up comment blocks and #if 0 areas.
289        * idtcpu.h: Made ifdef report an error.
290        * iregdef.h: Removed warning.
291        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
292        number defined by libcpu.
293        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
294        to access SR.
295        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
296        (_CPU_Context_Initialize): Honor ISR level in task initialization.
297        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
298
2992000-12-06      Joel Sherrill <joel@OARcorp.com>
300
301        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
302        context should be 32 not 64 bits.
303
3042000-11-30      Joel Sherrill <joel@OARcorp.com>
305
306        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
307        correct name of _CPU_Context_switch_restore.  Added dummy
308        version of exc_utlb_code() so applications would link.
309
3102000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
311
312        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
313
3142000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
315
316        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
317
3182000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
319
320        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
321        Switch to GNU canonicalization.
322
3232000-10-24      Alan Cudmore <alanc@linuxstart.com> and
324        Joel Sherrill <joel@OARcorp.com>
325
326        * This is a major reworking of the mips64orion port to use
327        gcc predefines as much as possible and a big push to multilib
328        the mips port.  The mips64orion port was copied/renamed to mips
329        to be more like other GNU tools.  Alan did most of the technical
330        work of determining how to map old macro names used by the mips64orion
331        port to standard compiler macro definitions.  Joel did the merge
332        with CVS magic to keep individual file history and did the BSP
333        modifications. Details follow:
334        * Makefile.am: idtmon.h in mips64orion port not present.
335        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
336        * cpu.c: Comments added.
337        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
338        First attempt at exception/interrupt processing for ISA level 1
339        and minus any use of IDT/MON added.
340        * idtcpu.h: Conditionals changed to use gcc predefines.
341        * iregdef.h: Ditto.
342        * cpu_asm.h: No real change.  Merger required commit.
343        * rtems/Makefile.am: Ditto.
344        * rtems/score/Makefile.am: Ditto.
345        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
346        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
347        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
348
3492000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
350
351        * Makefile.am: Include compile.am.
352
3532000-08-10      Joel Sherrill <joel@OARcorp.com>
354
355        * ChangeLog: New file.
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