source: rtems/cpukit/score/cpu/mips/ChangeLog @ d6a444d

4.104.114.84.95
Last change on this file since d6a444d was d6a444d, checked in by Ralf Corsepius <ralf.corsepius@…>, on 11/23/03 at 10:36:05

2003-11-23 Ralf Corsepius <corsepiu@…>

  • Makefile.am: Don't use gmake rules for preinstallation.
  • Property mode set to 100644
File size: 14.3 KB
Line 
12003-11-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
2
3        * Makefile.am: Don't use gmake rules for preinstallation.
4
52003-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
6
7        * configure.ac: Remove RTEMS_CANONICAL_HOST.
8
92003-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
10
11        * configure.ac: Remove RTEMS_CHECK_CPU.
12
132003-09-26      Joel Sherrill <joel@OARcorp.com>
14
15        * rtems/score/cpu.h: Obsoleting HP PA-RISC port and removing all
16        references.
17
182003-09-04      Joel Sherrill <joel@OARcorp.com>
19
20        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
21        rtems/score/types.h: URL for license changed.
22
232003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
24
25        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
26
272003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
28
29        * configure.ac: Remove AC_CONFIG_AUX_DIR.
30
312002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
32
33        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
34        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
35
362002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
37
38        * configure.ac: Fix package name.
39
402002-11-04      Joel Sherrill <joel@OARcorp.com>
41
42        * idtcpu.h: Removed warning.
43
442002-11-01      Joel Sherrill <joel@OARcorp.com>
45
46        * idtcpu.h: Removed warnings.
47
482002-10-28      Joel Sherrill <joel@OARcorp.com>
49
50        * idtcpu.h: Removed warning by turning extra token at the end of
51        an endif into a comment.
52
532002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
54
55        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
56
572002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
58
59        * .cvsignore: Reformat.
60        Add autom4te*cache.
61        Remove autom4te.cache.
62
632002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
64
65        * cpu_asm.S: Clarified some comments, removed code that forced
66        SR_IEP on when returning from an interrupt.
67
682002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
69
70        * configure.ac: Add RTEMS_PROG_CCAS
71
722002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
73
74        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
75        Add AC_PROG_RANLIB.
76
772002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
78        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
79        deadlock caused by interrupt arriving while dispatching.
80       
812002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
82
83        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
84        Use ../../../aclocal.
85
862001-04-03      Joel Sherrill <joel@OARcorp.com>
87
88        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
89        * rtems/score/mipstypes.h: Removed.
90        * rtems/score/types.h: New file via CVS magic.
91        * Makefile.am, rtems/score/cpu.h: Account for name change.
92
932002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
94
95        * configure.ac:
96        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
97        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
98        * Makefile.am: Remove AUTOMAKE_OPTIONS.
99
1002002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
101
102        * cpu_asm.S: Now compiles on 4600 and 4650.
103
1042002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
105
106        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
107        * rtems/score/cpu.h: Fixed register numbering in comments and made
108        interrupt enable/disable more robust.
109       
1102002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
111        * cpu_asm.S: Added support for the debug exception vector, cleaned
112        up the exception processing & exception return stuff.  Re-added
113        EPC in the task context structure so the gdb stub will know where
114        a thread is executing.  Should've left it there in the first place...
115        * idtcpu.h: Added support for the debug exception vector.
116        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
117        stack frame in an interrupt so context switch code can get the
118        userspace EPC when scheduling.
119        * rtems/score/cpu.h: Re-added EPC to the task context.
120
1212002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
122
123        * cpu_asm.S: Fixed exception return address, modified FP context
124        switch so FPU is properly enabled and also doesn't screw up the
125        exception FP handling.
126        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
127        returning from exceptions.
128        * iregdef.h: Added R_TAR to the stack frame so the target address
129        can be saved on a per-exception basis.  The new entry is past the
130        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
131        stuff.
132        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
133        to obtain FPU defines without syntax errors generated by the C
134        defintions.
135        * cpu.c: Improved interrupt level saves & restores.
136       
1372002-02-08      Joel Sherrill <joel@OARcorp.com>
138
139        * iregdef.h, rtems/score/cpu.h: Reordered register in the
140        exception stack frame to better match gdb's expectations.
141
1422001-02-05      Joel Sherrill <joel@OARcorp.com>
143
144        * cpu_asm.S: Enhanced to save/restore more registers on
145        exceptions.
146        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
147        register individually and document when it is saved.
148        * idtcpu.h: Added constants for the coprocessor 1 registers
149        revision and status.
150
1512001-02-05      Joel Sherrill <joel@OARcorp.com>
152
153        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
154
1552001-02-04      Joel Sherrill <joel@OARcorp.com>
156
157        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
158        in the previous patch that has now been confirmed.
159
1602001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
161
162        * cpu.c: Enhancements and fixes for modifying the SR when changing
163        the interrupt level.
164        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
165        managed on a per-task basis, improved handling of interrupt levels,
166        and made deferred FP contexts work on the MIPS.
167        * rtems/score/cpu.h: Modified to support above changes.
168
1692002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
170
171        * rtems/Makefile.am: Removed.
172        * rtems/score/Makefile.am: Removed.
173        * configure.ac: Reflect changes above.
174        * Makefile.am: Reflect changes above.
175
1762002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
177
178        * asm.h: Remove #include <rtems/score/targopts.h>.
179        Add #include <rtems/score/cpuopts.h>.
180        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
181
182
1832001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
184
185        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
186
1872001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
188
189        * Makefile.am: Add multilib support.
190
1912001-11-28      Joel Sherrill <joel@OARcorp.com>,
192
193        This was tracked as PR91.
194        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
195        is used to specify if the port uses the standard macro for this (FALSE).
196        A TRUE setting indicates the port provides its own implementation.
197
1982001-10-12      Joel Sherrill <joel@OARcorp.com>
199
200        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
201        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
202        Wayne Bullaughey <wayne@wmi.com>.
203
2042001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
205
206        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
207        * configure.in: Remove.
208        * configure.ac: New file, generated from configure.in by autoupdate.
209
2102001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
211
212        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
213        * Makefile.am: Use 'PREINSTALL_FILES ='.
214
2152001-07-03      Joel Sherrill <joel@OARcorp.com>
216
217        * cpu.c: Fixed typo.
218
2192000-05-24      Joel Sherrill <joel@OARcorp.com>
220
221        * rtems/score/mips.h: Added constants for MIPS exception numbers.
222        All exceptions should be given low numbers and thus can be installed
223        and processed in a uniform manner.  Variances between various MIPS
224        ISA levels were not accounted for.
225
2262001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
227
228        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
229        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
230
2312001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
232
233        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
234        the context initialization to account for floating point tasks. 
235        * rtems/score/mips.h: Added the routines mips_set_cause(),
236        mips_get_fcr31(), and mips_set_fcr31().
237        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
238
2392001-05-07      Joel Sherrill <joel@OARcorp.com>
240
241        * cpu_asm.S: Merged patches from Gregory Menke
242        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
243        stack usage and include nops in the delay slots.
244
2452001-04-20      Joel Sherrill <joel@OARcorp.com>
246
247        * cpu_asm.S: Added code to save and restore SR and EPC to
248        properly support nested interrupts.  Note that the ISR
249        (not RTEMS) enables interrupts allowing the nesting to occur.
250
2512001-03-14      Joel Sherrill <joel@OARcorp.com>
252
253        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
254        Removed unused variable _CPU_Thread_dispatch_pointer
255        and cleaned numerous comments.
256       
2572001-03-13      Joel Sherrill <joel@OARcorp.com>
258
259        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
260        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
261        Also reimplemented some assembly routines in C further reducing
262        the amount of assembly and increasing maintainability.
263
2642001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
265
266        * Makefile.am, rtems/score/Makefile.am:
267        Apply include_*HEADERS instead of H_FILES.
268
2692001-01-12      Joel Sherrill <joel@OARcorp.com>
270
271        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
272        register constraints from "general" to "register".
273
2742001-01-09      Joel Sherrill <joel@OARcorp.com>
275
276        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
277        to make it easier to conditionalize the code for various ISA levels.
278
2792001-01-08      Joel Sherrill <joel@OARcorp.com>
280
281        * idtcpu.h: Commented out definition of "wait".  It was stupid to
282        use such a common word as a macro.
283        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
284        * rtems/score/mips.h: Added include of <idtcpu.h>.
285        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
286
2872001-01-03      Joel Sherrill <joel@OARcorp.com>
288
289        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
290        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
291
2922000-12-19      Joel Sherrill <joel@OARcorp.com>
293
294        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
295        Previous code resulting in the interrupted immediately returning
296        to the caller of the routine it was inside.
297
2982000-12-19      Joel Sherrill <joel@OARcorp.com>
299
300        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
301        because it has not been allocated yet.
302
3032000-12-13      Joel Sherrill <joel@OARcorp.com>
304
305        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
306        * cpu_asm.S: Removed assembly language to vector ISR handler
307        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
308        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
309        longer a constant -- get the real value from libcpu.
310
3112000-12-13      Joel Sherrill <joel@OARcorp.com>
312
313        * cpu_asm.h: Removed.
314        * Makefile.am: Remove cpu_asm.h.
315        * rtems/score/mips64orion.h: Renamed mips.h.
316        * rtems/score/mips.h: New file, formerly mips64orion.h.
317        Header rewritten.
318        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
319        mips_disable_in_interrupt_mask): New macros.
320        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
321        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
322        few defines that were in <cpu_asm.h>.
323        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
324        MIPS ISA 3 is still in assembly for now.
325        (_CPU_Thread_Idle_body): Rewrote in C.
326        * cpu_asm.S: Rewrote file header.
327        (FRAME,ENDFRAME) now in asm.h.
328        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
329        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
330        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
331        leaves other bits in SR alone on task switch.
332        (mips_enable_interrupts,mips_disable_interrupts,
333        mips_enable_global_interrupts,mips_disable_global_interrupts,
334        disable_int, enable_int): Removed.
335        (mips_get_sr): Rewritten as C macro.
336        (_CPU_Thread_Idle_body): Rewritten in C.
337        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
338        placed in libcpu.
339        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
340        to libcpu/mips/shared/interrupts.
341        (general): Cleaned up comment blocks and #if 0 areas.
342        * idtcpu.h: Made ifdef report an error.
343        * iregdef.h: Removed warning.
344        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
345        number defined by libcpu.
346        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
347        to access SR.
348        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
349        (_CPU_Context_Initialize): Honor ISR level in task initialization.
350        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
351
3522000-12-06      Joel Sherrill <joel@OARcorp.com>
353
354        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
355        context should be 32 not 64 bits.
356
3572000-11-30      Joel Sherrill <joel@OARcorp.com>
358
359        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
360        correct name of _CPU_Context_switch_restore.  Added dummy
361        version of exc_utlb_code() so applications would link.
362
3632000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
364
365        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
366
3672000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
368
369        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
370
3712000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
372
373        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
374        Switch to GNU canonicalization.
375
3762000-10-24      Alan Cudmore <alanc@linuxstart.com> and
377        Joel Sherrill <joel@OARcorp.com>
378
379        * This is a major reworking of the mips64orion port to use
380        gcc predefines as much as possible and a big push to multilib
381        the mips port.  The mips64orion port was copied/renamed to mips
382        to be more like other GNU tools.  Alan did most of the technical
383        work of determining how to map old macro names used by the mips64orion
384        port to standard compiler macro definitions.  Joel did the merge
385        with CVS magic to keep individual file history and did the BSP
386        modifications. Details follow:
387        * Makefile.am: idtmon.h in mips64orion port not present.
388        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
389        * cpu.c: Comments added.
390        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
391        First attempt at exception/interrupt processing for ISA level 1
392        and minus any use of IDT/MON added.
393        * idtcpu.h: Conditionals changed to use gcc predefines.
394        * iregdef.h: Ditto.
395        * cpu_asm.h: No real change.  Merger required commit.
396        * rtems/Makefile.am: Ditto.
397        * rtems/score/Makefile.am: Ditto.
398        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
399        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
400        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
401
4022000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
403
404        * Makefile.am: Include compile.am.
405
4062000-08-10      Joel Sherrill <joel@OARcorp.com>
407
408        * ChangeLog: New file.
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