source: rtems/cpukit/score/cpu/mips/ChangeLog @ d3b09bf4

4.104.114.84.9
Last change on this file since d3b09bf4 was d3b09bf4, checked in by Ralf Corsepius <ralf.corsepius@…>, on Mar 29, 2004 at 12:59:18 PM

2004-03-29 Ralf Corsepius <ralf_corsepius@…>

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File size: 15.5 KB
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12004-03-29      Ralf Corsepius <ralf_corsepius@rtems.org>
2
3        * configure.ac: RTEMS_TOP([../../../..]).
4
52004-01-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
6
7        * configure.ac: Move RTEMS_TOP one subdir down.
8
92004-01-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
10
11        * Makefile.am: Add PREINSTALL_DIRS.
12
132004-01-14      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
14
15        * Makefile.am: Re-add dirstamps to PREINSTALL_FILES.
16        Add PREINSTALL_FILES to CLEANFILES.
17
182004-01-12      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
19
20        * configure.ac: Requires automake >= 1.8.1.
21
222004-01-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
23
24        * Makefile.am: Include compile.am, again.
25
262004-01-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
27
28        * Makefile.am: Convert to using automake compilation rules.
29
302004-01-07      Joel Sherrill <joel@OARcorp.com>
31
32        * rtems/score/mips.h: Removed junk revision line.
33
342003-12-12      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
35
36        * Makefile.am: Use mkdir_p. Remove dirs from PREINSTALL_FILES.
37
382003-12-12      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
39
40        * configure.ac: Require automake >= 1.8, autoconf >= 2.59.
41
422003-12-01      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
43
44        * Makefile.am: Remove TMPINSTALL_FILES.
45
462003-11-30      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
47
48        * Makefile.am: Add $(dirstamp) to preinstallation rules.
49
502003-11-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
51
52        * Makefile.am: Don't use gmake rules for preinstallation.
53
542003-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
55
56        * configure.ac: Remove RTEMS_CANONICAL_HOST.
57
582003-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
59
60        * configure.ac: Remove RTEMS_CHECK_CPU.
61
622003-09-26      Joel Sherrill <joel@OARcorp.com>
63
64        * rtems/score/cpu.h: Obsoleting HP PA-RISC port and removing all
65        references.
66
672003-09-04      Joel Sherrill <joel@OARcorp.com>
68
69        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
70        rtems/score/types.h: URL for license changed.
71
722003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
73
74        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
75
762003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
77
78        * configure.ac: Remove AC_CONFIG_AUX_DIR.
79
802002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
81
82        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
83        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
84
852002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
86
87        * configure.ac: Fix package name.
88
892002-11-04      Joel Sherrill <joel@OARcorp.com>
90
91        * idtcpu.h: Removed warning.
92
932002-11-01      Joel Sherrill <joel@OARcorp.com>
94
95        * idtcpu.h: Removed warnings.
96
972002-10-28      Joel Sherrill <joel@OARcorp.com>
98
99        * idtcpu.h: Removed warning by turning extra token at the end of
100        an endif into a comment.
101
1022002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
103
104        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
105
1062002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
107
108        * .cvsignore: Reformat.
109        Add autom4te*cache.
110        Remove autom4te.cache.
111
1122002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
113
114        * cpu_asm.S: Clarified some comments, removed code that forced
115        SR_IEP on when returning from an interrupt.
116
1172002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
118
119        * configure.ac: Add RTEMS_PROG_CCAS
120
1212002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
122
123        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
124        Add AC_PROG_RANLIB.
125
1262002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
127        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
128        deadlock caused by interrupt arriving while dispatching.
129       
1302002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
131
132        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
133        Use ../../../aclocal.
134
1352001-04-03      Joel Sherrill <joel@OARcorp.com>
136
137        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
138        * rtems/score/mipstypes.h: Removed.
139        * rtems/score/types.h: New file via CVS magic.
140        * Makefile.am, rtems/score/cpu.h: Account for name change.
141
1422002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
143
144        * configure.ac:
145        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
146        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
147        * Makefile.am: Remove AUTOMAKE_OPTIONS.
148
1492002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
150
151        * cpu_asm.S: Now compiles on 4600 and 4650.
152
1532002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
154
155        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
156        * rtems/score/cpu.h: Fixed register numbering in comments and made
157        interrupt enable/disable more robust.
158       
1592002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
160        * cpu_asm.S: Added support for the debug exception vector, cleaned
161        up the exception processing & exception return stuff.  Re-added
162        EPC in the task context structure so the gdb stub will know where
163        a thread is executing.  Should've left it there in the first place...
164        * idtcpu.h: Added support for the debug exception vector.
165        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
166        stack frame in an interrupt so context switch code can get the
167        userspace EPC when scheduling.
168        * rtems/score/cpu.h: Re-added EPC to the task context.
169
1702002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
171
172        * cpu_asm.S: Fixed exception return address, modified FP context
173        switch so FPU is properly enabled and also doesn't screw up the
174        exception FP handling.
175        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
176        returning from exceptions.
177        * iregdef.h: Added R_TAR to the stack frame so the target address
178        can be saved on a per-exception basis.  The new entry is past the
179        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
180        stuff.
181        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
182        to obtain FPU defines without syntax errors generated by the C
183        defintions.
184        * cpu.c: Improved interrupt level saves & restores.
185       
1862002-02-08      Joel Sherrill <joel@OARcorp.com>
187
188        * iregdef.h, rtems/score/cpu.h: Reordered register in the
189        exception stack frame to better match gdb's expectations.
190
1912001-02-05      Joel Sherrill <joel@OARcorp.com>
192
193        * cpu_asm.S: Enhanced to save/restore more registers on
194        exceptions.
195        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
196        register individually and document when it is saved.
197        * idtcpu.h: Added constants for the coprocessor 1 registers
198        revision and status.
199
2002001-02-05      Joel Sherrill <joel@OARcorp.com>
201
202        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
203
2042001-02-04      Joel Sherrill <joel@OARcorp.com>
205
206        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
207        in the previous patch that has now been confirmed.
208
2092001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
210
211        * cpu.c: Enhancements and fixes for modifying the SR when changing
212        the interrupt level.
213        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
214        managed on a per-task basis, improved handling of interrupt levels,
215        and made deferred FP contexts work on the MIPS.
216        * rtems/score/cpu.h: Modified to support above changes.
217
2182002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
219
220        * rtems/Makefile.am: Removed.
221        * rtems/score/Makefile.am: Removed.
222        * configure.ac: Reflect changes above.
223        * Makefile.am: Reflect changes above.
224
2252002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
226
227        * asm.h: Remove #include <rtems/score/targopts.h>.
228        Add #include <rtems/score/cpuopts.h>.
229        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
230
231
2322001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
233
234        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
235
2362001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
237
238        * Makefile.am: Add multilib support.
239
2402001-11-28      Joel Sherrill <joel@OARcorp.com>,
241
242        This was tracked as PR91.
243        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
244        is used to specify if the port uses the standard macro for this (FALSE).
245        A TRUE setting indicates the port provides its own implementation.
246
2472001-10-12      Joel Sherrill <joel@OARcorp.com>
248
249        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
250        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
251        Wayne Bullaughey <wayne@wmi.com>.
252
2532001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
254
255        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
256        * configure.in: Remove.
257        * configure.ac: New file, generated from configure.in by autoupdate.
258
2592001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
260
261        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
262        * Makefile.am: Use 'PREINSTALL_FILES ='.
263
2642001-07-03      Joel Sherrill <joel@OARcorp.com>
265
266        * cpu.c: Fixed typo.
267
2682000-05-24      Joel Sherrill <joel@OARcorp.com>
269
270        * rtems/score/mips.h: Added constants for MIPS exception numbers.
271        All exceptions should be given low numbers and thus can be installed
272        and processed in a uniform manner.  Variances between various MIPS
273        ISA levels were not accounted for.
274
2752001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
276
277        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
278        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
279
2802001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
281
282        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
283        the context initialization to account for floating point tasks. 
284        * rtems/score/mips.h: Added the routines mips_set_cause(),
285        mips_get_fcr31(), and mips_set_fcr31().
286        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
287
2882001-05-07      Joel Sherrill <joel@OARcorp.com>
289
290        * cpu_asm.S: Merged patches from Gregory Menke
291        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
292        stack usage and include nops in the delay slots.
293
2942001-04-20      Joel Sherrill <joel@OARcorp.com>
295
296        * cpu_asm.S: Added code to save and restore SR and EPC to
297        properly support nested interrupts.  Note that the ISR
298        (not RTEMS) enables interrupts allowing the nesting to occur.
299
3002001-03-14      Joel Sherrill <joel@OARcorp.com>
301
302        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
303        Removed unused variable _CPU_Thread_dispatch_pointer
304        and cleaned numerous comments.
305       
3062001-03-13      Joel Sherrill <joel@OARcorp.com>
307
308        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
309        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
310        Also reimplemented some assembly routines in C further reducing
311        the amount of assembly and increasing maintainability.
312
3132001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
314
315        * Makefile.am, rtems/score/Makefile.am:
316        Apply include_*HEADERS instead of H_FILES.
317
3182001-01-12      Joel Sherrill <joel@OARcorp.com>
319
320        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
321        register constraints from "general" to "register".
322
3232001-01-09      Joel Sherrill <joel@OARcorp.com>
324
325        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
326        to make it easier to conditionalize the code for various ISA levels.
327
3282001-01-08      Joel Sherrill <joel@OARcorp.com>
329
330        * idtcpu.h: Commented out definition of "wait".  It was stupid to
331        use such a common word as a macro.
332        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
333        * rtems/score/mips.h: Added include of <idtcpu.h>.
334        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
335
3362001-01-03      Joel Sherrill <joel@OARcorp.com>
337
338        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
339        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
340
3412000-12-19      Joel Sherrill <joel@OARcorp.com>
342
343        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
344        Previous code resulting in the interrupted immediately returning
345        to the caller of the routine it was inside.
346
3472000-12-19      Joel Sherrill <joel@OARcorp.com>
348
349        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
350        because it has not been allocated yet.
351
3522000-12-13      Joel Sherrill <joel@OARcorp.com>
353
354        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
355        * cpu_asm.S: Removed assembly language to vector ISR handler
356        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
357        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
358        longer a constant -- get the real value from libcpu.
359
3602000-12-13      Joel Sherrill <joel@OARcorp.com>
361
362        * cpu_asm.h: Removed.
363        * Makefile.am: Remove cpu_asm.h.
364        * rtems/score/mips64orion.h: Renamed mips.h.
365        * rtems/score/mips.h: New file, formerly mips64orion.h.
366        Header rewritten.
367        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
368        mips_disable_in_interrupt_mask): New macros.
369        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
370        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
371        few defines that were in <cpu_asm.h>.
372        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
373        MIPS ISA 3 is still in assembly for now.
374        (_CPU_Thread_Idle_body): Rewrote in C.
375        * cpu_asm.S: Rewrote file header.
376        (FRAME,ENDFRAME) now in asm.h.
377        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
378        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
379        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
380        leaves other bits in SR alone on task switch.
381        (mips_enable_interrupts,mips_disable_interrupts,
382        mips_enable_global_interrupts,mips_disable_global_interrupts,
383        disable_int, enable_int): Removed.
384        (mips_get_sr): Rewritten as C macro.
385        (_CPU_Thread_Idle_body): Rewritten in C.
386        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
387        placed in libcpu.
388        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
389        to libcpu/mips/shared/interrupts.
390        (general): Cleaned up comment blocks and #if 0 areas.
391        * idtcpu.h: Made ifdef report an error.
392        * iregdef.h: Removed warning.
393        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
394        number defined by libcpu.
395        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
396        to access SR.
397        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
398        (_CPU_Context_Initialize): Honor ISR level in task initialization.
399        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
400
4012000-12-06      Joel Sherrill <joel@OARcorp.com>
402
403        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
404        context should be 32 not 64 bits.
405
4062000-11-30      Joel Sherrill <joel@OARcorp.com>
407
408        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
409        correct name of _CPU_Context_switch_restore.  Added dummy
410        version of exc_utlb_code() so applications would link.
411
4122000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
413
414        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
415
4162000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
417
418        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
419
4202000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
421
422        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
423        Switch to GNU canonicalization.
424
4252000-10-24      Alan Cudmore <alanc@linuxstart.com> and
426        Joel Sherrill <joel@OARcorp.com>
427
428        * This is a major reworking of the mips64orion port to use
429        gcc predefines as much as possible and a big push to multilib
430        the mips port.  The mips64orion port was copied/renamed to mips
431        to be more like other GNU tools.  Alan did most of the technical
432        work of determining how to map old macro names used by the mips64orion
433        port to standard compiler macro definitions.  Joel did the merge
434        with CVS magic to keep individual file history and did the BSP
435        modifications. Details follow:
436        * Makefile.am: idtmon.h in mips64orion port not present.
437        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
438        * cpu.c: Comments added.
439        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
440        First attempt at exception/interrupt processing for ISA level 1
441        and minus any use of IDT/MON added.
442        * idtcpu.h: Conditionals changed to use gcc predefines.
443        * iregdef.h: Ditto.
444        * cpu_asm.h: No real change.  Merger required commit.
445        * rtems/Makefile.am: Ditto.
446        * rtems/score/Makefile.am: Ditto.
447        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
448        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
449        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
450
4512000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
452
453        * Makefile.am: Include compile.am.
454
4552000-08-10      Joel Sherrill <joel@OARcorp.com>
456
457        * ChangeLog: New file.
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