source: rtems/cpukit/score/cpu/mips/ChangeLog @ d26dce2

4.104.114.84.95
Last change on this file since d26dce2 was d26dce2, checked in by Joel Sherrill <joel.sherrill@…>, on 05/24/01 at 13:19:51

2001-05-24 Greg Menke <gregory.menke@…>

  • Assisted in design and debug by Joel Sherrill <joel@…>.
  • cpu_asm.S: Now works on Mongoose-V. Missed in previous patch.
  • Property mode set to 100644
File size: 7.1 KB
Line 
12001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
2
3        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
4        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
5
62001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
7
8        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
9        the context initialization to account for floating point tasks. 
10        * rtems/score/mips.h: Added the routines mips_set_cause(),
11        mips_get_fcr31(), and mips_set_fcr31().
12        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
13
142001-05-07      Joel Sherrill <joel@OARcorp.com>
15
16        * cpu_asm.S: Merged patches from Gregory Menke
17        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
18        stack usage and include nops in the delay slots.
19
202001-04-20      Joel Sherrill <joel@OARcorp.com>
21
22        * cpu_asm.S: Added code to save and restore SR and EPC to
23        properly support nested interrupts.  Note that the ISR
24        (not RTEMS) enables interrupts allowing the nesting to occur.
25
262001-03-14      Joel Sherrill <joel@OARcorp.com>
27
28        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
29        Removed unused variable _CPU_Thread_dispatch_pointer
30        and cleaned numerous comments.
31       
322001-03-13      Joel Sherrill <joel@OARcorp.com>
33
34        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
35        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
36        Also reimplemented some assembly routines in C further reducing
37        the amount of assembly and increasing maintainability.
38
392001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
40
41        * Makefile.am, rtems/score/Makefile.am:
42        Apply include_*HEADERS instead of H_FILES.
43
442001-01-12      Joel Sherrill <joel@OARcorp.com>
45
46        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
47        register constraints from "general" to "register".
48
492001-01-09      Joel Sherrill <joel@OARcorp.com>
50
51        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
52        to make it easier to conditionalize the code for various ISA levels.
53
542001-01-08      Joel Sherrill <joel@OARcorp.com>
55
56        * idtcpu.h: Commented out definition of "wait".  It was stupid to
57        use such a common word as a macro.
58        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
59        * rtems/score/mips.h: Added include of <idtcpu.h>.
60        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
61
622001-01-03      Joel Sherrill <joel@OARcorp.com>
63
64        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
65        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
66
672000-12-19      Joel Sherrill <joel@OARcorp.com>
68
69        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
70        Previous code resulting in the interrupted immediately returning
71        to the caller of the routine it was inside.
72
732000-12-19      Joel Sherrill <joel@OARcorp.com>
74
75        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
76        because it has not been allocated yet.
77
782000-12-13      Joel Sherrill <joel@OARcorp.com>
79
80        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
81        * cpu_asm.S: Removed assembly language to vector ISR handler
82        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
83        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
84        longer a constant -- get the real value from libcpu.
85
862000-12-13      Joel Sherrill <joel@OARcorp.com>
87
88        * cpu_asm.h: Removed.
89        * Makefile.am: Remove cpu_asm.h.
90        * rtems/score/mips64orion.h: Renamed mips.h.
91        * rtems/score/mips.h: New file, formerly mips64orion.h.
92        Header rewritten.
93        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
94        mips_disable_in_interrupt_mask): New macros.
95        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
96        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
97        few defines that were in <cpu_asm.h>.
98        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
99        MIPS ISA 3 is still in assembly for now.
100        (_CPU_Thread_Idle_body): Rewrote in C.
101        * cpu_asm.S: Rewrote file header.
102        (FRAME,ENDFRAME) now in asm.h.
103        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
104        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
105        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
106        leaves other bits in SR alone on task switch.
107        (mips_enable_interrupts,mips_disable_interrupts,
108        mips_enable_global_interrupts,mips_disable_global_interrupts,
109        disable_int, enable_int): Removed.
110        (mips_get_sr): Rewritten as C macro.
111        (_CPU_Thread_Idle_body): Rewritten in C.
112        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
113        placed in libcpu.
114        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
115        to libcpu/mips/shared/interrupts.
116        (general): Cleaned up comment blocks and #if 0 areas.
117        * idtcpu.h: Made ifdef report an error.
118        * iregdef.h: Removed warning.
119        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
120        number defined by libcpu.
121        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
122        to access SR.
123        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
124        (_CPU_Context_Initialize): Honor ISR level in task initialization.
125        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
126
1272000-12-06      Joel Sherrill <joel@OARcorp.com>
128
129        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
130        context should be 32 not 64 bits.
131
1322000-11-30      Joel Sherrill <joel@OARcorp.com>
133
134        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
135        correct name of _CPU_Context_switch_restore.  Added dummy
136        version of exc_utlb_code() so applications would link.
137
1382000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
139
140        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
141
1422000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
143
144        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
145
1462000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
147
148        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
149        Switch to GNU canonicalization.
150
1512000-10-24      Alan Cudmore <alanc@linuxstart.com> and
152        Joel Sherrill <joel@OARcorp.com>
153
154        * This is a major reworking of the mips64orion port to use
155        gcc predefines as much as possible and a big push to multilib
156        the mips port.  The mips64orion port was copied/renamed to mips
157        to be more like other GNU tools.  Alan did most of the technical
158        work of determining how to map old macro names used by the mips64orion
159        port to standard compiler macro definitions.  Joel did the merge
160        with CVS magic to keep individual file history and did the BSP
161        modifications. Details follow:
162        * Makefile.am: idtmon.h in mips64orion port not present.
163        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
164        * cpu.c: Comments added.
165        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
166        First attempt at exception/interrupt processing for ISA level 1
167        and minus any use of IDT/MON added.
168        * idtcpu.h: Conditionals changed to use gcc predefines.
169        * iregdef.h: Ditto.
170        * cpu_asm.h: No real change.  Merger required commit.
171        * rtems/Makefile.am: Ditto.
172        * rtems/score/Makefile.am: Ditto.
173        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
174        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
175        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
176
1772000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
178
179        * Makefile.am: Include compile.am.
180
1812000-08-10      Joel Sherrill <joel@OARcorp.com>
182
183        * ChangeLog: New file.
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