source: rtems/cpukit/score/cpu/mips/ChangeLog @ c163e3b9

4.104.114.84.95
Last change on this file since c163e3b9 was c163e3b9, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 26, 2005 at 11:36:33 PM

2005-04-26 Joel Sherrill <joel@…>

  • rtems/asm.h: Eliminate warnings.
  • Property mode set to 100644
File size: 16.5 KB
Line 
12005-04-26      Joel Sherrill <joel@OARcorp.com>
2
3        * rtems/asm.h: Eliminate warnings.
4
52005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
6
7        * Makefile.am: Split out preinstallation rules.
8        * preinstall.am: New (Split out from Makefile.am).
9
102005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
11
12        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
13        Header guards cleanup.
14
152005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
16
17        PR 754/rtems
18        * rtems/asm.h: New (relocated from .).
19        * asm.h: Remove (moved to rtems/asm.h).
20        * Makefile.am: Reflect changes above.
21
222005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
23
24        PR rtems/752
25        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
26        New header guards.
27        * idtcpu.h, iregdef.h: Remove.
28        * Makefile.am: Reflect changes above.
29
302004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
31
32        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
33        New header guards.
34
352005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
36
37        * rtems/score/types.h: Remove signed8, signed16, signed32,
38        unsigned8, unsigned16, unsigned32.
39
402005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
41
42        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
43
442005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
45
46        * rtems/score/types.h: #include <rtems/stdint.h>.
47
482005-01-07      Joel Sherrill <joel@OARcorp.com>
49
50        * rtems/score/cpu.h: Remove warnings.
51
522005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
53
54        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
55
562005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
57
58        PR 739
59        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
60        when compiling cpu_asm.S.  Problem was a #define sneaked in in
61        version 1.11, no ill effects would have only affected R4000
62        builds.
63
642005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
65
66        PR 737
67        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
68        slot when compiling cpu_asm.S
69
702005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
71
72        * Makefile.am: Remove build-variant support.
73
742004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
75
76        PR 730
77        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
78        for rtems-4.7.
79
802004-04-09      Joel Sherrill <joel@OARcorp.com>
81
82        PR 605/bsps
83        * cpu.c: Do not use C++ style comments.
84
852004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
86        PR 601
87        * cpu_asm.S: Added __mips==32 support for R4000 processors running
88        32 bit code.  Fixed #define problems that caused fpu code to
89        always be included even when no fpu is present.
90
912004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
92
93        PR 598/bsps
94        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
95        status/control register on context switches. Missing this register
96        was causing intermittent floating point errors.
97
982003-09-04      Joel Sherrill <joel@OARcorp.com>
99
100        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
101        rtems/score/types.h: URL for license changed.
102
1032003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
104
105        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
106
1072003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
108
109        * configure.ac: Remove AC_CONFIG_AUX_DIR.
110
1112002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
112
113        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
114        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
115
1162002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
117
118        * configure.ac: Fix package name.
119
1202002-11-04      Joel Sherrill <joel@OARcorp.com>
121
122        * idtcpu.h: Removed warning.
123
1242002-11-01      Joel Sherrill <joel@OARcorp.com>
125
126        * idtcpu.h: Removed warnings.
127
1282002-10-28      Joel Sherrill <joel@OARcorp.com>
129
130        * idtcpu.h: Removed warning by turning extra token at the end of
131        an endif into a comment.
132
1332002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
134
135        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
136
1372002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
138
139        * .cvsignore: Reformat.
140        Add autom4te*cache.
141        Remove autom4te.cache.
142
1432002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
144
145        * cpu_asm.S: Clarified some comments, removed code that forced
146        SR_IEP on when returning from an interrupt.
147
1482002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
149
150        * configure.ac: Add RTEMS_PROG_CCAS
151
1522002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
153
154        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
155        Add AC_PROG_RANLIB.
156
1572002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
158        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
159        deadlock caused by interrupt arriving while dispatching.
160       
1612002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
162
163        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
164        Use ../../../aclocal.
165
1662001-04-03      Joel Sherrill <joel@OARcorp.com>
167
168        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
169        * rtems/score/mipstypes.h: Removed.
170        * rtems/score/types.h: New file via CVS magic.
171        * Makefile.am, rtems/score/cpu.h: Account for name change.
172
1732002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
174
175        * configure.ac:
176        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
177        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
178        * Makefile.am: Remove AUTOMAKE_OPTIONS.
179
1802002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
181
182        * cpu_asm.S: Now compiles on 4600 and 4650.
183
1842002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
185
186        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
187        * rtems/score/cpu.h: Fixed register numbering in comments and made
188        interrupt enable/disable more robust.
189       
1902002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
191        * cpu_asm.S: Added support for the debug exception vector, cleaned
192        up the exception processing & exception return stuff.  Re-added
193        EPC in the task context structure so the gdb stub will know where
194        a thread is executing.  Should've left it there in the first place...
195        * idtcpu.h: Added support for the debug exception vector.
196        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
197        stack frame in an interrupt so context switch code can get the
198        userspace EPC when scheduling.
199        * rtems/score/cpu.h: Re-added EPC to the task context.
200
2012002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
202
203        * cpu_asm.S: Fixed exception return address, modified FP context
204        switch so FPU is properly enabled and also doesn't screw up the
205        exception FP handling.
206        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
207        returning from exceptions.
208        * iregdef.h: Added R_TAR to the stack frame so the target address
209        can be saved on a per-exception basis.  The new entry is past the
210        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
211        stuff.
212        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
213        to obtain FPU defines without syntax errors generated by the C
214        defintions.
215        * cpu.c: Improved interrupt level saves & restores.
216       
2172002-02-08      Joel Sherrill <joel@OARcorp.com>
218
219        * iregdef.h, rtems/score/cpu.h: Reordered register in the
220        exception stack frame to better match gdb's expectations.
221
2222001-02-05      Joel Sherrill <joel@OARcorp.com>
223
224        * cpu_asm.S: Enhanced to save/restore more registers on
225        exceptions.
226        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
227        register individually and document when it is saved.
228        * idtcpu.h: Added constants for the coprocessor 1 registers
229        revision and status.
230
2312001-02-05      Joel Sherrill <joel@OARcorp.com>
232
233        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
234
2352001-02-04      Joel Sherrill <joel@OARcorp.com>
236
237        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
238        in the previous patch that has now been confirmed.
239
2402001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
241
242        * cpu.c: Enhancements and fixes for modifying the SR when changing
243        the interrupt level.
244        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
245        managed on a per-task basis, improved handling of interrupt levels,
246        and made deferred FP contexts work on the MIPS.
247        * rtems/score/cpu.h: Modified to support above changes.
248
2492002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
250
251        * rtems/Makefile.am: Removed.
252        * rtems/score/Makefile.am: Removed.
253        * configure.ac: Reflect changes above.
254        * Makefile.am: Reflect changes above.
255
2562002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
257
258        * asm.h: Remove #include <rtems/score/targopts.h>.
259        Add #include <rtems/score/cpuopts.h>.
260        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
261
262
2632001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
264
265        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
266
2672001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
268
269        * Makefile.am: Add multilib support.
270
2712001-11-28      Joel Sherrill <joel@OARcorp.com>,
272
273        This was tracked as PR91.
274        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
275        is used to specify if the port uses the standard macro for this (FALSE).
276        A TRUE setting indicates the port provides its own implementation.
277
2782001-10-12      Joel Sherrill <joel@OARcorp.com>
279
280        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
281        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
282        Wayne Bullaughey <wayne@wmi.com>.
283
2842001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
285
286        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
287        * configure.in: Remove.
288        * configure.ac: New file, generated from configure.in by autoupdate.
289
2902001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
291
292        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
293        * Makefile.am: Use 'PREINSTALL_FILES ='.
294
2952001-07-03      Joel Sherrill <joel@OARcorp.com>
296
297        * cpu.c: Fixed typo.
298
2992000-05-24      Joel Sherrill <joel@OARcorp.com>
300
301        * rtems/score/mips.h: Added constants for MIPS exception numbers.
302        All exceptions should be given low numbers and thus can be installed
303        and processed in a uniform manner.  Variances between various MIPS
304        ISA levels were not accounted for.
305
3062001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
307
308        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
309        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
310
3112001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
312
313        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
314        the context initialization to account for floating point tasks. 
315        * rtems/score/mips.h: Added the routines mips_set_cause(),
316        mips_get_fcr31(), and mips_set_fcr31().
317        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
318
3192001-05-07      Joel Sherrill <joel@OARcorp.com>
320
321        * cpu_asm.S: Merged patches from Gregory Menke
322        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
323        stack usage and include nops in the delay slots.
324
3252001-04-20      Joel Sherrill <joel@OARcorp.com>
326
327        * cpu_asm.S: Added code to save and restore SR and EPC to
328        properly support nested interrupts.  Note that the ISR
329        (not RTEMS) enables interrupts allowing the nesting to occur.
330
3312001-03-14      Joel Sherrill <joel@OARcorp.com>
332
333        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
334        Removed unused variable _CPU_Thread_dispatch_pointer
335        and cleaned numerous comments.
336       
3372001-03-13      Joel Sherrill <joel@OARcorp.com>
338
339        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
340        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
341        Also reimplemented some assembly routines in C further reducing
342        the amount of assembly and increasing maintainability.
343
3442001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
345
346        * Makefile.am, rtems/score/Makefile.am:
347        Apply include_*HEADERS instead of H_FILES.
348
3492001-01-12      Joel Sherrill <joel@OARcorp.com>
350
351        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
352        register constraints from "general" to "register".
353
3542001-01-09      Joel Sherrill <joel@OARcorp.com>
355
356        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
357        to make it easier to conditionalize the code for various ISA levels.
358
3592001-01-08      Joel Sherrill <joel@OARcorp.com>
360
361        * idtcpu.h: Commented out definition of "wait".  It was stupid to
362        use such a common word as a macro.
363        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
364        * rtems/score/mips.h: Added include of <idtcpu.h>.
365        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
366
3672001-01-03      Joel Sherrill <joel@OARcorp.com>
368
369        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
370        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
371
3722000-12-19      Joel Sherrill <joel@OARcorp.com>
373
374        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
375        Previous code resulting in the interrupted immediately returning
376        to the caller of the routine it was inside.
377
3782000-12-19      Joel Sherrill <joel@OARcorp.com>
379
380        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
381        because it has not been allocated yet.
382
3832000-12-13      Joel Sherrill <joel@OARcorp.com>
384
385        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
386        * cpu_asm.S: Removed assembly language to vector ISR handler
387        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
388        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
389        longer a constant -- get the real value from libcpu.
390
3912000-12-13      Joel Sherrill <joel@OARcorp.com>
392
393        * cpu_asm.h: Removed.
394        * Makefile.am: Remove cpu_asm.h.
395        * rtems/score/mips64orion.h: Renamed mips.h.
396        * rtems/score/mips.h: New file, formerly mips64orion.h.
397        Header rewritten.
398        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
399        mips_disable_in_interrupt_mask): New macros.
400        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
401        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
402        few defines that were in <cpu_asm.h>.
403        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
404        MIPS ISA 3 is still in assembly for now.
405        (_CPU_Thread_Idle_body): Rewrote in C.
406        * cpu_asm.S: Rewrote file header.
407        (FRAME,ENDFRAME) now in asm.h.
408        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
409        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
410        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
411        leaves other bits in SR alone on task switch.
412        (mips_enable_interrupts,mips_disable_interrupts,
413        mips_enable_global_interrupts,mips_disable_global_interrupts,
414        disable_int, enable_int): Removed.
415        (mips_get_sr): Rewritten as C macro.
416        (_CPU_Thread_Idle_body): Rewritten in C.
417        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
418        placed in libcpu.
419        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
420        to libcpu/mips/shared/interrupts.
421        (general): Cleaned up comment blocks and #if 0 areas.
422        * idtcpu.h: Made ifdef report an error.
423        * iregdef.h: Removed warning.
424        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
425        number defined by libcpu.
426        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
427        to access SR.
428        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
429        (_CPU_Context_Initialize): Honor ISR level in task initialization.
430        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
431
4322000-12-06      Joel Sherrill <joel@OARcorp.com>
433
434        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
435        context should be 32 not 64 bits.
436
4372000-11-30      Joel Sherrill <joel@OARcorp.com>
438
439        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
440        correct name of _CPU_Context_switch_restore.  Added dummy
441        version of exc_utlb_code() so applications would link.
442
4432000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
444
445        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
446
4472000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
448
449        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
450
4512000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
452
453        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
454        Switch to GNU canonicalization.
455
4562000-10-24      Alan Cudmore <alanc@linuxstart.com> and
457        Joel Sherrill <joel@OARcorp.com>
458
459        * This is a major reworking of the mips64orion port to use
460        gcc predefines as much as possible and a big push to multilib
461        the mips port.  The mips64orion port was copied/renamed to mips
462        to be more like other GNU tools.  Alan did most of the technical
463        work of determining how to map old macro names used by the mips64orion
464        port to standard compiler macro definitions.  Joel did the merge
465        with CVS magic to keep individual file history and did the BSP
466        modifications. Details follow:
467        * Makefile.am: idtmon.h in mips64orion port not present.
468        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
469        * cpu.c: Comments added.
470        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
471        First attempt at exception/interrupt processing for ISA level 1
472        and minus any use of IDT/MON added.
473        * idtcpu.h: Conditionals changed to use gcc predefines.
474        * iregdef.h: Ditto.
475        * cpu_asm.h: No real change.  Merger required commit.
476        * rtems/Makefile.am: Ditto.
477        * rtems/score/Makefile.am: Ditto.
478        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
479        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
480        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
481
4822000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
483
484        * Makefile.am: Include compile.am.
485
4862000-08-10      Joel Sherrill <joel@OARcorp.com>
487
488        * ChangeLog: New file.
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