source: rtems/cpukit/score/cpu/mips/ChangeLog @ b7b6100

4.104.114.95
Last change on this file since b7b6100 was b7b6100, checked in by Ralf Corsepius <ralf.corsepius@…>, on 08/21/08 at 04:10:51

2008-08-21 Ralf Corsépius <ralf.corsepius@…>

  • rtems/score/types.h: Include stdbool.h. Use bool as base-type for boolean.
  • Property mode set to 100644
File size: 20.1 KB
Line 
12008-08-21      Ralf Corsépius <ralf.corsepius@rtems.org>
2
3        * rtems/score/types.h: Include stdbool.h.
4        Use bool as base-type for boolean.
5
62008-07-31      Joel Sherrill <joel.sherrill@OARcorp.com>
7
8        * cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads.
9
102008-06-05      Joel Sherrill <joel.sherrill@OARcorp.com>
11
12        * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
13        parameter to indicate that the port uses the Simple Vectored
14        Interrupt model or the Programmable Interrupt Controller Model. The
15        PIC model is implemented primarily in the BSP and it is responsible
16        for all memory allocation.
17
182008-06-04      Joel Sherrill <joel.sherrill@OARcorp.com>
19
20        * rtems/score/cpu.h: Use a constant for CPU_STACK_MINIMUM_SIZE so it
21        can be used in cpp expressions. Using sizeof() requires actually
22        compiling the file.
23
242007-12-17      Joel Sherrill <joel.sherrill@oarcorp.com>
25
26        * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.
27
282007-12-04      Joel Sherrill <joel.sherrill@OARcorp.com>
29
30        * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU
31        Table to Configuration Table. Eliminate CPU Table from all ports.
32        Delete references to CPU Table in all forms.
33
342007-12-03      Joel Sherrill <joel.sherrill@OARcorp.com>
35
36        * rtems/score/cpu.h: Moved most of the remaining CPU Table fields to
37        the Configuration Table. This included pretasking_hook,
38        predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace,
39        extra_mpci_receive_server_stack, stack_allocate_hook, and
40        stack_free_hook. As a side-effect of this effort some multiprocessing
41        code was made conditional and some style clean up occurred.
42
432007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
44
45        * rtems/score/cpu.h: Eliminate the clicks_per_microsecond field in the
46        MIPS CPU Table and define another mechanism for drivers to obtain
47        this information.
48
492007-08-04      Ralf Corsépius <ralf.corsepius@rtems.org>
50
51        * rtems/score/cpu.h: Use uintptr_t instead of uint32_t.
52
532007-05-09      Ralf Corsépius <ralf.corsepius@rtems.org>
54
55        * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
56
572007-04-17      Ralf Corsépius <ralf.corsepius@rtems.org>
58
59        * rtems/score/cpu.h:
60          Use Context_Control_fp* instead of void* for fp_contexts.
61          Eliminate evil casts.
62
632006-11-17      Ralf Corsépius <ralf.corsepius@rtems.org>
64
65        * rtems/score/types.h: Remove unsigned64, signed64.
66
672006-06-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
68
69        * cpu.c: Added __mips==32 to fix build problems on those targets
70        caused by the Bruce Robinson.
71
722006-06-08 Bruce Robinson <brucer@pmccorp.com>
73
74        * cpu.c: Add int64 types for __mips==3 cpus, incorporate
75           mips_interrupt_mask() into mask computations
76        * cpu_asm.S: Add int64 register save/restores for __mips==3 cpus.  Adjustment
77           of mips1 vs mips3 macros.
78        * cpu.h: Add int64 types for __mips==3 cpus.
79       
802006-03-17      Ralf Corsepius <ralf.corsepius@rtems.org>
81
82        * cpu.c (_CPU_Initialize): Add fpu initialization.
83        * rtems/score/cpu.h: Setup CPU_*_ENDIAN from GCC's__MIPS{EL|EB}__.
84        (Partial merger of submission by Bruce Robinson <brucer@pmccorp.com>).
85
862006-01-16      Joel Sherrill <joel@OARcorp.com>
87
88        * rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
89        As a side-effect, grammar and spelling errors were corrected, spacing
90        errors were address, and some variable names were improved.
91
922005-11-18      Joel Sherrill <joel@OARcorp.com>
93
94        * rtems/score/cpu.h: Eliminate use of unsigned32.
95
962005-11-08      Ralf Corsepius <ralf.corsepius@rtems.org>
97
98        * rtems/score/types.h: Eliminate unsigned16, unsigned32.
99
1002005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
101
102        * rtems/asm.h: Remove private version of CONCAT macros.
103        Include <rtems/concat.h> instead.
104
1052005-04-26      Joel Sherrill <joel@OARcorp.com>
106
107        * rtems/asm.h: Eliminate warnings.
108
1092005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
110
111        * Makefile.am: Split out preinstallation rules.
112        * preinstall.am: New (Split out from Makefile.am).
113
1142005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
115
116        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
117        Header guards cleanup.
118
1192005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
120
121        PR 754/rtems
122        * rtems/asm.h: New (relocated from .).
123        * asm.h: Remove (moved to rtems/asm.h).
124        * Makefile.am: Reflect changes above.
125
1262005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
127
128        PR rtems/752
129        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
130        New header guards.
131        * idtcpu.h, iregdef.h: Remove.
132        * Makefile.am: Reflect changes above.
133
1342004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
135
136        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
137        New header guards.
138
1392005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
140
141        * rtems/score/types.h: Remove signed8, signed16, signed32,
142        unsigned8, unsigned16, unsigned32.
143
1442005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
145
146        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
147
1482005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
149
150        * rtems/score/types.h: #include <rtems/stdint.h>.
151
1522005-01-07      Joel Sherrill <joel@OARcorp.com>
153
154        * rtems/score/cpu.h: Remove warnings.
155
1562005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
157
158        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
159
1602005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
161
162        PR 739
163        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
164        when compiling cpu_asm.S.  Problem was a #define sneaked in in
165        version 1.11, no ill effects would have only affected R4000
166        builds.
167
1682005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
169
170        PR 737
171        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
172        slot when compiling cpu_asm.S
173
1742005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
175
176        * Makefile.am: Remove build-variant support.
177
1782004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
179
180        PR 730
181        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
182        for rtems-4.7.
183
1842004-04-09      Joel Sherrill <joel@OARcorp.com>
185
186        PR 605/bsps
187        * cpu.c: Do not use C++ style comments.
188
1892004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
190        PR 601
191        * cpu_asm.S: Added __mips==32 support for R4000 processors running
192        32 bit code.  Fixed #define problems that caused fpu code to
193        always be included even when no fpu is present.
194
1952004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
196
197        PR 598/bsps
198        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
199        status/control register on context switches. Missing this register
200        was causing intermittent floating point errors.
201
2022003-09-04      Joel Sherrill <joel@OARcorp.com>
203
204        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
205        rtems/score/types.h: URL for license changed.
206
2072003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
208
209        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
210
2112003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
212
213        * configure.ac: Remove AC_CONFIG_AUX_DIR.
214
2152002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
216
217        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
218        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
219
2202002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
221
222        * configure.ac: Fix package name.
223
2242002-11-04      Joel Sherrill <joel@OARcorp.com>
225
226        * idtcpu.h: Removed warning.
227
2282002-11-01      Joel Sherrill <joel@OARcorp.com>
229
230        * idtcpu.h: Removed warnings.
231
2322002-10-28      Joel Sherrill <joel@OARcorp.com>
233
234        * idtcpu.h: Removed warning by turning extra token at the end of
235        an endif into a comment.
236
2372002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
238
239        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
240
2412002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
242
243        * .cvsignore: Reformat.
244        Add autom4te*cache.
245        Remove autom4te.cache.
246
2472002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
248
249        * cpu_asm.S: Clarified some comments, removed code that forced
250        SR_IEP on when returning from an interrupt.
251
2522002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
253
254        * configure.ac: Add RTEMS_PROG_CCAS
255
2562002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
257
258        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
259        Add AC_PROG_RANLIB.
260
2612002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
262        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
263        deadlock caused by interrupt arriving while dispatching.
264       
2652002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
266
267        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
268        Use ../../../aclocal.
269
2702001-04-03      Joel Sherrill <joel@OARcorp.com>
271
272        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
273        * rtems/score/mipstypes.h: Removed.
274        * rtems/score/types.h: New file via CVS magic.
275        * Makefile.am, rtems/score/cpu.h: Account for name change.
276
2772002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
278
279        * configure.ac:
280        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
281        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
282        * Makefile.am: Remove AUTOMAKE_OPTIONS.
283
2842002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
285
286        * cpu_asm.S: Now compiles on 4600 and 4650.
287
2882002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
289
290        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
291        * rtems/score/cpu.h: Fixed register numbering in comments and made
292        interrupt enable/disable more robust.
293       
2942002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
295        * cpu_asm.S: Added support for the debug exception vector, cleaned
296        up the exception processing & exception return stuff.  Re-added
297        EPC in the task context structure so the gdb stub will know where
298        a thread is executing.  Should've left it there in the first place...
299        * idtcpu.h: Added support for the debug exception vector.
300        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
301        stack frame in an interrupt so context switch code can get the
302        userspace EPC when scheduling.
303        * rtems/score/cpu.h: Re-added EPC to the task context.
304
3052002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
306
307        * cpu_asm.S: Fixed exception return address, modified FP context
308        switch so FPU is properly enabled and also doesn't screw up the
309        exception FP handling.
310        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
311        returning from exceptions.
312        * iregdef.h: Added R_TAR to the stack frame so the target address
313        can be saved on a per-exception basis.  The new entry is past the
314        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
315        stuff.
316        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
317        to obtain FPU defines without syntax errors generated by the C
318        defintions.
319        * cpu.c: Improved interrupt level saves & restores.
320       
3212002-02-08      Joel Sherrill <joel@OARcorp.com>
322
323        * iregdef.h, rtems/score/cpu.h: Reordered register in the
324        exception stack frame to better match gdb's expectations.
325
3262001-02-05      Joel Sherrill <joel@OARcorp.com>
327
328        * cpu_asm.S: Enhanced to save/restore more registers on
329        exceptions.
330        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
331        register individually and document when it is saved.
332        * idtcpu.h: Added constants for the coprocessor 1 registers
333        revision and status.
334
3352001-02-05      Joel Sherrill <joel@OARcorp.com>
336
337        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
338
3392001-02-04      Joel Sherrill <joel@OARcorp.com>
340
341        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
342        in the previous patch that has now been confirmed.
343
3442001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
345
346        * cpu.c: Enhancements and fixes for modifying the SR when changing
347        the interrupt level.
348        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
349        managed on a per-task basis, improved handling of interrupt levels,
350        and made deferred FP contexts work on the MIPS.
351        * rtems/score/cpu.h: Modified to support above changes.
352
3532002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
354
355        * rtems/Makefile.am: Removed.
356        * rtems/score/Makefile.am: Removed.
357        * configure.ac: Reflect changes above.
358        * Makefile.am: Reflect changes above.
359
3602002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
361
362        * asm.h: Remove #include <rtems/score/targopts.h>.
363        Add #include <rtems/score/cpuopts.h>.
364        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
365
366
3672001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
368
369        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
370
3712001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
372
373        * Makefile.am: Add multilib support.
374
3752001-11-28      Joel Sherrill <joel@OARcorp.com>,
376
377        This was tracked as PR91.
378        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
379        is used to specify if the port uses the standard macro for this (FALSE).
380        A TRUE setting indicates the port provides its own implementation.
381
3822001-10-12      Joel Sherrill <joel@OARcorp.com>
383
384        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
385        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
386        Wayne Bullaughey <wayne@wmi.com>.
387
3882001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
389
390        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
391        * configure.in: Remove.
392        * configure.ac: New file, generated from configure.in by autoupdate.
393
3942001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
395
396        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
397        * Makefile.am: Use 'PREINSTALL_FILES ='.
398
3992001-07-03      Joel Sherrill <joel@OARcorp.com>
400
401        * cpu.c: Fixed typo.
402
4032000-05-24      Joel Sherrill <joel@OARcorp.com>
404
405        * rtems/score/mips.h: Added constants for MIPS exception numbers.
406        All exceptions should be given low numbers and thus can be installed
407        and processed in a uniform manner.  Variances between various MIPS
408        ISA levels were not accounted for.
409
4102001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
411
412        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
413        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
414
4152001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
416
417        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
418        the context initialization to account for floating point tasks. 
419        * rtems/score/mips.h: Added the routines mips_set_cause(),
420        mips_get_fcr31(), and mips_set_fcr31().
421        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
422
4232001-05-07      Joel Sherrill <joel@OARcorp.com>
424
425        * cpu_asm.S: Merged patches from Gregory Menke
426        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
427        stack usage and include nops in the delay slots.
428
4292001-04-20      Joel Sherrill <joel@OARcorp.com>
430
431        * cpu_asm.S: Added code to save and restore SR and EPC to
432        properly support nested interrupts.  Note that the ISR
433        (not RTEMS) enables interrupts allowing the nesting to occur.
434
4352001-03-14      Joel Sherrill <joel@OARcorp.com>
436
437        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
438        Removed unused variable _CPU_Thread_dispatch_pointer
439        and cleaned numerous comments.
440       
4412001-03-13      Joel Sherrill <joel@OARcorp.com>
442
443        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
444        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
445        Also reimplemented some assembly routines in C further reducing
446        the amount of assembly and increasing maintainability.
447
4482001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
449
450        * Makefile.am, rtems/score/Makefile.am:
451        Apply include_*HEADERS instead of H_FILES.
452
4532001-01-12      Joel Sherrill <joel@OARcorp.com>
454
455        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
456        register constraints from "general" to "register".
457
4582001-01-09      Joel Sherrill <joel@OARcorp.com>
459
460        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
461        to make it easier to conditionalize the code for various ISA levels.
462
4632001-01-08      Joel Sherrill <joel@OARcorp.com>
464
465        * idtcpu.h: Commented out definition of "wait".  It was stupid to
466        use such a common word as a macro.
467        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
468        * rtems/score/mips.h: Added include of <idtcpu.h>.
469        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
470
4712001-01-03      Joel Sherrill <joel@OARcorp.com>
472
473        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
474        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
475
4762000-12-19      Joel Sherrill <joel@OARcorp.com>
477
478        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
479        Previous code resulting in the interrupted immediately returning
480        to the caller of the routine it was inside.
481
4822000-12-19      Joel Sherrill <joel@OARcorp.com>
483
484        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
485        because it has not been allocated yet.
486
4872000-12-13      Joel Sherrill <joel@OARcorp.com>
488
489        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
490        * cpu_asm.S: Removed assembly language to vector ISR handler
491        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
492        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
493        longer a constant -- get the real value from libcpu.
494
4952000-12-13      Joel Sherrill <joel@OARcorp.com>
496
497        * cpu_asm.h: Removed.
498        * Makefile.am: Remove cpu_asm.h.
499        * rtems/score/mips64orion.h: Renamed mips.h.
500        * rtems/score/mips.h: New file, formerly mips64orion.h.
501        Header rewritten.
502        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
503        mips_disable_in_interrupt_mask): New macros.
504        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
505        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
506        few defines that were in <cpu_asm.h>.
507        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
508        MIPS ISA 3 is still in assembly for now.
509        (_CPU_Thread_Idle_body): Rewrote in C.
510        * cpu_asm.S: Rewrote file header.
511        (FRAME,ENDFRAME) now in asm.h.
512        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
513        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
514        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
515        leaves other bits in SR alone on task switch.
516        (mips_enable_interrupts,mips_disable_interrupts,
517        mips_enable_global_interrupts,mips_disable_global_interrupts,
518        disable_int, enable_int): Removed.
519        (mips_get_sr): Rewritten as C macro.
520        (_CPU_Thread_Idle_body): Rewritten in C.
521        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
522        placed in libcpu.
523        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
524        to libcpu/mips/shared/interrupts.
525        (general): Cleaned up comment blocks and #if 0 areas.
526        * idtcpu.h: Made ifdef report an error.
527        * iregdef.h: Removed warning.
528        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
529        number defined by libcpu.
530        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
531        to access SR.
532        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
533        (_CPU_Context_Initialize): Honor ISR level in task initialization.
534        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
535
5362000-12-06      Joel Sherrill <joel@OARcorp.com>
537
538        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
539        context should be 32 not 64 bits.
540
5412000-11-30      Joel Sherrill <joel@OARcorp.com>
542
543        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
544        correct name of _CPU_Context_switch_restore.  Added dummy
545        version of exc_utlb_code() so applications would link.
546
5472000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
548
549        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
550
5512000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
552
553        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
554
5552000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
556
557        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
558        Switch to GNU canonicalization.
559
5602000-10-24      Alan Cudmore <alanc@linuxstart.com> and
561        Joel Sherrill <joel@OARcorp.com>
562
563        * This is a major reworking of the mips64orion port to use
564        gcc predefines as much as possible and a big push to multilib
565        the mips port.  The mips64orion port was copied/renamed to mips
566        to be more like other GNU tools.  Alan did most of the technical
567        work of determining how to map old macro names used by the mips64orion
568        port to standard compiler macro definitions.  Joel did the merge
569        with CVS magic to keep individual file history and did the BSP
570        modifications. Details follow:
571        * Makefile.am: idtmon.h in mips64orion port not present.
572        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
573        * cpu.c: Comments added.
574        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
575        First attempt at exception/interrupt processing for ISA level 1
576        and minus any use of IDT/MON added.
577        * idtcpu.h: Conditionals changed to use gcc predefines.
578        * iregdef.h: Ditto.
579        * cpu_asm.h: No real change.  Merger required commit.
580        * rtems/Makefile.am: Ditto.
581        * rtems/score/Makefile.am: Ditto.
582        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
583        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
584        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
585
5862000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
587
588        * Makefile.am: Include compile.am.
589
5902000-08-10      Joel Sherrill <joel@OARcorp.com>
591
592        * ChangeLog: New file.
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