source: rtems/cpukit/score/cpu/mips/ChangeLog @ b72e847b

4.8
Last change on this file since b72e847b was 72b4469, checked in by Ralf Corsepius <ralf.corsepius@…>, on Aug 4, 2007 at 6:07:30 AM

2007-08-04 Ralf Corsépius <ralf.corsepius@…>

  • rtems/score/cpu.h: Use uintptr_t instead of uint32_t.
  • Property mode set to 100644
File size: 18.3 KB
Line 
12007-08-04      Ralf Corsépius <ralf.corsepius@rtems.org>
2
3        * rtems/score/cpu.h: Use uintptr_t instead of uint32_t.
4
52007-05-09      Ralf Corsépius <ralf.corsepius@rtems.org>
6
7        * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
8
92007-04-17      Ralf Corsépius <ralf.corsepius@rtems.org>
10
11        * rtems/score/cpu.h:
12          Use Context_Control_fp* instead of void* for fp_contexts.
13          Eliminate evil casts.
14
152006-11-17      Ralf Corsépius <ralf.corsepius@rtems.org>
16
17        * rtems/score/types.h: Remove unsigned64, signed64.
18
192006-06-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
20
21        * cpu.c: Added __mips==32 to fix build problems on those targets
22        caused by the Bruce Robinson.
23
242006-06-08 Bruce Robinson <brucer@pmccorp.com>
25
26        * cpu.c: Add int64 types for __mips==3 cpus, incorporate
27           mips_interrupt_mask() into mask computations
28        * cpu_asm.S: Add int64 register save/restores for __mips==3 cpus.  Adjustment
29           of mips1 vs mips3 macros.
30        * cpu.h: Add int64 types for __mips==3 cpus.
31       
322006-03-17      Ralf Corsepius <ralf.corsepius@rtems.org>
33
34        * cpu.c (_CPU_Initialize): Add fpu initialization.
35        * rtems/score/cpu.h: Setup CPU_*_ENDIAN from GCC's__MIPS{EL|EB}__.
36        (Partial merger of submission by Bruce Robinson <brucer@pmccorp.com>).
37
382006-01-16      Joel Sherrill <joel@OARcorp.com>
39
40        * rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
41        As a side-effect, grammar and spelling errors were corrected, spacing
42        errors were address, and some variable names were improved.
43
442005-11-18      Joel Sherrill <joel@OARcorp.com>
45
46        * rtems/score/cpu.h: Eliminate use of unsigned32.
47
482005-11-08      Ralf Corsepius <ralf.corsepius@rtems.org>
49
50        * rtems/score/types.h: Eliminate unsigned16, unsigned32.
51
522005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
53
54        * rtems/asm.h: Remove private version of CONCAT macros.
55        Include <rtems/concat.h> instead.
56
572005-04-26      Joel Sherrill <joel@OARcorp.com>
58
59        * rtems/asm.h: Eliminate warnings.
60
612005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
62
63        * Makefile.am: Split out preinstallation rules.
64        * preinstall.am: New (Split out from Makefile.am).
65
662005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
67
68        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
69        Header guards cleanup.
70
712005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
72
73        PR 754/rtems
74        * rtems/asm.h: New (relocated from .).
75        * asm.h: Remove (moved to rtems/asm.h).
76        * Makefile.am: Reflect changes above.
77
782005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
79
80        PR rtems/752
81        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
82        New header guards.
83        * idtcpu.h, iregdef.h: Remove.
84        * Makefile.am: Reflect changes above.
85
862004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
87
88        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
89        New header guards.
90
912005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
92
93        * rtems/score/types.h: Remove signed8, signed16, signed32,
94        unsigned8, unsigned16, unsigned32.
95
962005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
97
98        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
99
1002005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
101
102        * rtems/score/types.h: #include <rtems/stdint.h>.
103
1042005-01-07      Joel Sherrill <joel@OARcorp.com>
105
106        * rtems/score/cpu.h: Remove warnings.
107
1082005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
109
110        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
111
1122005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
113
114        PR 739
115        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
116        when compiling cpu_asm.S.  Problem was a #define sneaked in in
117        version 1.11, no ill effects would have only affected R4000
118        builds.
119
1202005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
121
122        PR 737
123        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
124        slot when compiling cpu_asm.S
125
1262005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
127
128        * Makefile.am: Remove build-variant support.
129
1302004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
131
132        PR 730
133        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
134        for rtems-4.7.
135
1362004-04-09      Joel Sherrill <joel@OARcorp.com>
137
138        PR 605/bsps
139        * cpu.c: Do not use C++ style comments.
140
1412004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
142        PR 601
143        * cpu_asm.S: Added __mips==32 support for R4000 processors running
144        32 bit code.  Fixed #define problems that caused fpu code to
145        always be included even when no fpu is present.
146
1472004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
148
149        PR 598/bsps
150        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
151        status/control register on context switches. Missing this register
152        was causing intermittent floating point errors.
153
1542003-09-04      Joel Sherrill <joel@OARcorp.com>
155
156        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
157        rtems/score/types.h: URL for license changed.
158
1592003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
160
161        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
162
1632003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
164
165        * configure.ac: Remove AC_CONFIG_AUX_DIR.
166
1672002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
168
169        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
170        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
171
1722002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
173
174        * configure.ac: Fix package name.
175
1762002-11-04      Joel Sherrill <joel@OARcorp.com>
177
178        * idtcpu.h: Removed warning.
179
1802002-11-01      Joel Sherrill <joel@OARcorp.com>
181
182        * idtcpu.h: Removed warnings.
183
1842002-10-28      Joel Sherrill <joel@OARcorp.com>
185
186        * idtcpu.h: Removed warning by turning extra token at the end of
187        an endif into a comment.
188
1892002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
190
191        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
192
1932002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
194
195        * .cvsignore: Reformat.
196        Add autom4te*cache.
197        Remove autom4te.cache.
198
1992002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
200
201        * cpu_asm.S: Clarified some comments, removed code that forced
202        SR_IEP on when returning from an interrupt.
203
2042002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
205
206        * configure.ac: Add RTEMS_PROG_CCAS
207
2082002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
209
210        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
211        Add AC_PROG_RANLIB.
212
2132002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
214        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
215        deadlock caused by interrupt arriving while dispatching.
216       
2172002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
218
219        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
220        Use ../../../aclocal.
221
2222001-04-03      Joel Sherrill <joel@OARcorp.com>
223
224        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
225        * rtems/score/mipstypes.h: Removed.
226        * rtems/score/types.h: New file via CVS magic.
227        * Makefile.am, rtems/score/cpu.h: Account for name change.
228
2292002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
230
231        * configure.ac:
232        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
233        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
234        * Makefile.am: Remove AUTOMAKE_OPTIONS.
235
2362002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
237
238        * cpu_asm.S: Now compiles on 4600 and 4650.
239
2402002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
241
242        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
243        * rtems/score/cpu.h: Fixed register numbering in comments and made
244        interrupt enable/disable more robust.
245       
2462002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
247        * cpu_asm.S: Added support for the debug exception vector, cleaned
248        up the exception processing & exception return stuff.  Re-added
249        EPC in the task context structure so the gdb stub will know where
250        a thread is executing.  Should've left it there in the first place...
251        * idtcpu.h: Added support for the debug exception vector.
252        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
253        stack frame in an interrupt so context switch code can get the
254        userspace EPC when scheduling.
255        * rtems/score/cpu.h: Re-added EPC to the task context.
256
2572002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
258
259        * cpu_asm.S: Fixed exception return address, modified FP context
260        switch so FPU is properly enabled and also doesn't screw up the
261        exception FP handling.
262        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
263        returning from exceptions.
264        * iregdef.h: Added R_TAR to the stack frame so the target address
265        can be saved on a per-exception basis.  The new entry is past the
266        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
267        stuff.
268        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
269        to obtain FPU defines without syntax errors generated by the C
270        defintions.
271        * cpu.c: Improved interrupt level saves & restores.
272       
2732002-02-08      Joel Sherrill <joel@OARcorp.com>
274
275        * iregdef.h, rtems/score/cpu.h: Reordered register in the
276        exception stack frame to better match gdb's expectations.
277
2782001-02-05      Joel Sherrill <joel@OARcorp.com>
279
280        * cpu_asm.S: Enhanced to save/restore more registers on
281        exceptions.
282        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
283        register individually and document when it is saved.
284        * idtcpu.h: Added constants for the coprocessor 1 registers
285        revision and status.
286
2872001-02-05      Joel Sherrill <joel@OARcorp.com>
288
289        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
290
2912001-02-04      Joel Sherrill <joel@OARcorp.com>
292
293        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
294        in the previous patch that has now been confirmed.
295
2962001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
297
298        * cpu.c: Enhancements and fixes for modifying the SR when changing
299        the interrupt level.
300        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
301        managed on a per-task basis, improved handling of interrupt levels,
302        and made deferred FP contexts work on the MIPS.
303        * rtems/score/cpu.h: Modified to support above changes.
304
3052002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
306
307        * rtems/Makefile.am: Removed.
308        * rtems/score/Makefile.am: Removed.
309        * configure.ac: Reflect changes above.
310        * Makefile.am: Reflect changes above.
311
3122002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
313
314        * asm.h: Remove #include <rtems/score/targopts.h>.
315        Add #include <rtems/score/cpuopts.h>.
316        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
317
318
3192001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
320
321        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
322
3232001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
324
325        * Makefile.am: Add multilib support.
326
3272001-11-28      Joel Sherrill <joel@OARcorp.com>,
328
329        This was tracked as PR91.
330        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
331        is used to specify if the port uses the standard macro for this (FALSE).
332        A TRUE setting indicates the port provides its own implementation.
333
3342001-10-12      Joel Sherrill <joel@OARcorp.com>
335
336        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
337        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
338        Wayne Bullaughey <wayne@wmi.com>.
339
3402001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
341
342        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
343        * configure.in: Remove.
344        * configure.ac: New file, generated from configure.in by autoupdate.
345
3462001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
347
348        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
349        * Makefile.am: Use 'PREINSTALL_FILES ='.
350
3512001-07-03      Joel Sherrill <joel@OARcorp.com>
352
353        * cpu.c: Fixed typo.
354
3552000-05-24      Joel Sherrill <joel@OARcorp.com>
356
357        * rtems/score/mips.h: Added constants for MIPS exception numbers.
358        All exceptions should be given low numbers and thus can be installed
359        and processed in a uniform manner.  Variances between various MIPS
360        ISA levels were not accounted for.
361
3622001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
363
364        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
365        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
366
3672001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
368
369        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
370        the context initialization to account for floating point tasks. 
371        * rtems/score/mips.h: Added the routines mips_set_cause(),
372        mips_get_fcr31(), and mips_set_fcr31().
373        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
374
3752001-05-07      Joel Sherrill <joel@OARcorp.com>
376
377        * cpu_asm.S: Merged patches from Gregory Menke
378        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
379        stack usage and include nops in the delay slots.
380
3812001-04-20      Joel Sherrill <joel@OARcorp.com>
382
383        * cpu_asm.S: Added code to save and restore SR and EPC to
384        properly support nested interrupts.  Note that the ISR
385        (not RTEMS) enables interrupts allowing the nesting to occur.
386
3872001-03-14      Joel Sherrill <joel@OARcorp.com>
388
389        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
390        Removed unused variable _CPU_Thread_dispatch_pointer
391        and cleaned numerous comments.
392       
3932001-03-13      Joel Sherrill <joel@OARcorp.com>
394
395        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
396        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
397        Also reimplemented some assembly routines in C further reducing
398        the amount of assembly and increasing maintainability.
399
4002001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
401
402        * Makefile.am, rtems/score/Makefile.am:
403        Apply include_*HEADERS instead of H_FILES.
404
4052001-01-12      Joel Sherrill <joel@OARcorp.com>
406
407        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
408        register constraints from "general" to "register".
409
4102001-01-09      Joel Sherrill <joel@OARcorp.com>
411
412        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
413        to make it easier to conditionalize the code for various ISA levels.
414
4152001-01-08      Joel Sherrill <joel@OARcorp.com>
416
417        * idtcpu.h: Commented out definition of "wait".  It was stupid to
418        use such a common word as a macro.
419        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
420        * rtems/score/mips.h: Added include of <idtcpu.h>.
421        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
422
4232001-01-03      Joel Sherrill <joel@OARcorp.com>
424
425        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
426        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
427
4282000-12-19      Joel Sherrill <joel@OARcorp.com>
429
430        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
431        Previous code resulting in the interrupted immediately returning
432        to the caller of the routine it was inside.
433
4342000-12-19      Joel Sherrill <joel@OARcorp.com>
435
436        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
437        because it has not been allocated yet.
438
4392000-12-13      Joel Sherrill <joel@OARcorp.com>
440
441        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
442        * cpu_asm.S: Removed assembly language to vector ISR handler
443        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
444        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
445        longer a constant -- get the real value from libcpu.
446
4472000-12-13      Joel Sherrill <joel@OARcorp.com>
448
449        * cpu_asm.h: Removed.
450        * Makefile.am: Remove cpu_asm.h.
451        * rtems/score/mips64orion.h: Renamed mips.h.
452        * rtems/score/mips.h: New file, formerly mips64orion.h.
453        Header rewritten.
454        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
455        mips_disable_in_interrupt_mask): New macros.
456        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
457        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
458        few defines that were in <cpu_asm.h>.
459        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
460        MIPS ISA 3 is still in assembly for now.
461        (_CPU_Thread_Idle_body): Rewrote in C.
462        * cpu_asm.S: Rewrote file header.
463        (FRAME,ENDFRAME) now in asm.h.
464        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
465        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
466        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
467        leaves other bits in SR alone on task switch.
468        (mips_enable_interrupts,mips_disable_interrupts,
469        mips_enable_global_interrupts,mips_disable_global_interrupts,
470        disable_int, enable_int): Removed.
471        (mips_get_sr): Rewritten as C macro.
472        (_CPU_Thread_Idle_body): Rewritten in C.
473        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
474        placed in libcpu.
475        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
476        to libcpu/mips/shared/interrupts.
477        (general): Cleaned up comment blocks and #if 0 areas.
478        * idtcpu.h: Made ifdef report an error.
479        * iregdef.h: Removed warning.
480        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
481        number defined by libcpu.
482        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
483        to access SR.
484        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
485        (_CPU_Context_Initialize): Honor ISR level in task initialization.
486        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
487
4882000-12-06      Joel Sherrill <joel@OARcorp.com>
489
490        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
491        context should be 32 not 64 bits.
492
4932000-11-30      Joel Sherrill <joel@OARcorp.com>
494
495        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
496        correct name of _CPU_Context_switch_restore.  Added dummy
497        version of exc_utlb_code() so applications would link.
498
4992000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
500
501        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
502
5032000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
504
505        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
506
5072000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
508
509        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
510        Switch to GNU canonicalization.
511
5122000-10-24      Alan Cudmore <alanc@linuxstart.com> and
513        Joel Sherrill <joel@OARcorp.com>
514
515        * This is a major reworking of the mips64orion port to use
516        gcc predefines as much as possible and a big push to multilib
517        the mips port.  The mips64orion port was copied/renamed to mips
518        to be more like other GNU tools.  Alan did most of the technical
519        work of determining how to map old macro names used by the mips64orion
520        port to standard compiler macro definitions.  Joel did the merge
521        with CVS magic to keep individual file history and did the BSP
522        modifications. Details follow:
523        * Makefile.am: idtmon.h in mips64orion port not present.
524        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
525        * cpu.c: Comments added.
526        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
527        First attempt at exception/interrupt processing for ISA level 1
528        and minus any use of IDT/MON added.
529        * idtcpu.h: Conditionals changed to use gcc predefines.
530        * iregdef.h: Ditto.
531        * cpu_asm.h: No real change.  Merger required commit.
532        * rtems/Makefile.am: Ditto.
533        * rtems/score/Makefile.am: Ditto.
534        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
535        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
536        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
537
5382000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
539
540        * Makefile.am: Include compile.am.
541
5422000-08-10      Joel Sherrill <joel@OARcorp.com>
543
544        * ChangeLog: New file.
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