source: rtems/cpukit/score/cpu/mips/ChangeLog @ b5cdddf

4.104.114.84.95
Last change on this file since b5cdddf was b5cdddf, checked in by Ralf Corsepius <ralf.corsepius@…>, on Feb 4, 2005 at 5:38:26 AM

2005-02-04 Ralf Corsepius <ralf.corsepius@…>

  • rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h: Header guards cleanup.
  • Property mode set to 100644
File size: 16.3 KB
Line 
12005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
2
3        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
4        Header guards cleanup.
5
62005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
7
8        PR 754/rtems
9        * rtems/asm.h: New (relocated from .).
10        * asm.h: Remove (moved to rtems/asm.h).
11        * Makefile.am: Reflect changes above.
12
132005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
14
15        PR rtems/752
16        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
17        New header guards.
18        * idtcpu.h, iregdef.h: Remove.
19        * Makefile.am: Reflect changes above.
20
212004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
22
23        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
24        New header guards.
25
262005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
27
28        * rtems/score/types.h: Remove signed8, signed16, signed32,
29        unsigned8, unsigned16, unsigned32.
30
312005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
32
33        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
34
352005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
36
37        * rtems/score/types.h: #include <rtems/stdint.h>.
38
392005-01-07      Joel Sherrill <joel@OARcorp.com>
40
41        * rtems/score/cpu.h: Remove warnings.
42
432005-01-07      Ralf Corsepius <ralf.corsepius@freenet.de>
44
45        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
46
472005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
48
49        PR 739
50        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
51        when compiling cpu_asm.S.  Problem was a #define sneaked in in
52        version 1.11, no ill effects would have only affected R4000
53        builds.
54
552005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
56
57        PR 737
58        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
59        slot when compiling cpu_asm.S
60
612005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
62
63        * Makefile.am: Remove build-variant support.
64
652004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
66
67        PR 730
68        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
69        for rtems-4.7.
70
712004-04-09      Joel Sherrill <joel@OARcorp.com>
72
73        PR 605/bsps
74        * cpu.c: Do not use C++ style comments.
75
762004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
77        PR 601
78        * cpu_asm.S: Added __mips==32 support for R4000 processors running
79        32 bit code.  Fixed #define problems that caused fpu code to
80        always be included even when no fpu is present.
81
822004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
83
84        PR 598/bsps
85        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
86        status/control register on context switches. Missing this register
87        was causing intermittent floating point errors.
88
892003-09-04      Joel Sherrill <joel@OARcorp.com>
90
91        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
92        rtems/score/types.h: URL for license changed.
93
942003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
95
96        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
97
982003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
99
100        * configure.ac: Remove AC_CONFIG_AUX_DIR.
101
1022002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
103
104        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
105        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
106
1072002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
108
109        * configure.ac: Fix package name.
110
1112002-11-04      Joel Sherrill <joel@OARcorp.com>
112
113        * idtcpu.h: Removed warning.
114
1152002-11-01      Joel Sherrill <joel@OARcorp.com>
116
117        * idtcpu.h: Removed warnings.
118
1192002-10-28      Joel Sherrill <joel@OARcorp.com>
120
121        * idtcpu.h: Removed warning by turning extra token at the end of
122        an endif into a comment.
123
1242002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
125
126        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
127
1282002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
129
130        * .cvsignore: Reformat.
131        Add autom4te*cache.
132        Remove autom4te.cache.
133
1342002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
135
136        * cpu_asm.S: Clarified some comments, removed code that forced
137        SR_IEP on when returning from an interrupt.
138
1392002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
140
141        * configure.ac: Add RTEMS_PROG_CCAS
142
1432002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
144
145        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
146        Add AC_PROG_RANLIB.
147
1482002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
149        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
150        deadlock caused by interrupt arriving while dispatching.
151       
1522002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
153
154        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
155        Use ../../../aclocal.
156
1572001-04-03      Joel Sherrill <joel@OARcorp.com>
158
159        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
160        * rtems/score/mipstypes.h: Removed.
161        * rtems/score/types.h: New file via CVS magic.
162        * Makefile.am, rtems/score/cpu.h: Account for name change.
163
1642002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
165
166        * configure.ac:
167        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
168        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
169        * Makefile.am: Remove AUTOMAKE_OPTIONS.
170
1712002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
172
173        * cpu_asm.S: Now compiles on 4600 and 4650.
174
1752002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
176
177        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
178        * rtems/score/cpu.h: Fixed register numbering in comments and made
179        interrupt enable/disable more robust.
180       
1812002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
182        * cpu_asm.S: Added support for the debug exception vector, cleaned
183        up the exception processing & exception return stuff.  Re-added
184        EPC in the task context structure so the gdb stub will know where
185        a thread is executing.  Should've left it there in the first place...
186        * idtcpu.h: Added support for the debug exception vector.
187        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
188        stack frame in an interrupt so context switch code can get the
189        userspace EPC when scheduling.
190        * rtems/score/cpu.h: Re-added EPC to the task context.
191
1922002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
193
194        * cpu_asm.S: Fixed exception return address, modified FP context
195        switch so FPU is properly enabled and also doesn't screw up the
196        exception FP handling.
197        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
198        returning from exceptions.
199        * iregdef.h: Added R_TAR to the stack frame so the target address
200        can be saved on a per-exception basis.  The new entry is past the
201        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
202        stuff.
203        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
204        to obtain FPU defines without syntax errors generated by the C
205        defintions.
206        * cpu.c: Improved interrupt level saves & restores.
207       
2082002-02-08      Joel Sherrill <joel@OARcorp.com>
209
210        * iregdef.h, rtems/score/cpu.h: Reordered register in the
211        exception stack frame to better match gdb's expectations.
212
2132001-02-05      Joel Sherrill <joel@OARcorp.com>
214
215        * cpu_asm.S: Enhanced to save/restore more registers on
216        exceptions.
217        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
218        register individually and document when it is saved.
219        * idtcpu.h: Added constants for the coprocessor 1 registers
220        revision and status.
221
2222001-02-05      Joel Sherrill <joel@OARcorp.com>
223
224        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
225
2262001-02-04      Joel Sherrill <joel@OARcorp.com>
227
228        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
229        in the previous patch that has now been confirmed.
230
2312001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
232
233        * cpu.c: Enhancements and fixes for modifying the SR when changing
234        the interrupt level.
235        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
236        managed on a per-task basis, improved handling of interrupt levels,
237        and made deferred FP contexts work on the MIPS.
238        * rtems/score/cpu.h: Modified to support above changes.
239
2402002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
241
242        * rtems/Makefile.am: Removed.
243        * rtems/score/Makefile.am: Removed.
244        * configure.ac: Reflect changes above.
245        * Makefile.am: Reflect changes above.
246
2472002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
248
249        * asm.h: Remove #include <rtems/score/targopts.h>.
250        Add #include <rtems/score/cpuopts.h>.
251        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
252
253
2542001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
255
256        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
257
2582001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
259
260        * Makefile.am: Add multilib support.
261
2622001-11-28      Joel Sherrill <joel@OARcorp.com>,
263
264        This was tracked as PR91.
265        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
266        is used to specify if the port uses the standard macro for this (FALSE).
267        A TRUE setting indicates the port provides its own implementation.
268
2692001-10-12      Joel Sherrill <joel@OARcorp.com>
270
271        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
272        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
273        Wayne Bullaughey <wayne@wmi.com>.
274
2752001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
276
277        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
278        * configure.in: Remove.
279        * configure.ac: New file, generated from configure.in by autoupdate.
280
2812001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
282
283        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
284        * Makefile.am: Use 'PREINSTALL_FILES ='.
285
2862001-07-03      Joel Sherrill <joel@OARcorp.com>
287
288        * cpu.c: Fixed typo.
289
2902000-05-24      Joel Sherrill <joel@OARcorp.com>
291
292        * rtems/score/mips.h: Added constants for MIPS exception numbers.
293        All exceptions should be given low numbers and thus can be installed
294        and processed in a uniform manner.  Variances between various MIPS
295        ISA levels were not accounted for.
296
2972001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
298
299        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
300        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
301
3022001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
303
304        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
305        the context initialization to account for floating point tasks. 
306        * rtems/score/mips.h: Added the routines mips_set_cause(),
307        mips_get_fcr31(), and mips_set_fcr31().
308        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
309
3102001-05-07      Joel Sherrill <joel@OARcorp.com>
311
312        * cpu_asm.S: Merged patches from Gregory Menke
313        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
314        stack usage and include nops in the delay slots.
315
3162001-04-20      Joel Sherrill <joel@OARcorp.com>
317
318        * cpu_asm.S: Added code to save and restore SR and EPC to
319        properly support nested interrupts.  Note that the ISR
320        (not RTEMS) enables interrupts allowing the nesting to occur.
321
3222001-03-14      Joel Sherrill <joel@OARcorp.com>
323
324        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
325        Removed unused variable _CPU_Thread_dispatch_pointer
326        and cleaned numerous comments.
327       
3282001-03-13      Joel Sherrill <joel@OARcorp.com>
329
330        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
331        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
332        Also reimplemented some assembly routines in C further reducing
333        the amount of assembly and increasing maintainability.
334
3352001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
336
337        * Makefile.am, rtems/score/Makefile.am:
338        Apply include_*HEADERS instead of H_FILES.
339
3402001-01-12      Joel Sherrill <joel@OARcorp.com>
341
342        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
343        register constraints from "general" to "register".
344
3452001-01-09      Joel Sherrill <joel@OARcorp.com>
346
347        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
348        to make it easier to conditionalize the code for various ISA levels.
349
3502001-01-08      Joel Sherrill <joel@OARcorp.com>
351
352        * idtcpu.h: Commented out definition of "wait".  It was stupid to
353        use such a common word as a macro.
354        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
355        * rtems/score/mips.h: Added include of <idtcpu.h>.
356        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
357
3582001-01-03      Joel Sherrill <joel@OARcorp.com>
359
360        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
361        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
362
3632000-12-19      Joel Sherrill <joel@OARcorp.com>
364
365        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
366        Previous code resulting in the interrupted immediately returning
367        to the caller of the routine it was inside.
368
3692000-12-19      Joel Sherrill <joel@OARcorp.com>
370
371        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
372        because it has not been allocated yet.
373
3742000-12-13      Joel Sherrill <joel@OARcorp.com>
375
376        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
377        * cpu_asm.S: Removed assembly language to vector ISR handler
378        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
379        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
380        longer a constant -- get the real value from libcpu.
381
3822000-12-13      Joel Sherrill <joel@OARcorp.com>
383
384        * cpu_asm.h: Removed.
385        * Makefile.am: Remove cpu_asm.h.
386        * rtems/score/mips64orion.h: Renamed mips.h.
387        * rtems/score/mips.h: New file, formerly mips64orion.h.
388        Header rewritten.
389        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
390        mips_disable_in_interrupt_mask): New macros.
391        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
392        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
393        few defines that were in <cpu_asm.h>.
394        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
395        MIPS ISA 3 is still in assembly for now.
396        (_CPU_Thread_Idle_body): Rewrote in C.
397        * cpu_asm.S: Rewrote file header.
398        (FRAME,ENDFRAME) now in asm.h.
399        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
400        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
401        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
402        leaves other bits in SR alone on task switch.
403        (mips_enable_interrupts,mips_disable_interrupts,
404        mips_enable_global_interrupts,mips_disable_global_interrupts,
405        disable_int, enable_int): Removed.
406        (mips_get_sr): Rewritten as C macro.
407        (_CPU_Thread_Idle_body): Rewritten in C.
408        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
409        placed in libcpu.
410        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
411        to libcpu/mips/shared/interrupts.
412        (general): Cleaned up comment blocks and #if 0 areas.
413        * idtcpu.h: Made ifdef report an error.
414        * iregdef.h: Removed warning.
415        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
416        number defined by libcpu.
417        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
418        to access SR.
419        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
420        (_CPU_Context_Initialize): Honor ISR level in task initialization.
421        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
422
4232000-12-06      Joel Sherrill <joel@OARcorp.com>
424
425        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
426        context should be 32 not 64 bits.
427
4282000-11-30      Joel Sherrill <joel@OARcorp.com>
429
430        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
431        correct name of _CPU_Context_switch_restore.  Added dummy
432        version of exc_utlb_code() so applications would link.
433
4342000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
435
436        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
437
4382000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
439
440        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
441
4422000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
443
444        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
445        Switch to GNU canonicalization.
446
4472000-10-24      Alan Cudmore <alanc@linuxstart.com> and
448        Joel Sherrill <joel@OARcorp.com>
449
450        * This is a major reworking of the mips64orion port to use
451        gcc predefines as much as possible and a big push to multilib
452        the mips port.  The mips64orion port was copied/renamed to mips
453        to be more like other GNU tools.  Alan did most of the technical
454        work of determining how to map old macro names used by the mips64orion
455        port to standard compiler macro definitions.  Joel did the merge
456        with CVS magic to keep individual file history and did the BSP
457        modifications. Details follow:
458        * Makefile.am: idtmon.h in mips64orion port not present.
459        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
460        * cpu.c: Comments added.
461        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
462        First attempt at exception/interrupt processing for ISA level 1
463        and minus any use of IDT/MON added.
464        * idtcpu.h: Conditionals changed to use gcc predefines.
465        * iregdef.h: Ditto.
466        * cpu_asm.h: No real change.  Merger required commit.
467        * rtems/Makefile.am: Ditto.
468        * rtems/score/Makefile.am: Ditto.
469        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
470        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
471        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
472
4732000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
474
475        * Makefile.am: Include compile.am.
476
4772000-08-10      Joel Sherrill <joel@OARcorp.com>
478
479        * ChangeLog: New file.
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