source: rtems/cpukit/score/cpu/mips/ChangeLog @ b3eb2fb9

4.115
Last change on this file since b3eb2fb9 was b3eb2fb9, checked in by Ralf Corsepius <ralf.corsepius@…>, on 05/17/11 at 14:54:13

2011-05-17 Ralf Corsépius <ralf.corsepius@…>

  • Makefile.am: Reformat.
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12011-05-17      Ralf Corsépius <ralf.corsepius@rtems.org>
2
3        * Makefile.am: Reformat.
4
52011-02-11      Ralf Corsépius <ralf.corsepius@rtems.org>
6
7        * cpu.c, rtems/score/mips.h:
8        Use "__asm__" instead of "asm" for improved c99-compliance.
9
102011-01-04      Joel Sherrill <joel.sherrill@oarcorp.com>
11
12        * cpu_asm.S: _Thread_Executing was not used.
13
142010-10-21      Joel Sherrill <joel.sherrill@oarcorp.com>
15
16        * rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to
17        _CPU_Context_restore() because it does not return. Telling GCC this
18        avoids generation of dead code.
19
202010-07-30      Gedare Bloom <giddyup44@yahoo.com>
21
22        PR 1599/cpukit
23        * cpu_asm.S: Rename _Context_Switch_necessary to
24        _Thread_Dispatch_necessary to more properly reflect the intent.
25
262010-07-29      Gedare Bloom <giddyup44@yahoo.com>
27
28        PR 1635/cpukit
29        * rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority
30        handling, to isolate the bitmap implementation of priorities in the
31        supercore so that priority management is a little more modular. This
32        change is in anticipation of scheduler implementations that can
33        select how they manage tracking priority levels / finding the highest
34        priority ready task. Note that most of the changes here are simple
35        renaming, to clarify the use of the bitmap-based priority management.
36
372010-07-16      Sebastian Huber <sebastian.huber@embedded-brains.de>
38
39        * rtems/score/cpu.h: Include <rtems/score/types.h> first.
40        * rtems/score/types.h: Use <rtems/score/basedefs.h> header file.
41
422010-07-01      Joel Sherrill <joel.sherrill@oarcorp.com>
43
44        * rtems/asm.h, rtems/score/cpu.h: cpu.h defines were not available to
45        assembly programs. This resulted in percpu.h (when included from
46        assembly) not being able to detect that the MIPS does not have a
47        dedicated software managed interrupt stack.
48
492010-06-28      Joel Sherrill <joel.sherrill@oarcorp.com>
50
51        PR 1573/cpukit
52        * cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which
53        contains the information required by RTEMS for each CPU core. This
54        encapsulates information such as thread executing, heir, idle and
55        dispatch needed.
56
572010-06-16      Joel Sherrill <joel.sherrill@oarcorp.com>
58
59        * cpu_asm.S: Remove trailing tabs.
60
612010-04-25      Joel Sherrill <joel.sherrilL@OARcorp.com>
62
63        * cpu.c, rtems/score/cpu.h: Move _CPU_Context_Initialize() to cpu.c so
64        it is easier to make warning free.
65
662010-04-25      Joel Sherrill <joel.sherrilL@OARcorp.com>
67
68        * rtems/score/cpu.h: Remove warning in _CPU_Context_Initialize.
69
702010-03-27      Joel Sherrill <joel.sherrill@oarcorp.com>
71
72        * cpu.c, cpu_asm.S: Add include of config.h
73
742009-03-12      Joel Sherrill <joel.sherrill@OARcorp.com>
75
76        PR 1385/cpukit
77        * cpu_asm.S: When the type rtems_boolean was switched to the C99 bool,
78        the size changed from 4 bytes to 1 byte. The interrupt dispatching
79        code accesses two boolean variables for scheduling purposes and the
80        assembly implementations of this code did not get updated.
81
822009-02-12      Joel Sherrill <joel.sherrill@oarcorp.com>
83
84        * cpu.c, rtems/score/cpu.h: Change prototype of IDLE thread to
85        consistently return void * and take a uintptr_t argument.
86
872009-02-11      Joel Sherrill <joel.sherrill@oarcorp.com>
88
89        * cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and
90        passing address of _Thread_Dispatch to _CPU_Initialize. Clean up
91        comments.
92
932008-09-11      Ralf Corsépius <ralf.corsepius@rtems.org>
94
95        * rtems/score/types.h: Do not define boolean, single_precision,
96        double_precision unless RTEMS_DEPRECATED_TYPES is given.
97
982008-08-21      Ralf Corsépius <ralf.corsepius@rtems.org>
99
100        * rtems/score/types.h: Include stdbool.h.
101        Use bool as base-type for boolean.
102
1032008-07-31      Joel Sherrill <joel.sherrill@OARcorp.com>
104
105        * cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads.
106
1072008-06-05      Joel Sherrill <joel.sherrill@OARcorp.com>
108
109        * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
110        parameter to indicate that the port uses the Simple Vectored
111        Interrupt model or the Programmable Interrupt Controller Model. The
112        PIC model is implemented primarily in the BSP and it is responsible
113        for all memory allocation.
114
1152008-06-04      Joel Sherrill <joel.sherrill@OARcorp.com>
116
117        * rtems/score/cpu.h: Use a constant for CPU_STACK_MINIMUM_SIZE so it
118        can be used in cpp expressions. Using sizeof() requires actually
119        compiling the file.
120
1212007-12-17      Joel Sherrill <joel.sherrill@oarcorp.com>
122
123        * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.
124
1252007-12-04      Joel Sherrill <joel.sherrill@OARcorp.com>
126
127        * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU
128        Table to Configuration Table. Eliminate CPU Table from all ports.
129        Delete references to CPU Table in all forms.
130
1312007-12-03      Joel Sherrill <joel.sherrill@OARcorp.com>
132
133        * rtems/score/cpu.h: Moved most of the remaining CPU Table fields to
134        the Configuration Table. This included pretasking_hook,
135        predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace,
136        extra_mpci_receive_server_stack, stack_allocate_hook, and
137        stack_free_hook. As a side-effect of this effort some multiprocessing
138        code was made conditional and some style clean up occurred.
139
1402007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
141
142        * rtems/score/cpu.h: Eliminate the clicks_per_microsecond field in the
143        MIPS CPU Table and define another mechanism for drivers to obtain
144        this information.
145
1462007-08-04      Ralf Corsépius <ralf.corsepius@rtems.org>
147
148        * rtems/score/cpu.h: Use uintptr_t instead of uint32_t.
149
1502007-05-09      Ralf Corsépius <ralf.corsepius@rtems.org>
151
152        * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
153
1542007-04-17      Ralf Corsépius <ralf.corsepius@rtems.org>
155
156        * rtems/score/cpu.h:
157          Use Context_Control_fp* instead of void* for fp_contexts.
158          Eliminate evil casts.
159
1602006-11-17      Ralf Corsépius <ralf.corsepius@rtems.org>
161
162        * rtems/score/types.h: Remove unsigned64, signed64.
163
1642006-06-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
165
166        * cpu.c: Added __mips==32 to fix build problems on those targets
167        caused by the Bruce Robinson.
168
1692006-06-08 Bruce Robinson <brucer@pmccorp.com>
170
171        * cpu.c: Add int64 types for __mips==3 cpus, incorporate
172           mips_interrupt_mask() into mask computations
173        * cpu_asm.S: Add int64 register save/restores for __mips==3 cpus.  Adjustment
174           of mips1 vs mips3 macros.
175        * cpu.h: Add int64 types for __mips==3 cpus.
176       
1772006-03-17      Ralf Corsepius <ralf.corsepius@rtems.org>
178
179        * cpu.c (_CPU_Initialize): Add fpu initialization.
180        * rtems/score/cpu.h: Setup CPU_*_ENDIAN from GCC's__MIPS{EL|EB}__.
181        (Partial merger of submission by Bruce Robinson <brucer@pmccorp.com>).
182
1832006-01-16      Joel Sherrill <joel@OARcorp.com>
184
185        * rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
186        As a side-effect, grammar and spelling errors were corrected, spacing
187        errors were address, and some variable names were improved.
188
1892005-11-18      Joel Sherrill <joel@OARcorp.com>
190
191        * rtems/score/cpu.h: Eliminate use of unsigned32.
192
1932005-11-08      Ralf Corsepius <ralf.corsepius@rtems.org>
194
195        * rtems/score/types.h: Eliminate unsigned16, unsigned32.
196
1972005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
198
199        * rtems/asm.h: Remove private version of CONCAT macros.
200        Include <rtems/concat.h> instead.
201
2022005-04-26      Joel Sherrill <joel@OARcorp.com>
203
204        * rtems/asm.h: Eliminate warnings.
205
2062005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
207
208        * Makefile.am: Split out preinstallation rules.
209        * preinstall.am: New (Split out from Makefile.am).
210
2112005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
212
213        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
214        Header guards cleanup.
215
2162005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
217
218        PR 754/rtems
219        * rtems/asm.h: New (relocated from .).
220        * asm.h: Remove (moved to rtems/asm.h).
221        * Makefile.am: Reflect changes above.
222
2232005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
224
225        PR rtems/752
226        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
227        New header guards.
228        * idtcpu.h, iregdef.h: Remove.
229        * Makefile.am: Reflect changes above.
230
2312004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
232
233        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
234        New header guards.
235
2362005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
237
238        * rtems/score/types.h: Remove signed8, signed16, signed32,
239        unsigned8, unsigned16, unsigned32.
240
2412005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
242
243        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
244
2452005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
246
247        * rtems/score/types.h: #include <rtems/stdint.h>.
248
2492005-01-07      Joel Sherrill <joel@OARcorp.com>
250
251        * rtems/score/cpu.h: Remove warnings.
252
2532005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
254
255        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
256
2572005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
258
259        PR 739
260        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
261        when compiling cpu_asm.S.  Problem was a #define sneaked in in
262        version 1.11, no ill effects would have only affected R4000
263        builds.
264
2652005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
266
267        PR 737
268        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
269        slot when compiling cpu_asm.S
270
2712005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
272
273        * Makefile.am: Remove build-variant support.
274
2752004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
276
277        PR 730
278        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
279        for rtems-4.7.
280
2812004-04-09      Joel Sherrill <joel@OARcorp.com>
282
283        PR 605/bsps
284        * cpu.c: Do not use C++ style comments.
285
2862004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
287        PR 601
288        * cpu_asm.S: Added __mips==32 support for R4000 processors running
289        32 bit code.  Fixed #define problems that caused fpu code to
290        always be included even when no fpu is present.
291
2922004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
293
294        PR 598/bsps
295        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
296        status/control register on context switches. Missing this register
297        was causing intermittent floating point errors.
298
2992003-09-04      Joel Sherrill <joel@OARcorp.com>
300
301        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
302        rtems/score/types.h: URL for license changed.
303
3042003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
305
306        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
307
3082003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
309
310        * configure.ac: Remove AC_CONFIG_AUX_DIR.
311
3122002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
313
314        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
315        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
316
3172002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
318
319        * configure.ac: Fix package name.
320
3212002-11-04      Joel Sherrill <joel@OARcorp.com>
322
323        * idtcpu.h: Removed warning.
324
3252002-11-01      Joel Sherrill <joel@OARcorp.com>
326
327        * idtcpu.h: Removed warnings.
328
3292002-10-28      Joel Sherrill <joel@OARcorp.com>
330
331        * idtcpu.h: Removed warning by turning extra token at the end of
332        an endif into a comment.
333
3342002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
335
336        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
337
3382002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
339
340        * .cvsignore: Reformat.
341        Add autom4te*cache.
342        Remove autom4te.cache.
343
3442002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
345
346        * cpu_asm.S: Clarified some comments, removed code that forced
347        SR_IEP on when returning from an interrupt.
348
3492002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
350
351        * configure.ac: Add RTEMS_PROG_CCAS
352
3532002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
354
355        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
356        Add AC_PROG_RANLIB.
357
3582002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
359        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
360        deadlock caused by interrupt arriving while dispatching.
361       
3622002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
363
364        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
365        Use ../../../aclocal.
366
3672001-04-03      Joel Sherrill <joel@OARcorp.com>
368
369        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
370        * rtems/score/mipstypes.h: Removed.
371        * rtems/score/types.h: New file via CVS magic.
372        * Makefile.am, rtems/score/cpu.h: Account for name change.
373
3742002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
375
376        * configure.ac:
377        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
378        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
379        * Makefile.am: Remove AUTOMAKE_OPTIONS.
380
3812002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
382
383        * cpu_asm.S: Now compiles on 4600 and 4650.
384
3852002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
386
387        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
388        * rtems/score/cpu.h: Fixed register numbering in comments and made
389        interrupt enable/disable more robust.
390       
3912002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
392        * cpu_asm.S: Added support for the debug exception vector, cleaned
393        up the exception processing & exception return stuff.  Re-added
394        EPC in the task context structure so the gdb stub will know where
395        a thread is executing.  Should've left it there in the first place...
396        * idtcpu.h: Added support for the debug exception vector.
397        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
398        stack frame in an interrupt so context switch code can get the
399        userspace EPC when scheduling.
400        * rtems/score/cpu.h: Re-added EPC to the task context.
401
4022002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
403
404        * cpu_asm.S: Fixed exception return address, modified FP context
405        switch so FPU is properly enabled and also doesn't screw up the
406        exception FP handling.
407        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
408        returning from exceptions.
409        * iregdef.h: Added R_TAR to the stack frame so the target address
410        can be saved on a per-exception basis.  The new entry is past the
411        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
412        stuff.
413        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
414        to obtain FPU defines without syntax errors generated by the C
415        defintions.
416        * cpu.c: Improved interrupt level saves & restores.
417       
4182002-02-08      Joel Sherrill <joel@OARcorp.com>
419
420        * iregdef.h, rtems/score/cpu.h: Reordered register in the
421        exception stack frame to better match gdb's expectations.
422
4232001-02-05      Joel Sherrill <joel@OARcorp.com>
424
425        * cpu_asm.S: Enhanced to save/restore more registers on
426        exceptions.
427        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
428        register individually and document when it is saved.
429        * idtcpu.h: Added constants for the coprocessor 1 registers
430        revision and status.
431
4322001-02-05      Joel Sherrill <joel@OARcorp.com>
433
434        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
435
4362001-02-04      Joel Sherrill <joel@OARcorp.com>
437
438        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
439        in the previous patch that has now been confirmed.
440
4412001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
442
443        * cpu.c: Enhancements and fixes for modifying the SR when changing
444        the interrupt level.
445        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
446        managed on a per-task basis, improved handling of interrupt levels,
447        and made deferred FP contexts work on the MIPS.
448        * rtems/score/cpu.h: Modified to support above changes.
449
4502002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
451
452        * rtems/Makefile.am: Removed.
453        * rtems/score/Makefile.am: Removed.
454        * configure.ac: Reflect changes above.
455        * Makefile.am: Reflect changes above.
456
4572002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
458
459        * asm.h: Remove #include <rtems/score/targopts.h>.
460        Add #include <rtems/score/cpuopts.h>.
461        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
462
463
4642001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
465
466        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
467
4682001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
469
470        * Makefile.am: Add multilib support.
471
4722001-11-28      Joel Sherrill <joel@OARcorp.com>,
473
474        This was tracked as PR91.
475        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
476        is used to specify if the port uses the standard macro for this (FALSE).
477        A TRUE setting indicates the port provides its own implementation.
478
4792001-10-12      Joel Sherrill <joel@OARcorp.com>
480
481        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
482        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
483        Wayne Bullaughey <wayne@wmi.com>.
484
4852001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
486
487        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
488        * configure.in: Remove.
489        * configure.ac: New file, generated from configure.in by autoupdate.
490
4912001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
492
493        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
494        * Makefile.am: Use 'PREINSTALL_FILES ='.
495
4962001-07-03      Joel Sherrill <joel@OARcorp.com>
497
498        * cpu.c: Fixed typo.
499
5002000-05-24      Joel Sherrill <joel@OARcorp.com>
501
502        * rtems/score/mips.h: Added constants for MIPS exception numbers.
503        All exceptions should be given low numbers and thus can be installed
504        and processed in a uniform manner.  Variances between various MIPS
505        ISA levels were not accounted for.
506
5072001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
508
509        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
510        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
511
5122001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
513
514        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
515        the context initialization to account for floating point tasks. 
516        * rtems/score/mips.h: Added the routines mips_set_cause(),
517        mips_get_fcr31(), and mips_set_fcr31().
518        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
519
5202001-05-07      Joel Sherrill <joel@OARcorp.com>
521
522        * cpu_asm.S: Merged patches from Gregory Menke
523        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
524        stack usage and include nops in the delay slots.
525
5262001-04-20      Joel Sherrill <joel@OARcorp.com>
527
528        * cpu_asm.S: Added code to save and restore SR and EPC to
529        properly support nested interrupts.  Note that the ISR
530        (not RTEMS) enables interrupts allowing the nesting to occur.
531
5322001-03-14      Joel Sherrill <joel@OARcorp.com>
533
534        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
535        Removed unused variable _CPU_Thread_dispatch_pointer
536        and cleaned numerous comments.
537       
5382001-03-13      Joel Sherrill <joel@OARcorp.com>
539
540        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
541        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
542        Also reimplemented some assembly routines in C further reducing
543        the amount of assembly and increasing maintainability.
544
5452001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
546
547        * Makefile.am, rtems/score/Makefile.am:
548        Apply include_*HEADERS instead of H_FILES.
549
5502001-01-12      Joel Sherrill <joel@OARcorp.com>
551
552        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
553        register constraints from "general" to "register".
554
5552001-01-09      Joel Sherrill <joel@OARcorp.com>
556
557        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
558        to make it easier to conditionalize the code for various ISA levels.
559
5602001-01-08      Joel Sherrill <joel@OARcorp.com>
561
562        * idtcpu.h: Commented out definition of "wait".  It was stupid to
563        use such a common word as a macro.
564        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
565        * rtems/score/mips.h: Added include of <idtcpu.h>.
566        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
567
5682001-01-03      Joel Sherrill <joel@OARcorp.com>
569
570        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
571        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
572
5732000-12-19      Joel Sherrill <joel@OARcorp.com>
574
575        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
576        Previous code resulting in the interrupted immediately returning
577        to the caller of the routine it was inside.
578
5792000-12-19      Joel Sherrill <joel@OARcorp.com>
580
581        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
582        because it has not been allocated yet.
583
5842000-12-13      Joel Sherrill <joel@OARcorp.com>
585
586        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
587        * cpu_asm.S: Removed assembly language to vector ISR handler
588        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
589        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
590        longer a constant -- get the real value from libcpu.
591
5922000-12-13      Joel Sherrill <joel@OARcorp.com>
593
594        * cpu_asm.h: Removed.
595        * Makefile.am: Remove cpu_asm.h.
596        * rtems/score/mips64orion.h: Renamed mips.h.
597        * rtems/score/mips.h: New file, formerly mips64orion.h.
598        Header rewritten.
599        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
600        mips_disable_in_interrupt_mask): New macros.
601        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
602        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
603        few defines that were in <cpu_asm.h>.
604        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
605        MIPS ISA 3 is still in assembly for now.
606        (_CPU_Thread_Idle_body): Rewrote in C.
607        * cpu_asm.S: Rewrote file header.
608        (FRAME,ENDFRAME) now in asm.h.
609        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
610        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
611        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
612        leaves other bits in SR alone on task switch.
613        (mips_enable_interrupts,mips_disable_interrupts,
614        mips_enable_global_interrupts,mips_disable_global_interrupts,
615        disable_int, enable_int): Removed.
616        (mips_get_sr): Rewritten as C macro.
617        (_CPU_Thread_Idle_body): Rewritten in C.
618        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
619        placed in libcpu.
620        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
621        to libcpu/mips/shared/interrupts.
622        (general): Cleaned up comment blocks and #if 0 areas.
623        * idtcpu.h: Made ifdef report an error.
624        * iregdef.h: Removed warning.
625        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
626        number defined by libcpu.
627        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
628        to access SR.
629        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
630        (_CPU_Context_Initialize): Honor ISR level in task initialization.
631        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
632
6332000-12-06      Joel Sherrill <joel@OARcorp.com>
634
635        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
636        context should be 32 not 64 bits.
637
6382000-11-30      Joel Sherrill <joel@OARcorp.com>
639
640        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
641        correct name of _CPU_Context_switch_restore.  Added dummy
642        version of exc_utlb_code() so applications would link.
643
6442000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
645
646        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
647
6482000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
649
650        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
651
6522000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
653
654        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
655        Switch to GNU canonicalization.
656
6572000-10-24      Alan Cudmore <alanc@linuxstart.com> and
658        Joel Sherrill <joel@OARcorp.com>
659
660        * This is a major reworking of the mips64orion port to use
661        gcc predefines as much as possible and a big push to multilib
662        the mips port.  The mips64orion port was copied/renamed to mips
663        to be more like other GNU tools.  Alan did most of the technical
664        work of determining how to map old macro names used by the mips64orion
665        port to standard compiler macro definitions.  Joel did the merge
666        with CVS magic to keep individual file history and did the BSP
667        modifications. Details follow:
668        * Makefile.am: idtmon.h in mips64orion port not present.
669        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
670        * cpu.c: Comments added.
671        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
672        First attempt at exception/interrupt processing for ISA level 1
673        and minus any use of IDT/MON added.
674        * idtcpu.h: Conditionals changed to use gcc predefines.
675        * iregdef.h: Ditto.
676        * cpu_asm.h: No real change.  Merger required commit.
677        * rtems/Makefile.am: Ditto.
678        * rtems/score/Makefile.am: Ditto.
679        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
680        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
681        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
682
6832000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
684
685        * Makefile.am: Include compile.am.
686
6872000-08-10      Joel Sherrill <joel@OARcorp.com>
688
689        * ChangeLog: New file.
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