source: rtems/cpukit/score/cpu/mips/ChangeLog @ aa7f8a1f

4.104.114.84.95
Last change on this file since aa7f8a1f was aa7f8a1f, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 14, 2001 at 4:43:35 PM

2001-03-14 Joel Sherrill <joel@…>

  • cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h: Removed unused variable _CPU_Thread_dispatch_pointer and cleaned numerous comments.
  • Property mode set to 100644
File size: 6.1 KB
Line 
12001-03-14      Joel Sherrill <joel@OARcorp.com>
2
3        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
4        Removed unused variable _CPU_Thread_dispatch_pointer
5        and cleaned numerous comments.
6       
72001-03-13      Joel Sherrill <joel@OARcorp.com>
8
9        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
10        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
11        Also reimplemented some assembly routines in C further reducing
12        the amount of assembly and increasing maintainability.
13
142001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
15
16        * Makefile.am, rtems/score/Makefile.am:
17        Apply include_*HEADERS instead of H_FILES.
18
192001-01-12      Joel Sherrill <joel@OARcorp.com>
20
21        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
22        register constraints from "general" to "register".
23
242001-01-09      Joel Sherrill <joel@OARcorp.com>
25
26        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
27        to make it easier to conditionalize the code for various ISA levels.
28
292001-01-08      Joel Sherrill <joel@OARcorp.com>
30
31        * idtcpu.h: Commented out definition of "wait".  It was stupid to
32        use such a common word as a macro.
33        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
34        * rtems/score/mips.h: Added include of <idtcpu.h>.
35        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
36
372001-01-03      Joel Sherrill <joel@OARcorp.com>
38
39        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
40        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
41
422000-12-19      Joel Sherrill <joel@OARcorp.com>
43
44        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
45        Previous code resulting in the interrupted immediately returning
46        to the caller of the routine it was inside.
47
482000-12-19      Joel Sherrill <joel@OARcorp.com>
49
50        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
51        because it has not been allocated yet.
52
532000-12-13      Joel Sherrill <joel@OARcorp.com>
54
55        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
56        * cpu_asm.S: Removed assembly language to vector ISR handler
57        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
58        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
59        longer a constant -- get the real value from libcpu.
60
612000-12-13      Joel Sherrill <joel@OARcorp.com>
62
63        * cpu_asm.h: Removed.
64        * Makefile.am: Remove cpu_asm.h.
65        * rtems/score/mips64orion.h: Renamed mips.h.
66        * rtems/score/mips.h: New file, formerly mips64orion.h.
67        Header rewritten.
68        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
69        mips_disable_in_interrupt_mask): New macros.
70        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
71        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
72        few defines that were in <cpu_asm.h>.
73        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
74        MIPS ISA 3 is still in assembly for now.
75        (_CPU_Thread_Idle_body): Rewrote in C.
76        * cpu_asm.S: Rewrote file header.
77        (FRAME,ENDFRAME) now in asm.h.
78        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
79        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
80        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
81        leaves other bits in SR alone on task switch.
82        (mips_enable_interrupts,mips_disable_interrupts,
83        mips_enable_global_interrupts,mips_disable_global_interrupts,
84        disable_int, enable_int): Removed.
85        (mips_get_sr): Rewritten as C macro.
86        (_CPU_Thread_Idle_body): Rewritten in C.
87        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
88        placed in libcpu.
89        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
90        to libcpu/mips/shared/interrupts.
91        (general): Cleaned up comment blocks and #if 0 areas.
92        * idtcpu.h: Made ifdef report an error.
93        * iregdef.h: Removed warning.
94        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
95        number defined by libcpu.
96        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
97        to access SR.
98        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
99        (_CPU_Context_Initialize): Honor ISR level in task initialization.
100        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
101
1022000-12-06      Joel Sherrill <joel@OARcorp.com>
103
104        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
105        context should be 32 not 64 bits.
106
1072000-11-30      Joel Sherrill <joel@OARcorp.com>
108
109        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
110        correct name of _CPU_Context_switch_restore.  Added dummy
111        version of exc_utlb_code() so applications would link.
112
1132000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
114
115        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
116
1172000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
118
119        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
120
1212000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
122
123        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
124        Switch to GNU canonicalization.
125
1262000-10-24      Alan Cudmore <alanc@linuxstart.com> and
127        Joel Sherrill <joel@OARcorp.com>
128
129        * This is a major reworking of the mips64orion port to use
130        gcc predefines as much as possible and a big push to multilib
131        the mips port.  The mips64orion port was copied/renamed to mips
132        to be more like other GNU tools.  Alan did most of the technical
133        work of determining how to map old macro names used by the mips64orion
134        port to standard compiler macro definitions.  Joel did the merge
135        with CVS magic to keep individual file history and did the BSP
136        modifications. Details follow:
137        * Makefile.am: idtmon.h in mips64orion port not present.
138        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
139        * cpu.c: Comments added.
140        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
141        First attempt at exception/interrupt processing for ISA level 1
142        and minus any use of IDT/MON added.
143        * idtcpu.h: Conditionals changed to use gcc predefines.
144        * iregdef.h: Ditto.
145        * cpu_asm.h: No real change.  Merger required commit.
146        * rtems/Makefile.am: Ditto.
147        * rtems/score/Makefile.am: Ditto.
148        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
149        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
150        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
151
1522000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
153
154        * Makefile.am: Include compile.am.
155
1562000-08-10      Joel Sherrill <joel@OARcorp.com>
157
158        * ChangeLog: New file.
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