source: rtems/cpukit/score/cpu/mips/ChangeLog @ 9fd4f5c5

2001-01-03      Joel Sherrill <joel@OARcorp.com>

        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.

2000-12-19      Joel Sherrill <joel@OARcorp.com>

        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
        Previous code resulting in the interrupted immediately returning
        to the caller of the routine it was inside.

2000-12-19      Joel Sherrill <joel@OARcorp.com>

        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
        because it has not been allocated yet.

2000-12-13      Joel Sherrill <joel@OARcorp.com>

        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
        * cpu_asm.S: Removed assembly language to vector ISR handler
        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
        longer a constant -- get the real value from libcpu.

2000-12-13      Joel Sherrill <joel@OARcorp.com>

        * cpu_asm.h: Removed.
        * Makefile.am: Remove cpu_asm.h.
        * rtems/score/mips64orion.h: Renamed mips.h.
        * rtems/score/mips.h: New file, formerly mips64orion.h.
        Header rewritten.
        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
        mips_disable_in_interrupt_mask): New macros.
        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
        few defines that were in <cpu_asm.h>.
        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
        MIPS ISA 3 is still in assembly for now.
        (_CPU_Thread_Idle_body): Rewrote in C.
        * cpu_asm.S: Rewrote file header. 
        (FRAME,ENDFRAME) now in asm.h.
        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
        leaves other bits in SR alone on task switch.
        (mips_enable_interrupts,mips_disable_interrupts,
        mips_enable_global_interrupts,mips_disable_global_interrupts,
        disable_int, enable_int): Removed.
        (mips_get_sr): Rewritten as C macro.
        (_CPU_Thread_Idle_body): Rewritten in C.
        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
        placed in libcpu.
        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
        to libcpu/mips/shared/interrupts.
        (general): Cleaned up comment blocks and #if 0 areas.
        * idtcpu.h: Made ifdef report an error.
        * iregdef.h: Removed warning.
        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
        number defined by libcpu.
        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
        to access SR.
        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
        (_CPU_Context_Initialize): Honor ISR level in task initialization.
        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.

2000-12-06      Joel Sherrill <joel@OARcorp.com>

        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
        context should be 32 not 64 bits.

2000-11-30      Joel Sherrill <joel@OARcorp.com>

        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
        correct name of _CPU_Context_switch_restore.  Added dummy
        version of exc_utlb_code() so applications would link.

2000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.

2000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.

2000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
        Switch to GNU canonicalization.

2000-10-24      Alan Cudmore <alanc@linuxstart.com> and
        Joel Sherrill <joel@OARcorp.com>

        * This is a major reworking of the mips64orion port to use 
        gcc predefines as much as possible and a big push to multilib
        the mips port.  The mips64orion port was copied/renamed to mips
        to be more like other GNU tools.  Alan did most of the technical
        work of determining how to map old macro names used by the mips64orion
        port to standard compiler macro definitions.  Joel did the merge
        with CVS magic to keep individual file history and did the BSP
        modifications. Details follow:
        * Makefile.am: idtmon.h in mips64orion port not present.
        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
        * cpu.c: Comments added.
        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
        First attempt at exception/interrupt processing for ISA level 1 
        and minus any use of IDT/MON added.
        * idtcpu.h: Conditionals changed to use gcc predefines.
        * iregdef.h: Ditto.
        * cpu_asm.h: No real change.  Merger required commit.
        * rtems/Makefile.am: Ditto.
        * rtems/score/Makefile.am: Ditto.
        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.

2000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>

        * Makefile.am: Include compile.am.

2000-08-10      Joel Sherrill <joel@OARcorp.com>

        * ChangeLog: New file.