source: rtems/cpukit/score/cpu/mips/ChangeLog @ 9cec3485

Last change on this file since 9cec3485 was 9cec3485, checked in by Joel Sherrill <joel.sherrill@…>, on 04/03/04 at 16:29:06

2004-04-03 Art Ferrer <arturo.b.ferrer@…>

PR 598/bsps

  • cpu_asm.S, rtems/score/cpu.h: Add save of floating point status/control register on context switches. Missing this register was causing intermittent floating point errors.
  • Property mode set to 100644
File size: 14.1 KB
Line 
12004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
2
3        PR 598/bsps
4        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
5        status/control register on context switches. Missing this register
6        was causing intermittent floating point errors.
7
82003-09-04      Joel Sherrill <joel@OARcorp.com>
9
10        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
11        rtems/score/types.h: URL for license changed.
12
132003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
14
15        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
16
172003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
18
19        * configure.ac: Remove AC_CONFIG_AUX_DIR.
20
212002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
22
23        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
24        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
25
262002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
27
28        * configure.ac: Fix package name.
29
302002-11-04      Joel Sherrill <joel@OARcorp.com>
31
32        * idtcpu.h: Removed warning.
33
342002-11-01      Joel Sherrill <joel@OARcorp.com>
35
36        * idtcpu.h: Removed warnings.
37
382002-10-28      Joel Sherrill <joel@OARcorp.com>
39
40        * idtcpu.h: Removed warning by turning extra token at the end of
41        an endif into a comment.
42
432002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
44
45        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
46
472002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
48
49        * .cvsignore: Reformat.
50        Add autom4te*cache.
51        Remove autom4te.cache.
52
532002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
54
55        * cpu_asm.S: Clarified some comments, removed code that forced
56        SR_IEP on when returning from an interrupt.
57
582002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
59
60        * configure.ac: Add RTEMS_PROG_CCAS
61
622002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
63
64        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
65        Add AC_PROG_RANLIB.
66
672002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
68        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
69        deadlock caused by interrupt arriving while dispatching.
70       
712002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
72
73        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
74        Use ../../../aclocal.
75
762001-04-03      Joel Sherrill <joel@OARcorp.com>
77
78        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
79        * rtems/score/mipstypes.h: Removed.
80        * rtems/score/types.h: New file via CVS magic.
81        * Makefile.am, rtems/score/cpu.h: Account for name change.
82
832002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
84
85        * configure.ac:
86        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
87        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
88        * Makefile.am: Remove AUTOMAKE_OPTIONS.
89
902002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
91
92        * cpu_asm.S: Now compiles on 4600 and 4650.
93
942002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
95
96        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
97        * rtems/score/cpu.h: Fixed register numbering in comments and made
98        interrupt enable/disable more robust.
99       
1002002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
101        * cpu_asm.S: Added support for the debug exception vector, cleaned
102        up the exception processing & exception return stuff.  Re-added
103        EPC in the task context structure so the gdb stub will know where
104        a thread is executing.  Should've left it there in the first place...
105        * idtcpu.h: Added support for the debug exception vector.
106        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
107        stack frame in an interrupt so context switch code can get the
108        userspace EPC when scheduling.
109        * rtems/score/cpu.h: Re-added EPC to the task context.
110
1112002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
112
113        * cpu_asm.S: Fixed exception return address, modified FP context
114        switch so FPU is properly enabled and also doesn't screw up the
115        exception FP handling.
116        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
117        returning from exceptions.
118        * iregdef.h: Added R_TAR to the stack frame so the target address
119        can be saved on a per-exception basis.  The new entry is past the
120        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
121        stuff.
122        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
123        to obtain FPU defines without syntax errors generated by the C
124        defintions.
125        * cpu.c: Improved interrupt level saves & restores.
126       
1272002-02-08      Joel Sherrill <joel@OARcorp.com>
128
129        * iregdef.h, rtems/score/cpu.h: Reordered register in the
130        exception stack frame to better match gdb's expectations.
131
1322001-02-05      Joel Sherrill <joel@OARcorp.com>
133
134        * cpu_asm.S: Enhanced to save/restore more registers on
135        exceptions.
136        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
137        register individually and document when it is saved.
138        * idtcpu.h: Added constants for the coprocessor 1 registers
139        revision and status.
140
1412001-02-05      Joel Sherrill <joel@OARcorp.com>
142
143        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
144
1452001-02-04      Joel Sherrill <joel@OARcorp.com>
146
147        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
148        in the previous patch that has now been confirmed.
149
1502001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
151
152        * cpu.c: Enhancements and fixes for modifying the SR when changing
153        the interrupt level.
154        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
155        managed on a per-task basis, improved handling of interrupt levels,
156        and made deferred FP contexts work on the MIPS.
157        * rtems/score/cpu.h: Modified to support above changes.
158
1592002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
160
161        * rtems/Makefile.am: Removed.
162        * rtems/score/Makefile.am: Removed.
163        * configure.ac: Reflect changes above.
164        * Makefile.am: Reflect changes above.
165
1662002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
167
168        * asm.h: Remove #include <rtems/score/targopts.h>.
169        Add #include <rtems/score/cpuopts.h>.
170        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
171
172
1732001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
174
175        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
176
1772001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
178
179        * Makefile.am: Add multilib support.
180
1812001-11-28      Joel Sherrill <joel@OARcorp.com>,
182
183        This was tracked as PR91.
184        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
185        is used to specify if the port uses the standard macro for this (FALSE).
186        A TRUE setting indicates the port provides its own implementation.
187
1882001-10-12      Joel Sherrill <joel@OARcorp.com>
189
190        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
191        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
192        Wayne Bullaughey <wayne@wmi.com>.
193
1942001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
195
196        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
197        * configure.in: Remove.
198        * configure.ac: New file, generated from configure.in by autoupdate.
199
2002001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
201
202        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
203        * Makefile.am: Use 'PREINSTALL_FILES ='.
204
2052001-07-03      Joel Sherrill <joel@OARcorp.com>
206
207        * cpu.c: Fixed typo.
208
2092000-05-24      Joel Sherrill <joel@OARcorp.com>
210
211        * rtems/score/mips.h: Added constants for MIPS exception numbers.
212        All exceptions should be given low numbers and thus can be installed
213        and processed in a uniform manner.  Variances between various MIPS
214        ISA levels were not accounted for.
215
2162001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
217
218        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
219        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
220
2212001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
222
223        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
224        the context initialization to account for floating point tasks. 
225        * rtems/score/mips.h: Added the routines mips_set_cause(),
226        mips_get_fcr31(), and mips_set_fcr31().
227        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
228
2292001-05-07      Joel Sherrill <joel@OARcorp.com>
230
231        * cpu_asm.S: Merged patches from Gregory Menke
232        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
233        stack usage and include nops in the delay slots.
234
2352001-04-20      Joel Sherrill <joel@OARcorp.com>
236
237        * cpu_asm.S: Added code to save and restore SR and EPC to
238        properly support nested interrupts.  Note that the ISR
239        (not RTEMS) enables interrupts allowing the nesting to occur.
240
2412001-03-14      Joel Sherrill <joel@OARcorp.com>
242
243        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
244        Removed unused variable _CPU_Thread_dispatch_pointer
245        and cleaned numerous comments.
246       
2472001-03-13      Joel Sherrill <joel@OARcorp.com>
248
249        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
250        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
251        Also reimplemented some assembly routines in C further reducing
252        the amount of assembly and increasing maintainability.
253
2542001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
255
256        * Makefile.am, rtems/score/Makefile.am:
257        Apply include_*HEADERS instead of H_FILES.
258
2592001-01-12      Joel Sherrill <joel@OARcorp.com>
260
261        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
262        register constraints from "general" to "register".
263
2642001-01-09      Joel Sherrill <joel@OARcorp.com>
265
266        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
267        to make it easier to conditionalize the code for various ISA levels.
268
2692001-01-08      Joel Sherrill <joel@OARcorp.com>
270
271        * idtcpu.h: Commented out definition of "wait".  It was stupid to
272        use such a common word as a macro.
273        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
274        * rtems/score/mips.h: Added include of <idtcpu.h>.
275        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
276
2772001-01-03      Joel Sherrill <joel@OARcorp.com>
278
279        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
280        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
281
2822000-12-19      Joel Sherrill <joel@OARcorp.com>
283
284        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
285        Previous code resulting in the interrupted immediately returning
286        to the caller of the routine it was inside.
287
2882000-12-19      Joel Sherrill <joel@OARcorp.com>
289
290        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
291        because it has not been allocated yet.
292
2932000-12-13      Joel Sherrill <joel@OARcorp.com>
294
295        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
296        * cpu_asm.S: Removed assembly language to vector ISR handler
297        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
298        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
299        longer a constant -- get the real value from libcpu.
300
3012000-12-13      Joel Sherrill <joel@OARcorp.com>
302
303        * cpu_asm.h: Removed.
304        * Makefile.am: Remove cpu_asm.h.
305        * rtems/score/mips64orion.h: Renamed mips.h.
306        * rtems/score/mips.h: New file, formerly mips64orion.h.
307        Header rewritten.
308        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
309        mips_disable_in_interrupt_mask): New macros.
310        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
311        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
312        few defines that were in <cpu_asm.h>.
313        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
314        MIPS ISA 3 is still in assembly for now.
315        (_CPU_Thread_Idle_body): Rewrote in C.
316        * cpu_asm.S: Rewrote file header.
317        (FRAME,ENDFRAME) now in asm.h.
318        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
319        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
320        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
321        leaves other bits in SR alone on task switch.
322        (mips_enable_interrupts,mips_disable_interrupts,
323        mips_enable_global_interrupts,mips_disable_global_interrupts,
324        disable_int, enable_int): Removed.
325        (mips_get_sr): Rewritten as C macro.
326        (_CPU_Thread_Idle_body): Rewritten in C.
327        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
328        placed in libcpu.
329        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
330        to libcpu/mips/shared/interrupts.
331        (general): Cleaned up comment blocks and #if 0 areas.
332        * idtcpu.h: Made ifdef report an error.
333        * iregdef.h: Removed warning.
334        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
335        number defined by libcpu.
336        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
337        to access SR.
338        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
339        (_CPU_Context_Initialize): Honor ISR level in task initialization.
340        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
341
3422000-12-06      Joel Sherrill <joel@OARcorp.com>
343
344        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
345        context should be 32 not 64 bits.
346
3472000-11-30      Joel Sherrill <joel@OARcorp.com>
348
349        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
350        correct name of _CPU_Context_switch_restore.  Added dummy
351        version of exc_utlb_code() so applications would link.
352
3532000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
354
355        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
356
3572000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
358
359        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
360
3612000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
362
363        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
364        Switch to GNU canonicalization.
365
3662000-10-24      Alan Cudmore <alanc@linuxstart.com> and
367        Joel Sherrill <joel@OARcorp.com>
368
369        * This is a major reworking of the mips64orion port to use
370        gcc predefines as much as possible and a big push to multilib
371        the mips port.  The mips64orion port was copied/renamed to mips
372        to be more like other GNU tools.  Alan did most of the technical
373        work of determining how to map old macro names used by the mips64orion
374        port to standard compiler macro definitions.  Joel did the merge
375        with CVS magic to keep individual file history and did the BSP
376        modifications. Details follow:
377        * Makefile.am: idtmon.h in mips64orion port not present.
378        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
379        * cpu.c: Comments added.
380        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
381        First attempt at exception/interrupt processing for ISA level 1
382        and minus any use of IDT/MON added.
383        * idtcpu.h: Conditionals changed to use gcc predefines.
384        * iregdef.h: Ditto.
385        * cpu_asm.h: No real change.  Merger required commit.
386        * rtems/Makefile.am: Ditto.
387        * rtems/score/Makefile.am: Ditto.
388        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
389        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
390        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
391
3922000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
393
394        * Makefile.am: Include compile.am.
395
3962000-08-10      Joel Sherrill <joel@OARcorp.com>
397
398        * ChangeLog: New file.
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