source: rtems/cpukit/score/cpu/mips/ChangeLog @ 8c746fe

4.104.114.84.95
Last change on this file since 8c746fe was 8c746fe, checked in by Ralf Corsepius <ralf.corsepius@…>, on 07/01/02 at 09:59:55

2002-07-01 Ralf Corsepius <corsepiu@…>

  • configure.ac: Remove RTEMS_PROJECT_ROOT.
  • Property mode set to 100644
File size: 12.5 KB
Line 
12002-07-01      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
2
3        * configure.ac: Remove RTEMS_PROJECT_ROOT.
4
52002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
6
7        * configure.ac: Add RTEMS_PROG_CCAS
8
92002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
10
11        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
12        Add AC_PROG_RANLIB.
13
142002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
15
16        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
17        Use ../../../aclocal.
18
192001-04-03      Joel Sherrill <joel@OARcorp.com>
20
21        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
22        * rtems/score/mipstypes.h: Removed.
23        * rtems/score/types.h: New file via CVS magic.
24        * Makefile.am, rtems/score/cpu.h: Account for name change.
25
262002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
27
28        * configure.ac:
29        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
30        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
31        * Makefile.am: Remove AUTOMAKE_OPTIONS.
32
332002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
34
35        * cpu_asm.S: Now compiles on 4600 and 4650.
36
372002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
38
39        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
40        * rtems/score/cpu.h: Fixed register numbering in comments and made
41        interrupt enable/disable more robust.
42       
432002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
44        * cpu_asm.S: Added support for the debug exception vector, cleaned
45        up the exception processing & exception return stuff.  Re-added
46        EPC in the task context structure so the gdb stub will know where
47        a thread is executing.  Should've left it there in the first place...
48        * idtcpu.h: Added support for the debug exception vector.
49        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
50        stack frame in an interrupt so context switch code can get the
51        userspace EPC when scheduling.
52        * rtems/score/cpu.h: Re-added EPC to the task context.
53
542002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
55
56        * cpu_asm.S: Fixed exception return address, modified FP context
57        switch so FPU is properly enabled and also doesn't screw up the
58        exception FP handling.
59        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
60        returning from exceptions.
61        * iregdef.h: Added R_TAR to the stack frame so the target address
62        can be saved on a per-exception basis.  The new entry is past the
63        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
64        stuff.
65        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
66        to obtain FPU defines without systax errors generated by the C
67        defintions.
68        * cpu.c: Improved interrupt level saves & restores.
69       
702002-02-08      Joel Sherrill <joel@OARcorp.com>
71
72        * iregdef.h, rtems/score/cpu.h: Reordered register in the
73        exception stack frame to better match gdb's expectations.
74
752001-02-05      Joel Sherrill <joel@OARcorp.com>
76
77        * cpu_asm.S: Enhanced to save/restore more registers on
78        exceptions.
79        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
80        register individually and document when it is saved.
81        * idtcpu.h: Added constants for the coprocessor 1 registers
82        revision and status.
83
842001-02-05      Joel Sherrill <joel@OARcorp.com>
85
86        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
87
882001-02-04      Joel Sherrill <joel@OARcorp.com>
89
90        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
91        in the previous patch that has now been confirmed.
92
932001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
94
95        * cpu.c: Enhancements and fixes for modifying the SR when changing
96        the interrupt level.
97        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
98        managed on a per-task basis, improved handling of interrupt levels,
99        and made deferred FP contexts work on the MIPS.
100        * rtems/score/cpu.h: Modified to support above changes.
101
1022002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
103
104        * rtems/Makefile.am: Removed.
105        * rtems/score/Makefile.am: Removed.
106        * configure.ac: Reflect changes above.
107        * Makefile.am: Reflect changes above.
108
1092002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
110
111        * asm.h: Remove #include <rtems/score/targopts.h>.
112        Add #include <rtems/score/cpuopts.h>.
113        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
114
115
1162001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
117
118        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
119
1202001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
121
122        * Makefile.am: Add multilib support.
123
1242001-11-28      Joel Sherrill <joel@OARcorp.com>,
125
126        This was tracked as PR91.
127        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
128        is used to specify if the port uses the standard macro for this (FALSE).
129        A TRUE setting indicates the port provides its own implementation.
130
1312001-10-12      Joel Sherrill <joel@OARcorp.com>
132
133        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
134        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
135        Wayne Bullaughey <wayne@wmi.com>.
136
1372001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
138
139        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
140        * configure.in: Remove.
141        * configure.ac: New file, generated from configure.in by autoupdate.
142
1432001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
144
145        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
146        * Makefile.am: Use 'PREINSTALL_FILES ='.
147
1482001-07-03      Joel Sherrill <joel@OARcorp.com>
149
150        * cpu.c: Fixed typo.
151
1522000-05-24      Joel Sherrill <joel@OARcorp.com>
153
154        * rtems/score/mips.h: Added constants for MIPS exception numbers.
155        All exceptions should be given low numbers and thus can be installed
156        and processed in a uniform manner.  Variances between various MIPS
157        ISA levels were not accounted for.
158
1592001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
160
161        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
162        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
163
1642001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
165
166        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
167        the context initialization to account for floating point tasks. 
168        * rtems/score/mips.h: Added the routines mips_set_cause(),
169        mips_get_fcr31(), and mips_set_fcr31().
170        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
171
1722001-05-07      Joel Sherrill <joel@OARcorp.com>
173
174        * cpu_asm.S: Merged patches from Gregory Menke
175        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
176        stack usage and include nops in the delay slots.
177
1782001-04-20      Joel Sherrill <joel@OARcorp.com>
179
180        * cpu_asm.S: Added code to save and restore SR and EPC to
181        properly support nested interrupts.  Note that the ISR
182        (not RTEMS) enables interrupts allowing the nesting to occur.
183
1842001-03-14      Joel Sherrill <joel@OARcorp.com>
185
186        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
187        Removed unused variable _CPU_Thread_dispatch_pointer
188        and cleaned numerous comments.
189       
1902001-03-13      Joel Sherrill <joel@OARcorp.com>
191
192        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
193        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
194        Also reimplemented some assembly routines in C further reducing
195        the amount of assembly and increasing maintainability.
196
1972001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
198
199        * Makefile.am, rtems/score/Makefile.am:
200        Apply include_*HEADERS instead of H_FILES.
201
2022001-01-12      Joel Sherrill <joel@OARcorp.com>
203
204        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
205        register constraints from "general" to "register".
206
2072001-01-09      Joel Sherrill <joel@OARcorp.com>
208
209        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
210        to make it easier to conditionalize the code for various ISA levels.
211
2122001-01-08      Joel Sherrill <joel@OARcorp.com>
213
214        * idtcpu.h: Commented out definition of "wait".  It was stupid to
215        use such a common word as a macro.
216        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
217        * rtems/score/mips.h: Added include of <idtcpu.h>.
218        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
219
2202001-01-03      Joel Sherrill <joel@OARcorp.com>
221
222        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
223        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
224
2252000-12-19      Joel Sherrill <joel@OARcorp.com>
226
227        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
228        Previous code resulting in the interrupted immediately returning
229        to the caller of the routine it was inside.
230
2312000-12-19      Joel Sherrill <joel@OARcorp.com>
232
233        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
234        because it has not been allocated yet.
235
2362000-12-13      Joel Sherrill <joel@OARcorp.com>
237
238        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
239        * cpu_asm.S: Removed assembly language to vector ISR handler
240        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
241        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
242        longer a constant -- get the real value from libcpu.
243
2442000-12-13      Joel Sherrill <joel@OARcorp.com>
245
246        * cpu_asm.h: Removed.
247        * Makefile.am: Remove cpu_asm.h.
248        * rtems/score/mips64orion.h: Renamed mips.h.
249        * rtems/score/mips.h: New file, formerly mips64orion.h.
250        Header rewritten.
251        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
252        mips_disable_in_interrupt_mask): New macros.
253        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
254        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
255        few defines that were in <cpu_asm.h>.
256        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
257        MIPS ISA 3 is still in assembly for now.
258        (_CPU_Thread_Idle_body): Rewrote in C.
259        * cpu_asm.S: Rewrote file header.
260        (FRAME,ENDFRAME) now in asm.h.
261        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
262        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
263        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
264        leaves other bits in SR alone on task switch.
265        (mips_enable_interrupts,mips_disable_interrupts,
266        mips_enable_global_interrupts,mips_disable_global_interrupts,
267        disable_int, enable_int): Removed.
268        (mips_get_sr): Rewritten as C macro.
269        (_CPU_Thread_Idle_body): Rewritten in C.
270        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
271        placed in libcpu.
272        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
273        to libcpu/mips/shared/interrupts.
274        (general): Cleaned up comment blocks and #if 0 areas.
275        * idtcpu.h: Made ifdef report an error.
276        * iregdef.h: Removed warning.
277        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
278        number defined by libcpu.
279        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
280        to access SR.
281        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
282        (_CPU_Context_Initialize): Honor ISR level in task initialization.
283        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
284
2852000-12-06      Joel Sherrill <joel@OARcorp.com>
286
287        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
288        context should be 32 not 64 bits.
289
2902000-11-30      Joel Sherrill <joel@OARcorp.com>
291
292        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
293        correct name of _CPU_Context_switch_restore.  Added dummy
294        version of exc_utlb_code() so applications would link.
295
2962000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
297
298        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
299
3002000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
301
302        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
303
3042000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
305
306        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
307        Switch to GNU canonicalization.
308
3092000-10-24      Alan Cudmore <alanc@linuxstart.com> and
310        Joel Sherrill <joel@OARcorp.com>
311
312        * This is a major reworking of the mips64orion port to use
313        gcc predefines as much as possible and a big push to multilib
314        the mips port.  The mips64orion port was copied/renamed to mips
315        to be more like other GNU tools.  Alan did most of the technical
316        work of determining how to map old macro names used by the mips64orion
317        port to standard compiler macro definitions.  Joel did the merge
318        with CVS magic to keep individual file history and did the BSP
319        modifications. Details follow:
320        * Makefile.am: idtmon.h in mips64orion port not present.
321        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
322        * cpu.c: Comments added.
323        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
324        First attempt at exception/interrupt processing for ISA level 1
325        and minus any use of IDT/MON added.
326        * idtcpu.h: Conditionals changed to use gcc predefines.
327        * iregdef.h: Ditto.
328        * cpu_asm.h: No real change.  Merger required commit.
329        * rtems/Makefile.am: Ditto.
330        * rtems/score/Makefile.am: Ditto.
331        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
332        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
333        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
334
3352000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
336
337        * Makefile.am: Include compile.am.
338
3392000-08-10      Joel Sherrill <joel@OARcorp.com>
340
341        * ChangeLog: New file.
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