source: rtems/cpukit/score/cpu/mips/ChangeLog @ 8956e27

4.104.114.84.95
Last change on this file since 8956e27 was 8956e27, checked in by Ralf Corsepius <ralf.corsepius@…>, on 01/14/04 at 05:31:43

2004-01-14 Ralf Corsepius <corsepiu@…>

  • Makefile.am: Re-add dirstamps to PREINSTALL_FILES. Add PREINSTALL_FILES to CLEANFILES.
  • Property mode set to 100644
File size: 15.2 KB
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12004-01-14      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
2
3        * Makefile.am: Re-add dirstamps to PREINSTALL_FILES.
4        Add PREINSTALL_FILES to CLEANFILES.
5
62004-01-12      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
7
8        * configure.ac: Requires automake >= 1.8.1.
9
102004-01-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
11
12        * Makefile.am: Include compile.am, again.
13
142004-01-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
15
16        * Makefile.am: Convert to using automake compilation rules.
17
182004-01-07      Joel Sherrill <joel@OARcorp.com>
19
20        * rtems/score/mips.h: Removed junk revision line.
21
222003-12-12      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
23
24        * Makefile.am: Use mkdir_p. Remove dirs from PREINSTALL_FILES.
25
262003-12-12      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
27
28        * configure.ac: Require automake >= 1.8, autoconf >= 2.59.
29
302003-12-01      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
31
32        * Makefile.am: Remove TMPINSTALL_FILES.
33
342003-11-30      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
35
36        * Makefile.am: Add $(dirstamp) to preinstallation rules.
37
382003-11-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
39
40        * Makefile.am: Don't use gmake rules for preinstallation.
41
422003-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
43
44        * configure.ac: Remove RTEMS_CANONICAL_HOST.
45
462003-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
47
48        * configure.ac: Remove RTEMS_CHECK_CPU.
49
502003-09-26      Joel Sherrill <joel@OARcorp.com>
51
52        * rtems/score/cpu.h: Obsoleting HP PA-RISC port and removing all
53        references.
54
552003-09-04      Joel Sherrill <joel@OARcorp.com>
56
57        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
58        rtems/score/types.h: URL for license changed.
59
602003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
61
62        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
63
642003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
65
66        * configure.ac: Remove AC_CONFIG_AUX_DIR.
67
682002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
69
70        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
71        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
72
732002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
74
75        * configure.ac: Fix package name.
76
772002-11-04      Joel Sherrill <joel@OARcorp.com>
78
79        * idtcpu.h: Removed warning.
80
812002-11-01      Joel Sherrill <joel@OARcorp.com>
82
83        * idtcpu.h: Removed warnings.
84
852002-10-28      Joel Sherrill <joel@OARcorp.com>
86
87        * idtcpu.h: Removed warning by turning extra token at the end of
88        an endif into a comment.
89
902002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
91
92        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
93
942002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
95
96        * .cvsignore: Reformat.
97        Add autom4te*cache.
98        Remove autom4te.cache.
99
1002002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
101
102        * cpu_asm.S: Clarified some comments, removed code that forced
103        SR_IEP on when returning from an interrupt.
104
1052002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
106
107        * configure.ac: Add RTEMS_PROG_CCAS
108
1092002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
110
111        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
112        Add AC_PROG_RANLIB.
113
1142002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
115        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
116        deadlock caused by interrupt arriving while dispatching.
117       
1182002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
119
120        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
121        Use ../../../aclocal.
122
1232001-04-03      Joel Sherrill <joel@OARcorp.com>
124
125        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
126        * rtems/score/mipstypes.h: Removed.
127        * rtems/score/types.h: New file via CVS magic.
128        * Makefile.am, rtems/score/cpu.h: Account for name change.
129
1302002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
131
132        * configure.ac:
133        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
134        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
135        * Makefile.am: Remove AUTOMAKE_OPTIONS.
136
1372002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
138
139        * cpu_asm.S: Now compiles on 4600 and 4650.
140
1412002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
142
143        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
144        * rtems/score/cpu.h: Fixed register numbering in comments and made
145        interrupt enable/disable more robust.
146       
1472002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
148        * cpu_asm.S: Added support for the debug exception vector, cleaned
149        up the exception processing & exception return stuff.  Re-added
150        EPC in the task context structure so the gdb stub will know where
151        a thread is executing.  Should've left it there in the first place...
152        * idtcpu.h: Added support for the debug exception vector.
153        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
154        stack frame in an interrupt so context switch code can get the
155        userspace EPC when scheduling.
156        * rtems/score/cpu.h: Re-added EPC to the task context.
157
1582002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
159
160        * cpu_asm.S: Fixed exception return address, modified FP context
161        switch so FPU is properly enabled and also doesn't screw up the
162        exception FP handling.
163        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
164        returning from exceptions.
165        * iregdef.h: Added R_TAR to the stack frame so the target address
166        can be saved on a per-exception basis.  The new entry is past the
167        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
168        stuff.
169        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
170        to obtain FPU defines without syntax errors generated by the C
171        defintions.
172        * cpu.c: Improved interrupt level saves & restores.
173       
1742002-02-08      Joel Sherrill <joel@OARcorp.com>
175
176        * iregdef.h, rtems/score/cpu.h: Reordered register in the
177        exception stack frame to better match gdb's expectations.
178
1792001-02-05      Joel Sherrill <joel@OARcorp.com>
180
181        * cpu_asm.S: Enhanced to save/restore more registers on
182        exceptions.
183        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
184        register individually and document when it is saved.
185        * idtcpu.h: Added constants for the coprocessor 1 registers
186        revision and status.
187
1882001-02-05      Joel Sherrill <joel@OARcorp.com>
189
190        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
191
1922001-02-04      Joel Sherrill <joel@OARcorp.com>
193
194        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
195        in the previous patch that has now been confirmed.
196
1972001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
198
199        * cpu.c: Enhancements and fixes for modifying the SR when changing
200        the interrupt level.
201        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
202        managed on a per-task basis, improved handling of interrupt levels,
203        and made deferred FP contexts work on the MIPS.
204        * rtems/score/cpu.h: Modified to support above changes.
205
2062002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
207
208        * rtems/Makefile.am: Removed.
209        * rtems/score/Makefile.am: Removed.
210        * configure.ac: Reflect changes above.
211        * Makefile.am: Reflect changes above.
212
2132002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
214
215        * asm.h: Remove #include <rtems/score/targopts.h>.
216        Add #include <rtems/score/cpuopts.h>.
217        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
218
219
2202001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
221
222        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
223
2242001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
225
226        * Makefile.am: Add multilib support.
227
2282001-11-28      Joel Sherrill <joel@OARcorp.com>,
229
230        This was tracked as PR91.
231        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
232        is used to specify if the port uses the standard macro for this (FALSE).
233        A TRUE setting indicates the port provides its own implementation.
234
2352001-10-12      Joel Sherrill <joel@OARcorp.com>
236
237        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
238        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
239        Wayne Bullaughey <wayne@wmi.com>.
240
2412001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
242
243        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
244        * configure.in: Remove.
245        * configure.ac: New file, generated from configure.in by autoupdate.
246
2472001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
248
249        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
250        * Makefile.am: Use 'PREINSTALL_FILES ='.
251
2522001-07-03      Joel Sherrill <joel@OARcorp.com>
253
254        * cpu.c: Fixed typo.
255
2562000-05-24      Joel Sherrill <joel@OARcorp.com>
257
258        * rtems/score/mips.h: Added constants for MIPS exception numbers.
259        All exceptions should be given low numbers and thus can be installed
260        and processed in a uniform manner.  Variances between various MIPS
261        ISA levels were not accounted for.
262
2632001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
264
265        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
266        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
267
2682001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
269
270        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
271        the context initialization to account for floating point tasks. 
272        * rtems/score/mips.h: Added the routines mips_set_cause(),
273        mips_get_fcr31(), and mips_set_fcr31().
274        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
275
2762001-05-07      Joel Sherrill <joel@OARcorp.com>
277
278        * cpu_asm.S: Merged patches from Gregory Menke
279        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
280        stack usage and include nops in the delay slots.
281
2822001-04-20      Joel Sherrill <joel@OARcorp.com>
283
284        * cpu_asm.S: Added code to save and restore SR and EPC to
285        properly support nested interrupts.  Note that the ISR
286        (not RTEMS) enables interrupts allowing the nesting to occur.
287
2882001-03-14      Joel Sherrill <joel@OARcorp.com>
289
290        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
291        Removed unused variable _CPU_Thread_dispatch_pointer
292        and cleaned numerous comments.
293       
2942001-03-13      Joel Sherrill <joel@OARcorp.com>
295
296        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
297        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
298        Also reimplemented some assembly routines in C further reducing
299        the amount of assembly and increasing maintainability.
300
3012001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
302
303        * Makefile.am, rtems/score/Makefile.am:
304        Apply include_*HEADERS instead of H_FILES.
305
3062001-01-12      Joel Sherrill <joel@OARcorp.com>
307
308        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
309        register constraints from "general" to "register".
310
3112001-01-09      Joel Sherrill <joel@OARcorp.com>
312
313        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
314        to make it easier to conditionalize the code for various ISA levels.
315
3162001-01-08      Joel Sherrill <joel@OARcorp.com>
317
318        * idtcpu.h: Commented out definition of "wait".  It was stupid to
319        use such a common word as a macro.
320        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
321        * rtems/score/mips.h: Added include of <idtcpu.h>.
322        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
323
3242001-01-03      Joel Sherrill <joel@OARcorp.com>
325
326        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
327        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
328
3292000-12-19      Joel Sherrill <joel@OARcorp.com>
330
331        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
332        Previous code resulting in the interrupted immediately returning
333        to the caller of the routine it was inside.
334
3352000-12-19      Joel Sherrill <joel@OARcorp.com>
336
337        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
338        because it has not been allocated yet.
339
3402000-12-13      Joel Sherrill <joel@OARcorp.com>
341
342        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
343        * cpu_asm.S: Removed assembly language to vector ISR handler
344        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
345        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
346        longer a constant -- get the real value from libcpu.
347
3482000-12-13      Joel Sherrill <joel@OARcorp.com>
349
350        * cpu_asm.h: Removed.
351        * Makefile.am: Remove cpu_asm.h.
352        * rtems/score/mips64orion.h: Renamed mips.h.
353        * rtems/score/mips.h: New file, formerly mips64orion.h.
354        Header rewritten.
355        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
356        mips_disable_in_interrupt_mask): New macros.
357        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
358        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
359        few defines that were in <cpu_asm.h>.
360        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
361        MIPS ISA 3 is still in assembly for now.
362        (_CPU_Thread_Idle_body): Rewrote in C.
363        * cpu_asm.S: Rewrote file header.
364        (FRAME,ENDFRAME) now in asm.h.
365        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
366        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
367        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
368        leaves other bits in SR alone on task switch.
369        (mips_enable_interrupts,mips_disable_interrupts,
370        mips_enable_global_interrupts,mips_disable_global_interrupts,
371        disable_int, enable_int): Removed.
372        (mips_get_sr): Rewritten as C macro.
373        (_CPU_Thread_Idle_body): Rewritten in C.
374        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
375        placed in libcpu.
376        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
377        to libcpu/mips/shared/interrupts.
378        (general): Cleaned up comment blocks and #if 0 areas.
379        * idtcpu.h: Made ifdef report an error.
380        * iregdef.h: Removed warning.
381        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
382        number defined by libcpu.
383        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
384        to access SR.
385        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
386        (_CPU_Context_Initialize): Honor ISR level in task initialization.
387        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
388
3892000-12-06      Joel Sherrill <joel@OARcorp.com>
390
391        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
392        context should be 32 not 64 bits.
393
3942000-11-30      Joel Sherrill <joel@OARcorp.com>
395
396        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
397        correct name of _CPU_Context_switch_restore.  Added dummy
398        version of exc_utlb_code() so applications would link.
399
4002000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
401
402        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
403
4042000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
405
406        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
407
4082000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
409
410        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
411        Switch to GNU canonicalization.
412
4132000-10-24      Alan Cudmore <alanc@linuxstart.com> and
414        Joel Sherrill <joel@OARcorp.com>
415
416        * This is a major reworking of the mips64orion port to use
417        gcc predefines as much as possible and a big push to multilib
418        the mips port.  The mips64orion port was copied/renamed to mips
419        to be more like other GNU tools.  Alan did most of the technical
420        work of determining how to map old macro names used by the mips64orion
421        port to standard compiler macro definitions.  Joel did the merge
422        with CVS magic to keep individual file history and did the BSP
423        modifications. Details follow:
424        * Makefile.am: idtmon.h in mips64orion port not present.
425        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
426        * cpu.c: Comments added.
427        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
428        First attempt at exception/interrupt processing for ISA level 1
429        and minus any use of IDT/MON added.
430        * idtcpu.h: Conditionals changed to use gcc predefines.
431        * iregdef.h: Ditto.
432        * cpu_asm.h: No real change.  Merger required commit.
433        * rtems/Makefile.am: Ditto.
434        * rtems/score/Makefile.am: Ditto.
435        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
436        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
437        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
438
4392000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
440
441        * Makefile.am: Include compile.am.
442
4432000-08-10      Joel Sherrill <joel@OARcorp.com>
444
445        * ChangeLog: New file.
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