source: rtems/cpukit/score/cpu/mips/ChangeLog @ 8727808e

4.104.114.84.95
Last change on this file since 8727808e was 8727808e, checked in by Ralf Corsepius <ralf.corsepius@…>, on 10/21/03 at 14:22:55

2003-10-21 Ralf Corsepius <corsepiu@…>

  • configure.ac: Remove RTEMS_CHECK_CPU.
  • Property mode set to 100644
File size: 14.1 KB
Line 
12003-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
2
3        * configure.ac: Remove RTEMS_CHECK_CPU.
4
52003-09-26      Joel Sherrill <joel@OARcorp.com>
6
7        * rtems/score/cpu.h: Obsoleting HP PA-RISC port and removing all
8        references.
9
102003-09-04      Joel Sherrill <joel@OARcorp.com>
11
12        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
13        rtems/score/types.h: URL for license changed.
14
152003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
16
17        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
18
192003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
20
21        * configure.ac: Remove AC_CONFIG_AUX_DIR.
22
232002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
24
25        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
26        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
27
282002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
29
30        * configure.ac: Fix package name.
31
322002-11-04      Joel Sherrill <joel@OARcorp.com>
33
34        * idtcpu.h: Removed warning.
35
362002-11-01      Joel Sherrill <joel@OARcorp.com>
37
38        * idtcpu.h: Removed warnings.
39
402002-10-28      Joel Sherrill <joel@OARcorp.com>
41
42        * idtcpu.h: Removed warning by turning extra token at the end of
43        an endif into a comment.
44
452002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
46
47        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
48
492002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
50
51        * .cvsignore: Reformat.
52        Add autom4te*cache.
53        Remove autom4te.cache.
54
552002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
56
57        * cpu_asm.S: Clarified some comments, removed code that forced
58        SR_IEP on when returning from an interrupt.
59
602002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
61
62        * configure.ac: Add RTEMS_PROG_CCAS
63
642002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
65
66        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
67        Add AC_PROG_RANLIB.
68
692002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
70        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
71        deadlock caused by interrupt arriving while dispatching.
72       
732002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
74
75        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
76        Use ../../../aclocal.
77
782001-04-03      Joel Sherrill <joel@OARcorp.com>
79
80        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
81        * rtems/score/mipstypes.h: Removed.
82        * rtems/score/types.h: New file via CVS magic.
83        * Makefile.am, rtems/score/cpu.h: Account for name change.
84
852002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
86
87        * configure.ac:
88        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
89        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
90        * Makefile.am: Remove AUTOMAKE_OPTIONS.
91
922002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
93
94        * cpu_asm.S: Now compiles on 4600 and 4650.
95
962002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
97
98        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
99        * rtems/score/cpu.h: Fixed register numbering in comments and made
100        interrupt enable/disable more robust.
101       
1022002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
103        * cpu_asm.S: Added support for the debug exception vector, cleaned
104        up the exception processing & exception return stuff.  Re-added
105        EPC in the task context structure so the gdb stub will know where
106        a thread is executing.  Should've left it there in the first place...
107        * idtcpu.h: Added support for the debug exception vector.
108        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
109        stack frame in an interrupt so context switch code can get the
110        userspace EPC when scheduling.
111        * rtems/score/cpu.h: Re-added EPC to the task context.
112
1132002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
114
115        * cpu_asm.S: Fixed exception return address, modified FP context
116        switch so FPU is properly enabled and also doesn't screw up the
117        exception FP handling.
118        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
119        returning from exceptions.
120        * iregdef.h: Added R_TAR to the stack frame so the target address
121        can be saved on a per-exception basis.  The new entry is past the
122        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
123        stuff.
124        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
125        to obtain FPU defines without syntax errors generated by the C
126        defintions.
127        * cpu.c: Improved interrupt level saves & restores.
128       
1292002-02-08      Joel Sherrill <joel@OARcorp.com>
130
131        * iregdef.h, rtems/score/cpu.h: Reordered register in the
132        exception stack frame to better match gdb's expectations.
133
1342001-02-05      Joel Sherrill <joel@OARcorp.com>
135
136        * cpu_asm.S: Enhanced to save/restore more registers on
137        exceptions.
138        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
139        register individually and document when it is saved.
140        * idtcpu.h: Added constants for the coprocessor 1 registers
141        revision and status.
142
1432001-02-05      Joel Sherrill <joel@OARcorp.com>
144
145        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
146
1472001-02-04      Joel Sherrill <joel@OARcorp.com>
148
149        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
150        in the previous patch that has now been confirmed.
151
1522001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
153
154        * cpu.c: Enhancements and fixes for modifying the SR when changing
155        the interrupt level.
156        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
157        managed on a per-task basis, improved handling of interrupt levels,
158        and made deferred FP contexts work on the MIPS.
159        * rtems/score/cpu.h: Modified to support above changes.
160
1612002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
162
163        * rtems/Makefile.am: Removed.
164        * rtems/score/Makefile.am: Removed.
165        * configure.ac: Reflect changes above.
166        * Makefile.am: Reflect changes above.
167
1682002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
169
170        * asm.h: Remove #include <rtems/score/targopts.h>.
171        Add #include <rtems/score/cpuopts.h>.
172        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
173
174
1752001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
176
177        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
178
1792001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
180
181        * Makefile.am: Add multilib support.
182
1832001-11-28      Joel Sherrill <joel@OARcorp.com>,
184
185        This was tracked as PR91.
186        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
187        is used to specify if the port uses the standard macro for this (FALSE).
188        A TRUE setting indicates the port provides its own implementation.
189
1902001-10-12      Joel Sherrill <joel@OARcorp.com>
191
192        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
193        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
194        Wayne Bullaughey <wayne@wmi.com>.
195
1962001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
197
198        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
199        * configure.in: Remove.
200        * configure.ac: New file, generated from configure.in by autoupdate.
201
2022001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
203
204        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
205        * Makefile.am: Use 'PREINSTALL_FILES ='.
206
2072001-07-03      Joel Sherrill <joel@OARcorp.com>
208
209        * cpu.c: Fixed typo.
210
2112000-05-24      Joel Sherrill <joel@OARcorp.com>
212
213        * rtems/score/mips.h: Added constants for MIPS exception numbers.
214        All exceptions should be given low numbers and thus can be installed
215        and processed in a uniform manner.  Variances between various MIPS
216        ISA levels were not accounted for.
217
2182001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
219
220        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
221        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
222
2232001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
224
225        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
226        the context initialization to account for floating point tasks. 
227        * rtems/score/mips.h: Added the routines mips_set_cause(),
228        mips_get_fcr31(), and mips_set_fcr31().
229        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
230
2312001-05-07      Joel Sherrill <joel@OARcorp.com>
232
233        * cpu_asm.S: Merged patches from Gregory Menke
234        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
235        stack usage and include nops in the delay slots.
236
2372001-04-20      Joel Sherrill <joel@OARcorp.com>
238
239        * cpu_asm.S: Added code to save and restore SR and EPC to
240        properly support nested interrupts.  Note that the ISR
241        (not RTEMS) enables interrupts allowing the nesting to occur.
242
2432001-03-14      Joel Sherrill <joel@OARcorp.com>
244
245        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
246        Removed unused variable _CPU_Thread_dispatch_pointer
247        and cleaned numerous comments.
248       
2492001-03-13      Joel Sherrill <joel@OARcorp.com>
250
251        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
252        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
253        Also reimplemented some assembly routines in C further reducing
254        the amount of assembly and increasing maintainability.
255
2562001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
257
258        * Makefile.am, rtems/score/Makefile.am:
259        Apply include_*HEADERS instead of H_FILES.
260
2612001-01-12      Joel Sherrill <joel@OARcorp.com>
262
263        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
264        register constraints from "general" to "register".
265
2662001-01-09      Joel Sherrill <joel@OARcorp.com>
267
268        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
269        to make it easier to conditionalize the code for various ISA levels.
270
2712001-01-08      Joel Sherrill <joel@OARcorp.com>
272
273        * idtcpu.h: Commented out definition of "wait".  It was stupid to
274        use such a common word as a macro.
275        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
276        * rtems/score/mips.h: Added include of <idtcpu.h>.
277        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
278
2792001-01-03      Joel Sherrill <joel@OARcorp.com>
280
281        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
282        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
283
2842000-12-19      Joel Sherrill <joel@OARcorp.com>
285
286        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
287        Previous code resulting in the interrupted immediately returning
288        to the caller of the routine it was inside.
289
2902000-12-19      Joel Sherrill <joel@OARcorp.com>
291
292        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
293        because it has not been allocated yet.
294
2952000-12-13      Joel Sherrill <joel@OARcorp.com>
296
297        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
298        * cpu_asm.S: Removed assembly language to vector ISR handler
299        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
300        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
301        longer a constant -- get the real value from libcpu.
302
3032000-12-13      Joel Sherrill <joel@OARcorp.com>
304
305        * cpu_asm.h: Removed.
306        * Makefile.am: Remove cpu_asm.h.
307        * rtems/score/mips64orion.h: Renamed mips.h.
308        * rtems/score/mips.h: New file, formerly mips64orion.h.
309        Header rewritten.
310        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
311        mips_disable_in_interrupt_mask): New macros.
312        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
313        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
314        few defines that were in <cpu_asm.h>.
315        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
316        MIPS ISA 3 is still in assembly for now.
317        (_CPU_Thread_Idle_body): Rewrote in C.
318        * cpu_asm.S: Rewrote file header.
319        (FRAME,ENDFRAME) now in asm.h.
320        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
321        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
322        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
323        leaves other bits in SR alone on task switch.
324        (mips_enable_interrupts,mips_disable_interrupts,
325        mips_enable_global_interrupts,mips_disable_global_interrupts,
326        disable_int, enable_int): Removed.
327        (mips_get_sr): Rewritten as C macro.
328        (_CPU_Thread_Idle_body): Rewritten in C.
329        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
330        placed in libcpu.
331        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
332        to libcpu/mips/shared/interrupts.
333        (general): Cleaned up comment blocks and #if 0 areas.
334        * idtcpu.h: Made ifdef report an error.
335        * iregdef.h: Removed warning.
336        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
337        number defined by libcpu.
338        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
339        to access SR.
340        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
341        (_CPU_Context_Initialize): Honor ISR level in task initialization.
342        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
343
3442000-12-06      Joel Sherrill <joel@OARcorp.com>
345
346        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
347        context should be 32 not 64 bits.
348
3492000-11-30      Joel Sherrill <joel@OARcorp.com>
350
351        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
352        correct name of _CPU_Context_switch_restore.  Added dummy
353        version of exc_utlb_code() so applications would link.
354
3552000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
356
357        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
358
3592000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
360
361        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
362
3632000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
364
365        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
366        Switch to GNU canonicalization.
367
3682000-10-24      Alan Cudmore <alanc@linuxstart.com> and
369        Joel Sherrill <joel@OARcorp.com>
370
371        * This is a major reworking of the mips64orion port to use
372        gcc predefines as much as possible and a big push to multilib
373        the mips port.  The mips64orion port was copied/renamed to mips
374        to be more like other GNU tools.  Alan did most of the technical
375        work of determining how to map old macro names used by the mips64orion
376        port to standard compiler macro definitions.  Joel did the merge
377        with CVS magic to keep individual file history and did the BSP
378        modifications. Details follow:
379        * Makefile.am: idtmon.h in mips64orion port not present.
380        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
381        * cpu.c: Comments added.
382        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
383        First attempt at exception/interrupt processing for ISA level 1
384        and minus any use of IDT/MON added.
385        * idtcpu.h: Conditionals changed to use gcc predefines.
386        * iregdef.h: Ditto.
387        * cpu_asm.h: No real change.  Merger required commit.
388        * rtems/Makefile.am: Ditto.
389        * rtems/score/Makefile.am: Ditto.
390        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
391        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
392        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
393
3942000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
395
396        * Makefile.am: Include compile.am.
397
3982000-08-10      Joel Sherrill <joel@OARcorp.com>
399
400        * ChangeLog: New file.
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