source: rtems/cpukit/score/cpu/mips/ChangeLog @ 7a845e2f

4.104.114.84.9
Last change on this file since 7a845e2f was 7a845e2f, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 28, 2002 at 1:47:16 PM

2002-10-28 Joel Sherrill <joel@…>

  • idtcpu.h: Removed warning by turning extra token at the end of an endif into a comment.
  • Property mode set to 100644
File size: 13.1 KB
Line 
12002-10-28      Joel Sherrill <joel@OARcorp.com>
2
3        * idtcpu.h: Removed warning by turning extra token at the end of
4        an endif into a comment.
5
62002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
7
8        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
9
102002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
11
12        * .cvsignore: Reformat.
13        Add autom4te*cache.
14        Remove autom4te.cache.
15
162002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
17
18        * cpu_asm.S: Clarified some comments, removed code that forced
19        SR_IEP on when returning from an interrupt.
20
212002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
22
23        * configure.ac: Add RTEMS_PROG_CCAS
24
252002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
26
27        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
28        Add AC_PROG_RANLIB.
29
302002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
31        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
32        deadlock caused by interrupt arriving while dispatching.
33       
342002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
35
36        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
37        Use ../../../aclocal.
38
392001-04-03      Joel Sherrill <joel@OARcorp.com>
40
41        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
42        * rtems/score/mipstypes.h: Removed.
43        * rtems/score/types.h: New file via CVS magic.
44        * Makefile.am, rtems/score/cpu.h: Account for name change.
45
462002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
47
48        * configure.ac:
49        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
50        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
51        * Makefile.am: Remove AUTOMAKE_OPTIONS.
52
532002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
54
55        * cpu_asm.S: Now compiles on 4600 and 4650.
56
572002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
58
59        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
60        * rtems/score/cpu.h: Fixed register numbering in comments and made
61        interrupt enable/disable more robust.
62       
632002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
64        * cpu_asm.S: Added support for the debug exception vector, cleaned
65        up the exception processing & exception return stuff.  Re-added
66        EPC in the task context structure so the gdb stub will know where
67        a thread is executing.  Should've left it there in the first place...
68        * idtcpu.h: Added support for the debug exception vector.
69        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
70        stack frame in an interrupt so context switch code can get the
71        userspace EPC when scheduling.
72        * rtems/score/cpu.h: Re-added EPC to the task context.
73
742002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
75
76        * cpu_asm.S: Fixed exception return address, modified FP context
77        switch so FPU is properly enabled and also doesn't screw up the
78        exception FP handling.
79        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
80        returning from exceptions.
81        * iregdef.h: Added R_TAR to the stack frame so the target address
82        can be saved on a per-exception basis.  The new entry is past the
83        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
84        stuff.
85        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
86        to obtain FPU defines without syntax errors generated by the C
87        defintions.
88        * cpu.c: Improved interrupt level saves & restores.
89       
902002-02-08      Joel Sherrill <joel@OARcorp.com>
91
92        * iregdef.h, rtems/score/cpu.h: Reordered register in the
93        exception stack frame to better match gdb's expectations.
94
952001-02-05      Joel Sherrill <joel@OARcorp.com>
96
97        * cpu_asm.S: Enhanced to save/restore more registers on
98        exceptions.
99        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
100        register individually and document when it is saved.
101        * idtcpu.h: Added constants for the coprocessor 1 registers
102        revision and status.
103
1042001-02-05      Joel Sherrill <joel@OARcorp.com>
105
106        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
107
1082001-02-04      Joel Sherrill <joel@OARcorp.com>
109
110        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
111        in the previous patch that has now been confirmed.
112
1132001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
114
115        * cpu.c: Enhancements and fixes for modifying the SR when changing
116        the interrupt level.
117        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
118        managed on a per-task basis, improved handling of interrupt levels,
119        and made deferred FP contexts work on the MIPS.
120        * rtems/score/cpu.h: Modified to support above changes.
121
1222002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
123
124        * rtems/Makefile.am: Removed.
125        * rtems/score/Makefile.am: Removed.
126        * configure.ac: Reflect changes above.
127        * Makefile.am: Reflect changes above.
128
1292002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
130
131        * asm.h: Remove #include <rtems/score/targopts.h>.
132        Add #include <rtems/score/cpuopts.h>.
133        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
134
135
1362001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
137
138        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
139
1402001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
141
142        * Makefile.am: Add multilib support.
143
1442001-11-28      Joel Sherrill <joel@OARcorp.com>,
145
146        This was tracked as PR91.
147        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
148        is used to specify if the port uses the standard macro for this (FALSE).
149        A TRUE setting indicates the port provides its own implementation.
150
1512001-10-12      Joel Sherrill <joel@OARcorp.com>
152
153        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
154        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
155        Wayne Bullaughey <wayne@wmi.com>.
156
1572001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
158
159        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
160        * configure.in: Remove.
161        * configure.ac: New file, generated from configure.in by autoupdate.
162
1632001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
164
165        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
166        * Makefile.am: Use 'PREINSTALL_FILES ='.
167
1682001-07-03      Joel Sherrill <joel@OARcorp.com>
169
170        * cpu.c: Fixed typo.
171
1722000-05-24      Joel Sherrill <joel@OARcorp.com>
173
174        * rtems/score/mips.h: Added constants for MIPS exception numbers.
175        All exceptions should be given low numbers and thus can be installed
176        and processed in a uniform manner.  Variances between various MIPS
177        ISA levels were not accounted for.
178
1792001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
180
181        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
182        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
183
1842001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
185
186        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
187        the context initialization to account for floating point tasks. 
188        * rtems/score/mips.h: Added the routines mips_set_cause(),
189        mips_get_fcr31(), and mips_set_fcr31().
190        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
191
1922001-05-07      Joel Sherrill <joel@OARcorp.com>
193
194        * cpu_asm.S: Merged patches from Gregory Menke
195        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
196        stack usage and include nops in the delay slots.
197
1982001-04-20      Joel Sherrill <joel@OARcorp.com>
199
200        * cpu_asm.S: Added code to save and restore SR and EPC to
201        properly support nested interrupts.  Note that the ISR
202        (not RTEMS) enables interrupts allowing the nesting to occur.
203
2042001-03-14      Joel Sherrill <joel@OARcorp.com>
205
206        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
207        Removed unused variable _CPU_Thread_dispatch_pointer
208        and cleaned numerous comments.
209       
2102001-03-13      Joel Sherrill <joel@OARcorp.com>
211
212        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
213        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
214        Also reimplemented some assembly routines in C further reducing
215        the amount of assembly and increasing maintainability.
216
2172001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
218
219        * Makefile.am, rtems/score/Makefile.am:
220        Apply include_*HEADERS instead of H_FILES.
221
2222001-01-12      Joel Sherrill <joel@OARcorp.com>
223
224        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
225        register constraints from "general" to "register".
226
2272001-01-09      Joel Sherrill <joel@OARcorp.com>
228
229        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
230        to make it easier to conditionalize the code for various ISA levels.
231
2322001-01-08      Joel Sherrill <joel@OARcorp.com>
233
234        * idtcpu.h: Commented out definition of "wait".  It was stupid to
235        use such a common word as a macro.
236        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
237        * rtems/score/mips.h: Added include of <idtcpu.h>.
238        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
239
2402001-01-03      Joel Sherrill <joel@OARcorp.com>
241
242        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
243        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
244
2452000-12-19      Joel Sherrill <joel@OARcorp.com>
246
247        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
248        Previous code resulting in the interrupted immediately returning
249        to the caller of the routine it was inside.
250
2512000-12-19      Joel Sherrill <joel@OARcorp.com>
252
253        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
254        because it has not been allocated yet.
255
2562000-12-13      Joel Sherrill <joel@OARcorp.com>
257
258        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
259        * cpu_asm.S: Removed assembly language to vector ISR handler
260        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
261        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
262        longer a constant -- get the real value from libcpu.
263
2642000-12-13      Joel Sherrill <joel@OARcorp.com>
265
266        * cpu_asm.h: Removed.
267        * Makefile.am: Remove cpu_asm.h.
268        * rtems/score/mips64orion.h: Renamed mips.h.
269        * rtems/score/mips.h: New file, formerly mips64orion.h.
270        Header rewritten.
271        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
272        mips_disable_in_interrupt_mask): New macros.
273        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
274        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
275        few defines that were in <cpu_asm.h>.
276        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
277        MIPS ISA 3 is still in assembly for now.
278        (_CPU_Thread_Idle_body): Rewrote in C.
279        * cpu_asm.S: Rewrote file header.
280        (FRAME,ENDFRAME) now in asm.h.
281        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
282        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
283        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
284        leaves other bits in SR alone on task switch.
285        (mips_enable_interrupts,mips_disable_interrupts,
286        mips_enable_global_interrupts,mips_disable_global_interrupts,
287        disable_int, enable_int): Removed.
288        (mips_get_sr): Rewritten as C macro.
289        (_CPU_Thread_Idle_body): Rewritten in C.
290        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
291        placed in libcpu.
292        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
293        to libcpu/mips/shared/interrupts.
294        (general): Cleaned up comment blocks and #if 0 areas.
295        * idtcpu.h: Made ifdef report an error.
296        * iregdef.h: Removed warning.
297        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
298        number defined by libcpu.
299        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
300        to access SR.
301        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
302        (_CPU_Context_Initialize): Honor ISR level in task initialization.
303        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
304
3052000-12-06      Joel Sherrill <joel@OARcorp.com>
306
307        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
308        context should be 32 not 64 bits.
309
3102000-11-30      Joel Sherrill <joel@OARcorp.com>
311
312        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
313        correct name of _CPU_Context_switch_restore.  Added dummy
314        version of exc_utlb_code() so applications would link.
315
3162000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
317
318        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
319
3202000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
321
322        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
323
3242000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
325
326        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
327        Switch to GNU canonicalization.
328
3292000-10-24      Alan Cudmore <alanc@linuxstart.com> and
330        Joel Sherrill <joel@OARcorp.com>
331
332        * This is a major reworking of the mips64orion port to use
333        gcc predefines as much as possible and a big push to multilib
334        the mips port.  The mips64orion port was copied/renamed to mips
335        to be more like other GNU tools.  Alan did most of the technical
336        work of determining how to map old macro names used by the mips64orion
337        port to standard compiler macro definitions.  Joel did the merge
338        with CVS magic to keep individual file history and did the BSP
339        modifications. Details follow:
340        * Makefile.am: idtmon.h in mips64orion port not present.
341        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
342        * cpu.c: Comments added.
343        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
344        First attempt at exception/interrupt processing for ISA level 1
345        and minus any use of IDT/MON added.
346        * idtcpu.h: Conditionals changed to use gcc predefines.
347        * iregdef.h: Ditto.
348        * cpu_asm.h: No real change.  Merger required commit.
349        * rtems/Makefile.am: Ditto.
350        * rtems/score/Makefile.am: Ditto.
351        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
352        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
353        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
354
3552000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
356
357        * Makefile.am: Include compile.am.
358
3592000-08-10      Joel Sherrill <joel@OARcorp.com>
360
361        * ChangeLog: New file.
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