source: rtems/cpukit/score/cpu/mips/ChangeLog @ 75749ff

4.104.114.84.95
Last change on this file since 75749ff was 75749ff, checked in by Joel Sherrill <joel.sherrill@…>, on Nov 1, 2002 at 10:00:27 PM

2002-11-01 Joel Sherrill <joel@…>

  • idtcpu.h: Removed warnings.
  • Property mode set to 100644
File size: 13.1 KB
Line 
12002-11-01      Joel Sherrill <joel@OARcorp.com>
2
3        * idtcpu.h: Removed warnings.
4
52002-10-28      Joel Sherrill <joel@OARcorp.com>
6
7        * idtcpu.h: Removed warning by turning extra token at the end of
8        an endif into a comment.
9
102002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
11
12        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
13
142002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
15
16        * .cvsignore: Reformat.
17        Add autom4te*cache.
18        Remove autom4te.cache.
19
202002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
21
22        * cpu_asm.S: Clarified some comments, removed code that forced
23        SR_IEP on when returning from an interrupt.
24
252002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
26
27        * configure.ac: Add RTEMS_PROG_CCAS
28
292002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
30
31        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
32        Add AC_PROG_RANLIB.
33
342002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
35        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
36        deadlock caused by interrupt arriving while dispatching.
37       
382002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
39
40        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
41        Use ../../../aclocal.
42
432001-04-03      Joel Sherrill <joel@OARcorp.com>
44
45        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
46        * rtems/score/mipstypes.h: Removed.
47        * rtems/score/types.h: New file via CVS magic.
48        * Makefile.am, rtems/score/cpu.h: Account for name change.
49
502002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
51
52        * configure.ac:
53        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
54        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
55        * Makefile.am: Remove AUTOMAKE_OPTIONS.
56
572002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
58
59        * cpu_asm.S: Now compiles on 4600 and 4650.
60
612002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
62
63        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
64        * rtems/score/cpu.h: Fixed register numbering in comments and made
65        interrupt enable/disable more robust.
66       
672002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
68        * cpu_asm.S: Added support for the debug exception vector, cleaned
69        up the exception processing & exception return stuff.  Re-added
70        EPC in the task context structure so the gdb stub will know where
71        a thread is executing.  Should've left it there in the first place...
72        * idtcpu.h: Added support for the debug exception vector.
73        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
74        stack frame in an interrupt so context switch code can get the
75        userspace EPC when scheduling.
76        * rtems/score/cpu.h: Re-added EPC to the task context.
77
782002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
79
80        * cpu_asm.S: Fixed exception return address, modified FP context
81        switch so FPU is properly enabled and also doesn't screw up the
82        exception FP handling.
83        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
84        returning from exceptions.
85        * iregdef.h: Added R_TAR to the stack frame so the target address
86        can be saved on a per-exception basis.  The new entry is past the
87        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
88        stuff.
89        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
90        to obtain FPU defines without syntax errors generated by the C
91        defintions.
92        * cpu.c: Improved interrupt level saves & restores.
93       
942002-02-08      Joel Sherrill <joel@OARcorp.com>
95
96        * iregdef.h, rtems/score/cpu.h: Reordered register in the
97        exception stack frame to better match gdb's expectations.
98
992001-02-05      Joel Sherrill <joel@OARcorp.com>
100
101        * cpu_asm.S: Enhanced to save/restore more registers on
102        exceptions.
103        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
104        register individually and document when it is saved.
105        * idtcpu.h: Added constants for the coprocessor 1 registers
106        revision and status.
107
1082001-02-05      Joel Sherrill <joel@OARcorp.com>
109
110        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
111
1122001-02-04      Joel Sherrill <joel@OARcorp.com>
113
114        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
115        in the previous patch that has now been confirmed.
116
1172001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
118
119        * cpu.c: Enhancements and fixes for modifying the SR when changing
120        the interrupt level.
121        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
122        managed on a per-task basis, improved handling of interrupt levels,
123        and made deferred FP contexts work on the MIPS.
124        * rtems/score/cpu.h: Modified to support above changes.
125
1262002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
127
128        * rtems/Makefile.am: Removed.
129        * rtems/score/Makefile.am: Removed.
130        * configure.ac: Reflect changes above.
131        * Makefile.am: Reflect changes above.
132
1332002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
134
135        * asm.h: Remove #include <rtems/score/targopts.h>.
136        Add #include <rtems/score/cpuopts.h>.
137        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
138
139
1402001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
141
142        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
143
1442001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
145
146        * Makefile.am: Add multilib support.
147
1482001-11-28      Joel Sherrill <joel@OARcorp.com>,
149
150        This was tracked as PR91.
151        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
152        is used to specify if the port uses the standard macro for this (FALSE).
153        A TRUE setting indicates the port provides its own implementation.
154
1552001-10-12      Joel Sherrill <joel@OARcorp.com>
156
157        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
158        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
159        Wayne Bullaughey <wayne@wmi.com>.
160
1612001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
162
163        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
164        * configure.in: Remove.
165        * configure.ac: New file, generated from configure.in by autoupdate.
166
1672001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
168
169        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
170        * Makefile.am: Use 'PREINSTALL_FILES ='.
171
1722001-07-03      Joel Sherrill <joel@OARcorp.com>
173
174        * cpu.c: Fixed typo.
175
1762000-05-24      Joel Sherrill <joel@OARcorp.com>
177
178        * rtems/score/mips.h: Added constants for MIPS exception numbers.
179        All exceptions should be given low numbers and thus can be installed
180        and processed in a uniform manner.  Variances between various MIPS
181        ISA levels were not accounted for.
182
1832001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
184
185        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
186        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
187
1882001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
189
190        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
191        the context initialization to account for floating point tasks. 
192        * rtems/score/mips.h: Added the routines mips_set_cause(),
193        mips_get_fcr31(), and mips_set_fcr31().
194        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
195
1962001-05-07      Joel Sherrill <joel@OARcorp.com>
197
198        * cpu_asm.S: Merged patches from Gregory Menke
199        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
200        stack usage and include nops in the delay slots.
201
2022001-04-20      Joel Sherrill <joel@OARcorp.com>
203
204        * cpu_asm.S: Added code to save and restore SR and EPC to
205        properly support nested interrupts.  Note that the ISR
206        (not RTEMS) enables interrupts allowing the nesting to occur.
207
2082001-03-14      Joel Sherrill <joel@OARcorp.com>
209
210        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
211        Removed unused variable _CPU_Thread_dispatch_pointer
212        and cleaned numerous comments.
213       
2142001-03-13      Joel Sherrill <joel@OARcorp.com>
215
216        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
217        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
218        Also reimplemented some assembly routines in C further reducing
219        the amount of assembly and increasing maintainability.
220
2212001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
222
223        * Makefile.am, rtems/score/Makefile.am:
224        Apply include_*HEADERS instead of H_FILES.
225
2262001-01-12      Joel Sherrill <joel@OARcorp.com>
227
228        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
229        register constraints from "general" to "register".
230
2312001-01-09      Joel Sherrill <joel@OARcorp.com>
232
233        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
234        to make it easier to conditionalize the code for various ISA levels.
235
2362001-01-08      Joel Sherrill <joel@OARcorp.com>
237
238        * idtcpu.h: Commented out definition of "wait".  It was stupid to
239        use such a common word as a macro.
240        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
241        * rtems/score/mips.h: Added include of <idtcpu.h>.
242        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
243
2442001-01-03      Joel Sherrill <joel@OARcorp.com>
245
246        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
247        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
248
2492000-12-19      Joel Sherrill <joel@OARcorp.com>
250
251        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
252        Previous code resulting in the interrupted immediately returning
253        to the caller of the routine it was inside.
254
2552000-12-19      Joel Sherrill <joel@OARcorp.com>
256
257        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
258        because it has not been allocated yet.
259
2602000-12-13      Joel Sherrill <joel@OARcorp.com>
261
262        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
263        * cpu_asm.S: Removed assembly language to vector ISR handler
264        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
265        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
266        longer a constant -- get the real value from libcpu.
267
2682000-12-13      Joel Sherrill <joel@OARcorp.com>
269
270        * cpu_asm.h: Removed.
271        * Makefile.am: Remove cpu_asm.h.
272        * rtems/score/mips64orion.h: Renamed mips.h.
273        * rtems/score/mips.h: New file, formerly mips64orion.h.
274        Header rewritten.
275        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
276        mips_disable_in_interrupt_mask): New macros.
277        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
278        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
279        few defines that were in <cpu_asm.h>.
280        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
281        MIPS ISA 3 is still in assembly for now.
282        (_CPU_Thread_Idle_body): Rewrote in C.
283        * cpu_asm.S: Rewrote file header.
284        (FRAME,ENDFRAME) now in asm.h.
285        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
286        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
287        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
288        leaves other bits in SR alone on task switch.
289        (mips_enable_interrupts,mips_disable_interrupts,
290        mips_enable_global_interrupts,mips_disable_global_interrupts,
291        disable_int, enable_int): Removed.
292        (mips_get_sr): Rewritten as C macro.
293        (_CPU_Thread_Idle_body): Rewritten in C.
294        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
295        placed in libcpu.
296        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
297        to libcpu/mips/shared/interrupts.
298        (general): Cleaned up comment blocks and #if 0 areas.
299        * idtcpu.h: Made ifdef report an error.
300        * iregdef.h: Removed warning.
301        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
302        number defined by libcpu.
303        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
304        to access SR.
305        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
306        (_CPU_Context_Initialize): Honor ISR level in task initialization.
307        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
308
3092000-12-06      Joel Sherrill <joel@OARcorp.com>
310
311        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
312        context should be 32 not 64 bits.
313
3142000-11-30      Joel Sherrill <joel@OARcorp.com>
315
316        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
317        correct name of _CPU_Context_switch_restore.  Added dummy
318        version of exc_utlb_code() so applications would link.
319
3202000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
321
322        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
323
3242000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
325
326        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
327
3282000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
329
330        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
331        Switch to GNU canonicalization.
332
3332000-10-24      Alan Cudmore <alanc@linuxstart.com> and
334        Joel Sherrill <joel@OARcorp.com>
335
336        * This is a major reworking of the mips64orion port to use
337        gcc predefines as much as possible and a big push to multilib
338        the mips port.  The mips64orion port was copied/renamed to mips
339        to be more like other GNU tools.  Alan did most of the technical
340        work of determining how to map old macro names used by the mips64orion
341        port to standard compiler macro definitions.  Joel did the merge
342        with CVS magic to keep individual file history and did the BSP
343        modifications. Details follow:
344        * Makefile.am: idtmon.h in mips64orion port not present.
345        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
346        * cpu.c: Comments added.
347        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
348        First attempt at exception/interrupt processing for ISA level 1
349        and minus any use of IDT/MON added.
350        * idtcpu.h: Conditionals changed to use gcc predefines.
351        * iregdef.h: Ditto.
352        * cpu_asm.h: No real change.  Merger required commit.
353        * rtems/Makefile.am: Ditto.
354        * rtems/score/Makefile.am: Ditto.
355        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
356        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
357        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
358
3592000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
360
361        * Makefile.am: Include compile.am.
362
3632000-08-10      Joel Sherrill <joel@OARcorp.com>
364
365        * ChangeLog: New file.
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