source: rtems/cpukit/score/cpu/mips/ChangeLog @ 6d42b4c6

4.115
Last change on this file since 6d42b4c6 was 6d42b4c6, checked in by Joel Sherrill <joel.sherrill@…>, on 06/29/10 at 00:34:00

2010-06-28 Joel Sherrill <joel.sherrill@…>

PR 1573/cpukit

  • cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which contains the information required by RTEMS for each CPU core. This encapsulates information such as thread executing, heir, idle and dispatch needed.
  • Property mode set to 100644
File size: 21.7 KB
Line 
12010-06-28      Joel Sherrill <joel.sherrill@oarcorp.com>
2
3        PR 1573/cpukit
4        * cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which
5        contains the information required by RTEMS for each CPU core. This
6        encapsulates information such as thread executing, heir, idle and
7        dispatch needed.
8
92010-06-16      Joel Sherrill <joel.sherrill@oarcorp.com>
10
11        * cpu_asm.S: Remove trailing tabs.
12
132010-04-25      Joel Sherrill <joel.sherrilL@OARcorp.com>
14
15        * cpu.c, rtems/score/cpu.h: Move _CPU_Context_Initialize() to cpu.c so
16        it is easier to make warning free.
17
182010-04-25      Joel Sherrill <joel.sherrilL@OARcorp.com>
19
20        * rtems/score/cpu.h: Remove warning in _CPU_Context_Initialize.
21
222010-03-27      Joel Sherrill <joel.sherrill@oarcorp.com>
23
24        * cpu.c, cpu_asm.S: Add include of config.h
25
262009-03-12      Joel Sherrill <joel.sherrill@OARcorp.com>
27
28        PR 1385/cpukit
29        * cpu_asm.S: When the type rtems_boolean was switched to the C99 bool,
30        the size changed from 4 bytes to 1 byte. The interrupt dispatching
31        code accesses two boolean variables for scheduling purposes and the
32        assembly implementations of this code did not get updated.
33
342009-02-12      Joel Sherrill <joel.sherrill@oarcorp.com>
35
36        * cpu.c, rtems/score/cpu.h: Change prototype of IDLE thread to
37        consistently return void * and take a uintptr_t argument.
38
392009-02-11      Joel Sherrill <joel.sherrill@oarcorp.com>
40
41        * cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and
42        passing address of _Thread_Dispatch to _CPU_Initialize. Clean up
43        comments.
44
452008-09-11      Ralf Corsépius <ralf.corsepius@rtems.org>
46
47        * rtems/score/types.h: Do not define boolean, single_precision,
48        double_precision unless RTEMS_DEPRECATED_TYPES is given.
49
502008-08-21      Ralf Corsépius <ralf.corsepius@rtems.org>
51
52        * rtems/score/types.h: Include stdbool.h.
53        Use bool as base-type for boolean.
54
552008-07-31      Joel Sherrill <joel.sherrill@OARcorp.com>
56
57        * cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads.
58
592008-06-05      Joel Sherrill <joel.sherrill@OARcorp.com>
60
61        * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
62        parameter to indicate that the port uses the Simple Vectored
63        Interrupt model or the Programmable Interrupt Controller Model. The
64        PIC model is implemented primarily in the BSP and it is responsible
65        for all memory allocation.
66
672008-06-04      Joel Sherrill <joel.sherrill@OARcorp.com>
68
69        * rtems/score/cpu.h: Use a constant for CPU_STACK_MINIMUM_SIZE so it
70        can be used in cpp expressions. Using sizeof() requires actually
71        compiling the file.
72
732007-12-17      Joel Sherrill <joel.sherrill@oarcorp.com>
74
75        * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.
76
772007-12-04      Joel Sherrill <joel.sherrill@OARcorp.com>
78
79        * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU
80        Table to Configuration Table. Eliminate CPU Table from all ports.
81        Delete references to CPU Table in all forms.
82
832007-12-03      Joel Sherrill <joel.sherrill@OARcorp.com>
84
85        * rtems/score/cpu.h: Moved most of the remaining CPU Table fields to
86        the Configuration Table. This included pretasking_hook,
87        predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace,
88        extra_mpci_receive_server_stack, stack_allocate_hook, and
89        stack_free_hook. As a side-effect of this effort some multiprocessing
90        code was made conditional and some style clean up occurred.
91
922007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
93
94        * rtems/score/cpu.h: Eliminate the clicks_per_microsecond field in the
95        MIPS CPU Table and define another mechanism for drivers to obtain
96        this information.
97
982007-08-04      Ralf Corsépius <ralf.corsepius@rtems.org>
99
100        * rtems/score/cpu.h: Use uintptr_t instead of uint32_t.
101
1022007-05-09      Ralf Corsépius <ralf.corsepius@rtems.org>
103
104        * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
105
1062007-04-17      Ralf Corsépius <ralf.corsepius@rtems.org>
107
108        * rtems/score/cpu.h:
109          Use Context_Control_fp* instead of void* for fp_contexts.
110          Eliminate evil casts.
111
1122006-11-17      Ralf Corsépius <ralf.corsepius@rtems.org>
113
114        * rtems/score/types.h: Remove unsigned64, signed64.
115
1162006-06-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
117
118        * cpu.c: Added __mips==32 to fix build problems on those targets
119        caused by the Bruce Robinson.
120
1212006-06-08 Bruce Robinson <brucer@pmccorp.com>
122
123        * cpu.c: Add int64 types for __mips==3 cpus, incorporate
124           mips_interrupt_mask() into mask computations
125        * cpu_asm.S: Add int64 register save/restores for __mips==3 cpus.  Adjustment
126           of mips1 vs mips3 macros.
127        * cpu.h: Add int64 types for __mips==3 cpus.
128       
1292006-03-17      Ralf Corsepius <ralf.corsepius@rtems.org>
130
131        * cpu.c (_CPU_Initialize): Add fpu initialization.
132        * rtems/score/cpu.h: Setup CPU_*_ENDIAN from GCC's__MIPS{EL|EB}__.
133        (Partial merger of submission by Bruce Robinson <brucer@pmccorp.com>).
134
1352006-01-16      Joel Sherrill <joel@OARcorp.com>
136
137        * rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
138        As a side-effect, grammar and spelling errors were corrected, spacing
139        errors were address, and some variable names were improved.
140
1412005-11-18      Joel Sherrill <joel@OARcorp.com>
142
143        * rtems/score/cpu.h: Eliminate use of unsigned32.
144
1452005-11-08      Ralf Corsepius <ralf.corsepius@rtems.org>
146
147        * rtems/score/types.h: Eliminate unsigned16, unsigned32.
148
1492005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
150
151        * rtems/asm.h: Remove private version of CONCAT macros.
152        Include <rtems/concat.h> instead.
153
1542005-04-26      Joel Sherrill <joel@OARcorp.com>
155
156        * rtems/asm.h: Eliminate warnings.
157
1582005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
159
160        * Makefile.am: Split out preinstallation rules.
161        * preinstall.am: New (Split out from Makefile.am).
162
1632005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
164
165        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
166        Header guards cleanup.
167
1682005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
169
170        PR 754/rtems
171        * rtems/asm.h: New (relocated from .).
172        * asm.h: Remove (moved to rtems/asm.h).
173        * Makefile.am: Reflect changes above.
174
1752005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
176
177        PR rtems/752
178        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
179        New header guards.
180        * idtcpu.h, iregdef.h: Remove.
181        * Makefile.am: Reflect changes above.
182
1832004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
184
185        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
186        New header guards.
187
1882005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
189
190        * rtems/score/types.h: Remove signed8, signed16, signed32,
191        unsigned8, unsigned16, unsigned32.
192
1932005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
194
195        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
196
1972005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
198
199        * rtems/score/types.h: #include <rtems/stdint.h>.
200
2012005-01-07      Joel Sherrill <joel@OARcorp.com>
202
203        * rtems/score/cpu.h: Remove warnings.
204
2052005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
206
207        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
208
2092005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
210
211        PR 739
212        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
213        when compiling cpu_asm.S.  Problem was a #define sneaked in in
214        version 1.11, no ill effects would have only affected R4000
215        builds.
216
2172005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
218
219        PR 737
220        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
221        slot when compiling cpu_asm.S
222
2232005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
224
225        * Makefile.am: Remove build-variant support.
226
2272004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
228
229        PR 730
230        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
231        for rtems-4.7.
232
2332004-04-09      Joel Sherrill <joel@OARcorp.com>
234
235        PR 605/bsps
236        * cpu.c: Do not use C++ style comments.
237
2382004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
239        PR 601
240        * cpu_asm.S: Added __mips==32 support for R4000 processors running
241        32 bit code.  Fixed #define problems that caused fpu code to
242        always be included even when no fpu is present.
243
2442004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
245
246        PR 598/bsps
247        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
248        status/control register on context switches. Missing this register
249        was causing intermittent floating point errors.
250
2512003-09-04      Joel Sherrill <joel@OARcorp.com>
252
253        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
254        rtems/score/types.h: URL for license changed.
255
2562003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
257
258        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
259
2602003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
261
262        * configure.ac: Remove AC_CONFIG_AUX_DIR.
263
2642002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
265
266        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
267        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
268
2692002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
270
271        * configure.ac: Fix package name.
272
2732002-11-04      Joel Sherrill <joel@OARcorp.com>
274
275        * idtcpu.h: Removed warning.
276
2772002-11-01      Joel Sherrill <joel@OARcorp.com>
278
279        * idtcpu.h: Removed warnings.
280
2812002-10-28      Joel Sherrill <joel@OARcorp.com>
282
283        * idtcpu.h: Removed warning by turning extra token at the end of
284        an endif into a comment.
285
2862002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
287
288        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
289
2902002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
291
292        * .cvsignore: Reformat.
293        Add autom4te*cache.
294        Remove autom4te.cache.
295
2962002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
297
298        * cpu_asm.S: Clarified some comments, removed code that forced
299        SR_IEP on when returning from an interrupt.
300
3012002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
302
303        * configure.ac: Add RTEMS_PROG_CCAS
304
3052002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
306
307        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
308        Add AC_PROG_RANLIB.
309
3102002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
311        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
312        deadlock caused by interrupt arriving while dispatching.
313       
3142002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
315
316        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
317        Use ../../../aclocal.
318
3192001-04-03      Joel Sherrill <joel@OARcorp.com>
320
321        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
322        * rtems/score/mipstypes.h: Removed.
323        * rtems/score/types.h: New file via CVS magic.
324        * Makefile.am, rtems/score/cpu.h: Account for name change.
325
3262002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
327
328        * configure.ac:
329        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
330        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
331        * Makefile.am: Remove AUTOMAKE_OPTIONS.
332
3332002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
334
335        * cpu_asm.S: Now compiles on 4600 and 4650.
336
3372002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
338
339        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
340        * rtems/score/cpu.h: Fixed register numbering in comments and made
341        interrupt enable/disable more robust.
342       
3432002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
344        * cpu_asm.S: Added support for the debug exception vector, cleaned
345        up the exception processing & exception return stuff.  Re-added
346        EPC in the task context structure so the gdb stub will know where
347        a thread is executing.  Should've left it there in the first place...
348        * idtcpu.h: Added support for the debug exception vector.
349        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
350        stack frame in an interrupt so context switch code can get the
351        userspace EPC when scheduling.
352        * rtems/score/cpu.h: Re-added EPC to the task context.
353
3542002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
355
356        * cpu_asm.S: Fixed exception return address, modified FP context
357        switch so FPU is properly enabled and also doesn't screw up the
358        exception FP handling.
359        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
360        returning from exceptions.
361        * iregdef.h: Added R_TAR to the stack frame so the target address
362        can be saved on a per-exception basis.  The new entry is past the
363        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
364        stuff.
365        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
366        to obtain FPU defines without syntax errors generated by the C
367        defintions.
368        * cpu.c: Improved interrupt level saves & restores.
369       
3702002-02-08      Joel Sherrill <joel@OARcorp.com>
371
372        * iregdef.h, rtems/score/cpu.h: Reordered register in the
373        exception stack frame to better match gdb's expectations.
374
3752001-02-05      Joel Sherrill <joel@OARcorp.com>
376
377        * cpu_asm.S: Enhanced to save/restore more registers on
378        exceptions.
379        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
380        register individually and document when it is saved.
381        * idtcpu.h: Added constants for the coprocessor 1 registers
382        revision and status.
383
3842001-02-05      Joel Sherrill <joel@OARcorp.com>
385
386        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
387
3882001-02-04      Joel Sherrill <joel@OARcorp.com>
389
390        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
391        in the previous patch that has now been confirmed.
392
3932001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
394
395        * cpu.c: Enhancements and fixes for modifying the SR when changing
396        the interrupt level.
397        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
398        managed on a per-task basis, improved handling of interrupt levels,
399        and made deferred FP contexts work on the MIPS.
400        * rtems/score/cpu.h: Modified to support above changes.
401
4022002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
403
404        * rtems/Makefile.am: Removed.
405        * rtems/score/Makefile.am: Removed.
406        * configure.ac: Reflect changes above.
407        * Makefile.am: Reflect changes above.
408
4092002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
410
411        * asm.h: Remove #include <rtems/score/targopts.h>.
412        Add #include <rtems/score/cpuopts.h>.
413        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
414
415
4162001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
417
418        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
419
4202001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
421
422        * Makefile.am: Add multilib support.
423
4242001-11-28      Joel Sherrill <joel@OARcorp.com>,
425
426        This was tracked as PR91.
427        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
428        is used to specify if the port uses the standard macro for this (FALSE).
429        A TRUE setting indicates the port provides its own implementation.
430
4312001-10-12      Joel Sherrill <joel@OARcorp.com>
432
433        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
434        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
435        Wayne Bullaughey <wayne@wmi.com>.
436
4372001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
438
439        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
440        * configure.in: Remove.
441        * configure.ac: New file, generated from configure.in by autoupdate.
442
4432001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
444
445        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
446        * Makefile.am: Use 'PREINSTALL_FILES ='.
447
4482001-07-03      Joel Sherrill <joel@OARcorp.com>
449
450        * cpu.c: Fixed typo.
451
4522000-05-24      Joel Sherrill <joel@OARcorp.com>
453
454        * rtems/score/mips.h: Added constants for MIPS exception numbers.
455        All exceptions should be given low numbers and thus can be installed
456        and processed in a uniform manner.  Variances between various MIPS
457        ISA levels were not accounted for.
458
4592001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
460
461        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
462        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
463
4642001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
465
466        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
467        the context initialization to account for floating point tasks. 
468        * rtems/score/mips.h: Added the routines mips_set_cause(),
469        mips_get_fcr31(), and mips_set_fcr31().
470        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
471
4722001-05-07      Joel Sherrill <joel@OARcorp.com>
473
474        * cpu_asm.S: Merged patches from Gregory Menke
475        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
476        stack usage and include nops in the delay slots.
477
4782001-04-20      Joel Sherrill <joel@OARcorp.com>
479
480        * cpu_asm.S: Added code to save and restore SR and EPC to
481        properly support nested interrupts.  Note that the ISR
482        (not RTEMS) enables interrupts allowing the nesting to occur.
483
4842001-03-14      Joel Sherrill <joel@OARcorp.com>
485
486        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
487        Removed unused variable _CPU_Thread_dispatch_pointer
488        and cleaned numerous comments.
489       
4902001-03-13      Joel Sherrill <joel@OARcorp.com>
491
492        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
493        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
494        Also reimplemented some assembly routines in C further reducing
495        the amount of assembly and increasing maintainability.
496
4972001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
498
499        * Makefile.am, rtems/score/Makefile.am:
500        Apply include_*HEADERS instead of H_FILES.
501
5022001-01-12      Joel Sherrill <joel@OARcorp.com>
503
504        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
505        register constraints from "general" to "register".
506
5072001-01-09      Joel Sherrill <joel@OARcorp.com>
508
509        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
510        to make it easier to conditionalize the code for various ISA levels.
511
5122001-01-08      Joel Sherrill <joel@OARcorp.com>
513
514        * idtcpu.h: Commented out definition of "wait".  It was stupid to
515        use such a common word as a macro.
516        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
517        * rtems/score/mips.h: Added include of <idtcpu.h>.
518        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
519
5202001-01-03      Joel Sherrill <joel@OARcorp.com>
521
522        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
523        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
524
5252000-12-19      Joel Sherrill <joel@OARcorp.com>
526
527        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
528        Previous code resulting in the interrupted immediately returning
529        to the caller of the routine it was inside.
530
5312000-12-19      Joel Sherrill <joel@OARcorp.com>
532
533        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
534        because it has not been allocated yet.
535
5362000-12-13      Joel Sherrill <joel@OARcorp.com>
537
538        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
539        * cpu_asm.S: Removed assembly language to vector ISR handler
540        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
541        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
542        longer a constant -- get the real value from libcpu.
543
5442000-12-13      Joel Sherrill <joel@OARcorp.com>
545
546        * cpu_asm.h: Removed.
547        * Makefile.am: Remove cpu_asm.h.
548        * rtems/score/mips64orion.h: Renamed mips.h.
549        * rtems/score/mips.h: New file, formerly mips64orion.h.
550        Header rewritten.
551        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
552        mips_disable_in_interrupt_mask): New macros.
553        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
554        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
555        few defines that were in <cpu_asm.h>.
556        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
557        MIPS ISA 3 is still in assembly for now.
558        (_CPU_Thread_Idle_body): Rewrote in C.
559        * cpu_asm.S: Rewrote file header.
560        (FRAME,ENDFRAME) now in asm.h.
561        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
562        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
563        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
564        leaves other bits in SR alone on task switch.
565        (mips_enable_interrupts,mips_disable_interrupts,
566        mips_enable_global_interrupts,mips_disable_global_interrupts,
567        disable_int, enable_int): Removed.
568        (mips_get_sr): Rewritten as C macro.
569        (_CPU_Thread_Idle_body): Rewritten in C.
570        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
571        placed in libcpu.
572        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
573        to libcpu/mips/shared/interrupts.
574        (general): Cleaned up comment blocks and #if 0 areas.
575        * idtcpu.h: Made ifdef report an error.
576        * iregdef.h: Removed warning.
577        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
578        number defined by libcpu.
579        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
580        to access SR.
581        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
582        (_CPU_Context_Initialize): Honor ISR level in task initialization.
583        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
584
5852000-12-06      Joel Sherrill <joel@OARcorp.com>
586
587        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
588        context should be 32 not 64 bits.
589
5902000-11-30      Joel Sherrill <joel@OARcorp.com>
591
592        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
593        correct name of _CPU_Context_switch_restore.  Added dummy
594        version of exc_utlb_code() so applications would link.
595
5962000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
597
598        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
599
6002000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
601
602        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
603
6042000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
605
606        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
607        Switch to GNU canonicalization.
608
6092000-10-24      Alan Cudmore <alanc@linuxstart.com> and
610        Joel Sherrill <joel@OARcorp.com>
611
612        * This is a major reworking of the mips64orion port to use
613        gcc predefines as much as possible and a big push to multilib
614        the mips port.  The mips64orion port was copied/renamed to mips
615        to be more like other GNU tools.  Alan did most of the technical
616        work of determining how to map old macro names used by the mips64orion
617        port to standard compiler macro definitions.  Joel did the merge
618        with CVS magic to keep individual file history and did the BSP
619        modifications. Details follow:
620        * Makefile.am: idtmon.h in mips64orion port not present.
621        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
622        * cpu.c: Comments added.
623        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
624        First attempt at exception/interrupt processing for ISA level 1
625        and minus any use of IDT/MON added.
626        * idtcpu.h: Conditionals changed to use gcc predefines.
627        * iregdef.h: Ditto.
628        * cpu_asm.h: No real change.  Merger required commit.
629        * rtems/Makefile.am: Ditto.
630        * rtems/score/Makefile.am: Ditto.
631        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
632        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
633        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
634
6352000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
636
637        * Makefile.am: Include compile.am.
638
6392000-08-10      Joel Sherrill <joel@OARcorp.com>
640
641        * ChangeLog: New file.
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