source: rtems/cpukit/score/cpu/mips/ChangeLog @ 6162bc2

4.104.115
Last change on this file since 6162bc2 was 6162bc2, checked in by Ralf Corsepius <ralf.corsepius@…>, on 09/11/08 at 14:10:16

2008-09-11 Ralf Corsépius <ralf.corsepius@…>

  • rtems/score/types.h: Do not define boolean, single_precision, double_precision unless RTEMS_DEPRECATED_TYPES is given.
  • Property mode set to 100644
File size: 20.3 KB
Line 
12008-09-11      Ralf Corsépius <ralf.corsepius@rtems.org>
2
3        * rtems/score/types.h: Do not define boolean, single_precision,
4        double_precision unless RTEMS_DEPRECATED_TYPES is given.
5
62008-08-21      Ralf Corsépius <ralf.corsepius@rtems.org>
7
8        * rtems/score/types.h: Include stdbool.h.
9        Use bool as base-type for boolean.
10
112008-07-31      Joel Sherrill <joel.sherrill@OARcorp.com>
12
13        * cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads.
14
152008-06-05      Joel Sherrill <joel.sherrill@OARcorp.com>
16
17        * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
18        parameter to indicate that the port uses the Simple Vectored
19        Interrupt model or the Programmable Interrupt Controller Model. The
20        PIC model is implemented primarily in the BSP and it is responsible
21        for all memory allocation.
22
232008-06-04      Joel Sherrill <joel.sherrill@OARcorp.com>
24
25        * rtems/score/cpu.h: Use a constant for CPU_STACK_MINIMUM_SIZE so it
26        can be used in cpp expressions. Using sizeof() requires actually
27        compiling the file.
28
292007-12-17      Joel Sherrill <joel.sherrill@oarcorp.com>
30
31        * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.
32
332007-12-04      Joel Sherrill <joel.sherrill@OARcorp.com>
34
35        * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU
36        Table to Configuration Table. Eliminate CPU Table from all ports.
37        Delete references to CPU Table in all forms.
38
392007-12-03      Joel Sherrill <joel.sherrill@OARcorp.com>
40
41        * rtems/score/cpu.h: Moved most of the remaining CPU Table fields to
42        the Configuration Table. This included pretasking_hook,
43        predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace,
44        extra_mpci_receive_server_stack, stack_allocate_hook, and
45        stack_free_hook. As a side-effect of this effort some multiprocessing
46        code was made conditional and some style clean up occurred.
47
482007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
49
50        * rtems/score/cpu.h: Eliminate the clicks_per_microsecond field in the
51        MIPS CPU Table and define another mechanism for drivers to obtain
52        this information.
53
542007-08-04      Ralf Corsépius <ralf.corsepius@rtems.org>
55
56        * rtems/score/cpu.h: Use uintptr_t instead of uint32_t.
57
582007-05-09      Ralf Corsépius <ralf.corsepius@rtems.org>
59
60        * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
61
622007-04-17      Ralf Corsépius <ralf.corsepius@rtems.org>
63
64        * rtems/score/cpu.h:
65          Use Context_Control_fp* instead of void* for fp_contexts.
66          Eliminate evil casts.
67
682006-11-17      Ralf Corsépius <ralf.corsepius@rtems.org>
69
70        * rtems/score/types.h: Remove unsigned64, signed64.
71
722006-06-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
73
74        * cpu.c: Added __mips==32 to fix build problems on those targets
75        caused by the Bruce Robinson.
76
772006-06-08 Bruce Robinson <brucer@pmccorp.com>
78
79        * cpu.c: Add int64 types for __mips==3 cpus, incorporate
80           mips_interrupt_mask() into mask computations
81        * cpu_asm.S: Add int64 register save/restores for __mips==3 cpus.  Adjustment
82           of mips1 vs mips3 macros.
83        * cpu.h: Add int64 types for __mips==3 cpus.
84       
852006-03-17      Ralf Corsepius <ralf.corsepius@rtems.org>
86
87        * cpu.c (_CPU_Initialize): Add fpu initialization.
88        * rtems/score/cpu.h: Setup CPU_*_ENDIAN from GCC's__MIPS{EL|EB}__.
89        (Partial merger of submission by Bruce Robinson <brucer@pmccorp.com>).
90
912006-01-16      Joel Sherrill <joel@OARcorp.com>
92
93        * rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
94        As a side-effect, grammar and spelling errors were corrected, spacing
95        errors were address, and some variable names were improved.
96
972005-11-18      Joel Sherrill <joel@OARcorp.com>
98
99        * rtems/score/cpu.h: Eliminate use of unsigned32.
100
1012005-11-08      Ralf Corsepius <ralf.corsepius@rtems.org>
102
103        * rtems/score/types.h: Eliminate unsigned16, unsigned32.
104
1052005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
106
107        * rtems/asm.h: Remove private version of CONCAT macros.
108        Include <rtems/concat.h> instead.
109
1102005-04-26      Joel Sherrill <joel@OARcorp.com>
111
112        * rtems/asm.h: Eliminate warnings.
113
1142005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
115
116        * Makefile.am: Split out preinstallation rules.
117        * preinstall.am: New (Split out from Makefile.am).
118
1192005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
120
121        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
122        Header guards cleanup.
123
1242005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
125
126        PR 754/rtems
127        * rtems/asm.h: New (relocated from .).
128        * asm.h: Remove (moved to rtems/asm.h).
129        * Makefile.am: Reflect changes above.
130
1312005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
132
133        PR rtems/752
134        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
135        New header guards.
136        * idtcpu.h, iregdef.h: Remove.
137        * Makefile.am: Reflect changes above.
138
1392004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
140
141        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
142        New header guards.
143
1442005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
145
146        * rtems/score/types.h: Remove signed8, signed16, signed32,
147        unsigned8, unsigned16, unsigned32.
148
1492005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
150
151        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
152
1532005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
154
155        * rtems/score/types.h: #include <rtems/stdint.h>.
156
1572005-01-07      Joel Sherrill <joel@OARcorp.com>
158
159        * rtems/score/cpu.h: Remove warnings.
160
1612005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
162
163        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
164
1652005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
166
167        PR 739
168        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
169        when compiling cpu_asm.S.  Problem was a #define sneaked in in
170        version 1.11, no ill effects would have only affected R4000
171        builds.
172
1732005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
174
175        PR 737
176        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
177        slot when compiling cpu_asm.S
178
1792005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
180
181        * Makefile.am: Remove build-variant support.
182
1832004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
184
185        PR 730
186        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
187        for rtems-4.7.
188
1892004-04-09      Joel Sherrill <joel@OARcorp.com>
190
191        PR 605/bsps
192        * cpu.c: Do not use C++ style comments.
193
1942004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
195        PR 601
196        * cpu_asm.S: Added __mips==32 support for R4000 processors running
197        32 bit code.  Fixed #define problems that caused fpu code to
198        always be included even when no fpu is present.
199
2002004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
201
202        PR 598/bsps
203        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
204        status/control register on context switches. Missing this register
205        was causing intermittent floating point errors.
206
2072003-09-04      Joel Sherrill <joel@OARcorp.com>
208
209        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
210        rtems/score/types.h: URL for license changed.
211
2122003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
213
214        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
215
2162003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
217
218        * configure.ac: Remove AC_CONFIG_AUX_DIR.
219
2202002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
221
222        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
223        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
224
2252002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
226
227        * configure.ac: Fix package name.
228
2292002-11-04      Joel Sherrill <joel@OARcorp.com>
230
231        * idtcpu.h: Removed warning.
232
2332002-11-01      Joel Sherrill <joel@OARcorp.com>
234
235        * idtcpu.h: Removed warnings.
236
2372002-10-28      Joel Sherrill <joel@OARcorp.com>
238
239        * idtcpu.h: Removed warning by turning extra token at the end of
240        an endif into a comment.
241
2422002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
243
244        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
245
2462002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
247
248        * .cvsignore: Reformat.
249        Add autom4te*cache.
250        Remove autom4te.cache.
251
2522002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
253
254        * cpu_asm.S: Clarified some comments, removed code that forced
255        SR_IEP on when returning from an interrupt.
256
2572002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
258
259        * configure.ac: Add RTEMS_PROG_CCAS
260
2612002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
262
263        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
264        Add AC_PROG_RANLIB.
265
2662002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
267        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
268        deadlock caused by interrupt arriving while dispatching.
269       
2702002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
271
272        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
273        Use ../../../aclocal.
274
2752001-04-03      Joel Sherrill <joel@OARcorp.com>
276
277        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
278        * rtems/score/mipstypes.h: Removed.
279        * rtems/score/types.h: New file via CVS magic.
280        * Makefile.am, rtems/score/cpu.h: Account for name change.
281
2822002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
283
284        * configure.ac:
285        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
286        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
287        * Makefile.am: Remove AUTOMAKE_OPTIONS.
288
2892002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
290
291        * cpu_asm.S: Now compiles on 4600 and 4650.
292
2932002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
294
295        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
296        * rtems/score/cpu.h: Fixed register numbering in comments and made
297        interrupt enable/disable more robust.
298       
2992002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
300        * cpu_asm.S: Added support for the debug exception vector, cleaned
301        up the exception processing & exception return stuff.  Re-added
302        EPC in the task context structure so the gdb stub will know where
303        a thread is executing.  Should've left it there in the first place...
304        * idtcpu.h: Added support for the debug exception vector.
305        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
306        stack frame in an interrupt so context switch code can get the
307        userspace EPC when scheduling.
308        * rtems/score/cpu.h: Re-added EPC to the task context.
309
3102002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
311
312        * cpu_asm.S: Fixed exception return address, modified FP context
313        switch so FPU is properly enabled and also doesn't screw up the
314        exception FP handling.
315        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
316        returning from exceptions.
317        * iregdef.h: Added R_TAR to the stack frame so the target address
318        can be saved on a per-exception basis.  The new entry is past the
319        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
320        stuff.
321        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
322        to obtain FPU defines without syntax errors generated by the C
323        defintions.
324        * cpu.c: Improved interrupt level saves & restores.
325       
3262002-02-08      Joel Sherrill <joel@OARcorp.com>
327
328        * iregdef.h, rtems/score/cpu.h: Reordered register in the
329        exception stack frame to better match gdb's expectations.
330
3312001-02-05      Joel Sherrill <joel@OARcorp.com>
332
333        * cpu_asm.S: Enhanced to save/restore more registers on
334        exceptions.
335        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
336        register individually and document when it is saved.
337        * idtcpu.h: Added constants for the coprocessor 1 registers
338        revision and status.
339
3402001-02-05      Joel Sherrill <joel@OARcorp.com>
341
342        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
343
3442001-02-04      Joel Sherrill <joel@OARcorp.com>
345
346        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
347        in the previous patch that has now been confirmed.
348
3492001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
350
351        * cpu.c: Enhancements and fixes for modifying the SR when changing
352        the interrupt level.
353        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
354        managed on a per-task basis, improved handling of interrupt levels,
355        and made deferred FP contexts work on the MIPS.
356        * rtems/score/cpu.h: Modified to support above changes.
357
3582002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
359
360        * rtems/Makefile.am: Removed.
361        * rtems/score/Makefile.am: Removed.
362        * configure.ac: Reflect changes above.
363        * Makefile.am: Reflect changes above.
364
3652002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
366
367        * asm.h: Remove #include <rtems/score/targopts.h>.
368        Add #include <rtems/score/cpuopts.h>.
369        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
370
371
3722001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
373
374        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
375
3762001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
377
378        * Makefile.am: Add multilib support.
379
3802001-11-28      Joel Sherrill <joel@OARcorp.com>,
381
382        This was tracked as PR91.
383        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
384        is used to specify if the port uses the standard macro for this (FALSE).
385        A TRUE setting indicates the port provides its own implementation.
386
3872001-10-12      Joel Sherrill <joel@OARcorp.com>
388
389        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
390        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
391        Wayne Bullaughey <wayne@wmi.com>.
392
3932001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
394
395        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
396        * configure.in: Remove.
397        * configure.ac: New file, generated from configure.in by autoupdate.
398
3992001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
400
401        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
402        * Makefile.am: Use 'PREINSTALL_FILES ='.
403
4042001-07-03      Joel Sherrill <joel@OARcorp.com>
405
406        * cpu.c: Fixed typo.
407
4082000-05-24      Joel Sherrill <joel@OARcorp.com>
409
410        * rtems/score/mips.h: Added constants for MIPS exception numbers.
411        All exceptions should be given low numbers and thus can be installed
412        and processed in a uniform manner.  Variances between various MIPS
413        ISA levels were not accounted for.
414
4152001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
416
417        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
418        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
419
4202001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
421
422        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
423        the context initialization to account for floating point tasks. 
424        * rtems/score/mips.h: Added the routines mips_set_cause(),
425        mips_get_fcr31(), and mips_set_fcr31().
426        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
427
4282001-05-07      Joel Sherrill <joel@OARcorp.com>
429
430        * cpu_asm.S: Merged patches from Gregory Menke
431        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
432        stack usage and include nops in the delay slots.
433
4342001-04-20      Joel Sherrill <joel@OARcorp.com>
435
436        * cpu_asm.S: Added code to save and restore SR and EPC to
437        properly support nested interrupts.  Note that the ISR
438        (not RTEMS) enables interrupts allowing the nesting to occur.
439
4402001-03-14      Joel Sherrill <joel@OARcorp.com>
441
442        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
443        Removed unused variable _CPU_Thread_dispatch_pointer
444        and cleaned numerous comments.
445       
4462001-03-13      Joel Sherrill <joel@OARcorp.com>
447
448        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
449        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
450        Also reimplemented some assembly routines in C further reducing
451        the amount of assembly and increasing maintainability.
452
4532001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
454
455        * Makefile.am, rtems/score/Makefile.am:
456        Apply include_*HEADERS instead of H_FILES.
457
4582001-01-12      Joel Sherrill <joel@OARcorp.com>
459
460        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
461        register constraints from "general" to "register".
462
4632001-01-09      Joel Sherrill <joel@OARcorp.com>
464
465        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
466        to make it easier to conditionalize the code for various ISA levels.
467
4682001-01-08      Joel Sherrill <joel@OARcorp.com>
469
470        * idtcpu.h: Commented out definition of "wait".  It was stupid to
471        use such a common word as a macro.
472        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
473        * rtems/score/mips.h: Added include of <idtcpu.h>.
474        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
475
4762001-01-03      Joel Sherrill <joel@OARcorp.com>
477
478        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
479        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
480
4812000-12-19      Joel Sherrill <joel@OARcorp.com>
482
483        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
484        Previous code resulting in the interrupted immediately returning
485        to the caller of the routine it was inside.
486
4872000-12-19      Joel Sherrill <joel@OARcorp.com>
488
489        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
490        because it has not been allocated yet.
491
4922000-12-13      Joel Sherrill <joel@OARcorp.com>
493
494        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
495        * cpu_asm.S: Removed assembly language to vector ISR handler
496        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
497        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
498        longer a constant -- get the real value from libcpu.
499
5002000-12-13      Joel Sherrill <joel@OARcorp.com>
501
502        * cpu_asm.h: Removed.
503        * Makefile.am: Remove cpu_asm.h.
504        * rtems/score/mips64orion.h: Renamed mips.h.
505        * rtems/score/mips.h: New file, formerly mips64orion.h.
506        Header rewritten.
507        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
508        mips_disable_in_interrupt_mask): New macros.
509        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
510        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
511        few defines that were in <cpu_asm.h>.
512        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
513        MIPS ISA 3 is still in assembly for now.
514        (_CPU_Thread_Idle_body): Rewrote in C.
515        * cpu_asm.S: Rewrote file header.
516        (FRAME,ENDFRAME) now in asm.h.
517        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
518        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
519        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
520        leaves other bits in SR alone on task switch.
521        (mips_enable_interrupts,mips_disable_interrupts,
522        mips_enable_global_interrupts,mips_disable_global_interrupts,
523        disable_int, enable_int): Removed.
524        (mips_get_sr): Rewritten as C macro.
525        (_CPU_Thread_Idle_body): Rewritten in C.
526        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
527        placed in libcpu.
528        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
529        to libcpu/mips/shared/interrupts.
530        (general): Cleaned up comment blocks and #if 0 areas.
531        * idtcpu.h: Made ifdef report an error.
532        * iregdef.h: Removed warning.
533        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
534        number defined by libcpu.
535        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
536        to access SR.
537        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
538        (_CPU_Context_Initialize): Honor ISR level in task initialization.
539        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
540
5412000-12-06      Joel Sherrill <joel@OARcorp.com>
542
543        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
544        context should be 32 not 64 bits.
545
5462000-11-30      Joel Sherrill <joel@OARcorp.com>
547
548        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
549        correct name of _CPU_Context_switch_restore.  Added dummy
550        version of exc_utlb_code() so applications would link.
551
5522000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
553
554        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
555
5562000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
557
558        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
559
5602000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
561
562        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
563        Switch to GNU canonicalization.
564
5652000-10-24      Alan Cudmore <alanc@linuxstart.com> and
566        Joel Sherrill <joel@OARcorp.com>
567
568        * This is a major reworking of the mips64orion port to use
569        gcc predefines as much as possible and a big push to multilib
570        the mips port.  The mips64orion port was copied/renamed to mips
571        to be more like other GNU tools.  Alan did most of the technical
572        work of determining how to map old macro names used by the mips64orion
573        port to standard compiler macro definitions.  Joel did the merge
574        with CVS magic to keep individual file history and did the BSP
575        modifications. Details follow:
576        * Makefile.am: idtmon.h in mips64orion port not present.
577        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
578        * cpu.c: Comments added.
579        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
580        First attempt at exception/interrupt processing for ISA level 1
581        and minus any use of IDT/MON added.
582        * idtcpu.h: Conditionals changed to use gcc predefines.
583        * iregdef.h: Ditto.
584        * cpu_asm.h: No real change.  Merger required commit.
585        * rtems/Makefile.am: Ditto.
586        * rtems/score/Makefile.am: Ditto.
587        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
588        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
589        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
590
5912000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
592
593        * Makefile.am: Include compile.am.
594
5952000-08-10      Joel Sherrill <joel@OARcorp.com>
596
597        * ChangeLog: New file.
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