source: rtems/cpukit/score/cpu/mips/ChangeLog @ 5ff0481

4.104.114.84.95
Last change on this file since 5ff0481 was 5ff0481, checked in by Ralf Corsepius <ralf.corsepius@…>, on Jan 28, 2005 at 3:53:32 PM

2004-01-28 Ralf Corsepius <ralf.corsepiu@…>

  • asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h: New header guards.
  • Property mode set to 100644
File size: 15.7 KB
Line 
12004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
2
3        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
4        New header guards.
5
62005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
7
8        * rtems/score/types.h: Remove signed8, signed16, signed32,
9        unsigned8, unsigned16, unsigned32.
10
112005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
12
13        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
14
152005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
16
17        * rtems/score/types.h: #include <rtems/stdint.h>.
18
192005-01-07      Joel Sherrill <joel@OARcorp.com>
20
21        * rtems/score/cpu.h: Remove warnings.
22
232005-01-07      Ralf Corsepius <ralf.corsepius@freenet.de>
24
25        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
26
272005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
28
29        PR 739
30        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
31        when compiling cpu_asm.S.  Problem was a #define sneaked in in
32        version 1.11, no ill effects would have only affected R4000
33        builds.
34
352005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
36
37        PR 737
38        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
39        slot when compiling cpu_asm.S
40
412005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
42
43        * Makefile.am: Remove build-variant support.
44
452004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
46
47        PR 730
48        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
49        for rtems-4.7.
50
512004-04-09      Joel Sherrill <joel@OARcorp.com>
52
53        PR 605/bsps
54        * cpu.c: Do not use C++ style comments.
55
562004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
57        PR 601
58        * cpu_asm.S: Added __mips==32 support for R4000 processors running
59        32 bit code.  Fixed #define problems that caused fpu code to
60        always be included even when no fpu is present.
61
622004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
63
64        PR 598/bsps
65        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
66        status/control register on context switches. Missing this register
67        was causing intermittent floating point errors.
68
692003-09-04      Joel Sherrill <joel@OARcorp.com>
70
71        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
72        rtems/score/types.h: URL for license changed.
73
742003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
75
76        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
77
782003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
79
80        * configure.ac: Remove AC_CONFIG_AUX_DIR.
81
822002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
83
84        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
85        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
86
872002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
88
89        * configure.ac: Fix package name.
90
912002-11-04      Joel Sherrill <joel@OARcorp.com>
92
93        * idtcpu.h: Removed warning.
94
952002-11-01      Joel Sherrill <joel@OARcorp.com>
96
97        * idtcpu.h: Removed warnings.
98
992002-10-28      Joel Sherrill <joel@OARcorp.com>
100
101        * idtcpu.h: Removed warning by turning extra token at the end of
102        an endif into a comment.
103
1042002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
105
106        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
107
1082002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
109
110        * .cvsignore: Reformat.
111        Add autom4te*cache.
112        Remove autom4te.cache.
113
1142002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
115
116        * cpu_asm.S: Clarified some comments, removed code that forced
117        SR_IEP on when returning from an interrupt.
118
1192002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
120
121        * configure.ac: Add RTEMS_PROG_CCAS
122
1232002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
124
125        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
126        Add AC_PROG_RANLIB.
127
1282002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
129        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
130        deadlock caused by interrupt arriving while dispatching.
131       
1322002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
133
134        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
135        Use ../../../aclocal.
136
1372001-04-03      Joel Sherrill <joel@OARcorp.com>
138
139        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
140        * rtems/score/mipstypes.h: Removed.
141        * rtems/score/types.h: New file via CVS magic.
142        * Makefile.am, rtems/score/cpu.h: Account for name change.
143
1442002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
145
146        * configure.ac:
147        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
148        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
149        * Makefile.am: Remove AUTOMAKE_OPTIONS.
150
1512002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
152
153        * cpu_asm.S: Now compiles on 4600 and 4650.
154
1552002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
156
157        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
158        * rtems/score/cpu.h: Fixed register numbering in comments and made
159        interrupt enable/disable more robust.
160       
1612002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
162        * cpu_asm.S: Added support for the debug exception vector, cleaned
163        up the exception processing & exception return stuff.  Re-added
164        EPC in the task context structure so the gdb stub will know where
165        a thread is executing.  Should've left it there in the first place...
166        * idtcpu.h: Added support for the debug exception vector.
167        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
168        stack frame in an interrupt so context switch code can get the
169        userspace EPC when scheduling.
170        * rtems/score/cpu.h: Re-added EPC to the task context.
171
1722002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
173
174        * cpu_asm.S: Fixed exception return address, modified FP context
175        switch so FPU is properly enabled and also doesn't screw up the
176        exception FP handling.
177        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
178        returning from exceptions.
179        * iregdef.h: Added R_TAR to the stack frame so the target address
180        can be saved on a per-exception basis.  The new entry is past the
181        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
182        stuff.
183        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
184        to obtain FPU defines without syntax errors generated by the C
185        defintions.
186        * cpu.c: Improved interrupt level saves & restores.
187       
1882002-02-08      Joel Sherrill <joel@OARcorp.com>
189
190        * iregdef.h, rtems/score/cpu.h: Reordered register in the
191        exception stack frame to better match gdb's expectations.
192
1932001-02-05      Joel Sherrill <joel@OARcorp.com>
194
195        * cpu_asm.S: Enhanced to save/restore more registers on
196        exceptions.
197        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
198        register individually and document when it is saved.
199        * idtcpu.h: Added constants for the coprocessor 1 registers
200        revision and status.
201
2022001-02-05      Joel Sherrill <joel@OARcorp.com>
203
204        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
205
2062001-02-04      Joel Sherrill <joel@OARcorp.com>
207
208        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
209        in the previous patch that has now been confirmed.
210
2112001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
212
213        * cpu.c: Enhancements and fixes for modifying the SR when changing
214        the interrupt level.
215        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
216        managed on a per-task basis, improved handling of interrupt levels,
217        and made deferred FP contexts work on the MIPS.
218        * rtems/score/cpu.h: Modified to support above changes.
219
2202002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
221
222        * rtems/Makefile.am: Removed.
223        * rtems/score/Makefile.am: Removed.
224        * configure.ac: Reflect changes above.
225        * Makefile.am: Reflect changes above.
226
2272002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
228
229        * asm.h: Remove #include <rtems/score/targopts.h>.
230        Add #include <rtems/score/cpuopts.h>.
231        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
232
233
2342001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
235
236        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
237
2382001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
239
240        * Makefile.am: Add multilib support.
241
2422001-11-28      Joel Sherrill <joel@OARcorp.com>,
243
244        This was tracked as PR91.
245        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
246        is used to specify if the port uses the standard macro for this (FALSE).
247        A TRUE setting indicates the port provides its own implementation.
248
2492001-10-12      Joel Sherrill <joel@OARcorp.com>
250
251        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
252        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
253        Wayne Bullaughey <wayne@wmi.com>.
254
2552001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
256
257        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
258        * configure.in: Remove.
259        * configure.ac: New file, generated from configure.in by autoupdate.
260
2612001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
262
263        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
264        * Makefile.am: Use 'PREINSTALL_FILES ='.
265
2662001-07-03      Joel Sherrill <joel@OARcorp.com>
267
268        * cpu.c: Fixed typo.
269
2702000-05-24      Joel Sherrill <joel@OARcorp.com>
271
272        * rtems/score/mips.h: Added constants for MIPS exception numbers.
273        All exceptions should be given low numbers and thus can be installed
274        and processed in a uniform manner.  Variances between various MIPS
275        ISA levels were not accounted for.
276
2772001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
278
279        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
280        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
281
2822001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
283
284        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
285        the context initialization to account for floating point tasks. 
286        * rtems/score/mips.h: Added the routines mips_set_cause(),
287        mips_get_fcr31(), and mips_set_fcr31().
288        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
289
2902001-05-07      Joel Sherrill <joel@OARcorp.com>
291
292        * cpu_asm.S: Merged patches from Gregory Menke
293        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
294        stack usage and include nops in the delay slots.
295
2962001-04-20      Joel Sherrill <joel@OARcorp.com>
297
298        * cpu_asm.S: Added code to save and restore SR and EPC to
299        properly support nested interrupts.  Note that the ISR
300        (not RTEMS) enables interrupts allowing the nesting to occur.
301
3022001-03-14      Joel Sherrill <joel@OARcorp.com>
303
304        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
305        Removed unused variable _CPU_Thread_dispatch_pointer
306        and cleaned numerous comments.
307       
3082001-03-13      Joel Sherrill <joel@OARcorp.com>
309
310        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
311        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
312        Also reimplemented some assembly routines in C further reducing
313        the amount of assembly and increasing maintainability.
314
3152001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
316
317        * Makefile.am, rtems/score/Makefile.am:
318        Apply include_*HEADERS instead of H_FILES.
319
3202001-01-12      Joel Sherrill <joel@OARcorp.com>
321
322        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
323        register constraints from "general" to "register".
324
3252001-01-09      Joel Sherrill <joel@OARcorp.com>
326
327        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
328        to make it easier to conditionalize the code for various ISA levels.
329
3302001-01-08      Joel Sherrill <joel@OARcorp.com>
331
332        * idtcpu.h: Commented out definition of "wait".  It was stupid to
333        use such a common word as a macro.
334        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
335        * rtems/score/mips.h: Added include of <idtcpu.h>.
336        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
337
3382001-01-03      Joel Sherrill <joel@OARcorp.com>
339
340        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
341        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
342
3432000-12-19      Joel Sherrill <joel@OARcorp.com>
344
345        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
346        Previous code resulting in the interrupted immediately returning
347        to the caller of the routine it was inside.
348
3492000-12-19      Joel Sherrill <joel@OARcorp.com>
350
351        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
352        because it has not been allocated yet.
353
3542000-12-13      Joel Sherrill <joel@OARcorp.com>
355
356        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
357        * cpu_asm.S: Removed assembly language to vector ISR handler
358        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
359        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
360        longer a constant -- get the real value from libcpu.
361
3622000-12-13      Joel Sherrill <joel@OARcorp.com>
363
364        * cpu_asm.h: Removed.
365        * Makefile.am: Remove cpu_asm.h.
366        * rtems/score/mips64orion.h: Renamed mips.h.
367        * rtems/score/mips.h: New file, formerly mips64orion.h.
368        Header rewritten.
369        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
370        mips_disable_in_interrupt_mask): New macros.
371        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
372        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
373        few defines that were in <cpu_asm.h>.
374        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
375        MIPS ISA 3 is still in assembly for now.
376        (_CPU_Thread_Idle_body): Rewrote in C.
377        * cpu_asm.S: Rewrote file header.
378        (FRAME,ENDFRAME) now in asm.h.
379        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
380        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
381        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
382        leaves other bits in SR alone on task switch.
383        (mips_enable_interrupts,mips_disable_interrupts,
384        mips_enable_global_interrupts,mips_disable_global_interrupts,
385        disable_int, enable_int): Removed.
386        (mips_get_sr): Rewritten as C macro.
387        (_CPU_Thread_Idle_body): Rewritten in C.
388        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
389        placed in libcpu.
390        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
391        to libcpu/mips/shared/interrupts.
392        (general): Cleaned up comment blocks and #if 0 areas.
393        * idtcpu.h: Made ifdef report an error.
394        * iregdef.h: Removed warning.
395        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
396        number defined by libcpu.
397        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
398        to access SR.
399        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
400        (_CPU_Context_Initialize): Honor ISR level in task initialization.
401        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
402
4032000-12-06      Joel Sherrill <joel@OARcorp.com>
404
405        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
406        context should be 32 not 64 bits.
407
4082000-11-30      Joel Sherrill <joel@OARcorp.com>
409
410        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
411        correct name of _CPU_Context_switch_restore.  Added dummy
412        version of exc_utlb_code() so applications would link.
413
4142000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
415
416        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
417
4182000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
419
420        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
421
4222000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
423
424        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
425        Switch to GNU canonicalization.
426
4272000-10-24      Alan Cudmore <alanc@linuxstart.com> and
428        Joel Sherrill <joel@OARcorp.com>
429
430        * This is a major reworking of the mips64orion port to use
431        gcc predefines as much as possible and a big push to multilib
432        the mips port.  The mips64orion port was copied/renamed to mips
433        to be more like other GNU tools.  Alan did most of the technical
434        work of determining how to map old macro names used by the mips64orion
435        port to standard compiler macro definitions.  Joel did the merge
436        with CVS magic to keep individual file history and did the BSP
437        modifications. Details follow:
438        * Makefile.am: idtmon.h in mips64orion port not present.
439        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
440        * cpu.c: Comments added.
441        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
442        First attempt at exception/interrupt processing for ISA level 1
443        and minus any use of IDT/MON added.
444        * idtcpu.h: Conditionals changed to use gcc predefines.
445        * iregdef.h: Ditto.
446        * cpu_asm.h: No real change.  Merger required commit.
447        * rtems/Makefile.am: Ditto.
448        * rtems/score/Makefile.am: Ditto.
449        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
450        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
451        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
452
4532000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
454
455        * Makefile.am: Include compile.am.
456
4572000-08-10      Joel Sherrill <joel@OARcorp.com>
458
459        * ChangeLog: New file.
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