source: rtems/cpukit/score/cpu/mips/ChangeLog @ 5c8b6b6

4.104.114.84.9
Last change on this file since 5c8b6b6 was 5c8b6b6, checked in by Ralf Corsepius <ralf.corsepius@…>, on Oct 25, 2002 at 5:46:06 AM

2002-10-25 Ralf Corsepius <corsepiu@…>

  • configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
  • Property mode set to 100644
File size: 12.9 KB
Line 
12002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
2
3        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
4
52002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
6
7        * .cvsignore: Reformat.
8        Add autom4te*cache.
9        Remove autom4te.cache.
10
112002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
12
13        * cpu_asm.S: Clarified some comments, removed code that forced
14        SR_IEP on when returning from an interrupt.
15
162002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
17
18        * configure.ac: Add RTEMS_PROG_CCAS
19
202002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
21
22        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
23        Add AC_PROG_RANLIB.
24
252002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
26        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
27        deadlock caused by interrupt arriving while dispatching.
28       
292002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
30
31        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
32        Use ../../../aclocal.
33
342001-04-03      Joel Sherrill <joel@OARcorp.com>
35
36        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
37        * rtems/score/mipstypes.h: Removed.
38        * rtems/score/types.h: New file via CVS magic.
39        * Makefile.am, rtems/score/cpu.h: Account for name change.
40
412002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
42
43        * configure.ac:
44        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
45        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
46        * Makefile.am: Remove AUTOMAKE_OPTIONS.
47
482002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
49
50        * cpu_asm.S: Now compiles on 4600 and 4650.
51
522002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
53
54        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
55        * rtems/score/cpu.h: Fixed register numbering in comments and made
56        interrupt enable/disable more robust.
57       
582002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
59        * cpu_asm.S: Added support for the debug exception vector, cleaned
60        up the exception processing & exception return stuff.  Re-added
61        EPC in the task context structure so the gdb stub will know where
62        a thread is executing.  Should've left it there in the first place...
63        * idtcpu.h: Added support for the debug exception vector.
64        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
65        stack frame in an interrupt so context switch code can get the
66        userspace EPC when scheduling.
67        * rtems/score/cpu.h: Re-added EPC to the task context.
68
692002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
70
71        * cpu_asm.S: Fixed exception return address, modified FP context
72        switch so FPU is properly enabled and also doesn't screw up the
73        exception FP handling.
74        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
75        returning from exceptions.
76        * iregdef.h: Added R_TAR to the stack frame so the target address
77        can be saved on a per-exception basis.  The new entry is past the
78        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
79        stuff.
80        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
81        to obtain FPU defines without syntax errors generated by the C
82        defintions.
83        * cpu.c: Improved interrupt level saves & restores.
84       
852002-02-08      Joel Sherrill <joel@OARcorp.com>
86
87        * iregdef.h, rtems/score/cpu.h: Reordered register in the
88        exception stack frame to better match gdb's expectations.
89
902001-02-05      Joel Sherrill <joel@OARcorp.com>
91
92        * cpu_asm.S: Enhanced to save/restore more registers on
93        exceptions.
94        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
95        register individually and document when it is saved.
96        * idtcpu.h: Added constants for the coprocessor 1 registers
97        revision and status.
98
992001-02-05      Joel Sherrill <joel@OARcorp.com>
100
101        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
102
1032001-02-04      Joel Sherrill <joel@OARcorp.com>
104
105        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
106        in the previous patch that has now been confirmed.
107
1082001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
109
110        * cpu.c: Enhancements and fixes for modifying the SR when changing
111        the interrupt level.
112        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
113        managed on a per-task basis, improved handling of interrupt levels,
114        and made deferred FP contexts work on the MIPS.
115        * rtems/score/cpu.h: Modified to support above changes.
116
1172002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
118
119        * rtems/Makefile.am: Removed.
120        * rtems/score/Makefile.am: Removed.
121        * configure.ac: Reflect changes above.
122        * Makefile.am: Reflect changes above.
123
1242002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
125
126        * asm.h: Remove #include <rtems/score/targopts.h>.
127        Add #include <rtems/score/cpuopts.h>.
128        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
129
130
1312001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
132
133        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
134
1352001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
136
137        * Makefile.am: Add multilib support.
138
1392001-11-28      Joel Sherrill <joel@OARcorp.com>,
140
141        This was tracked as PR91.
142        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
143        is used to specify if the port uses the standard macro for this (FALSE).
144        A TRUE setting indicates the port provides its own implementation.
145
1462001-10-12      Joel Sherrill <joel@OARcorp.com>
147
148        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
149        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
150        Wayne Bullaughey <wayne@wmi.com>.
151
1522001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
153
154        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
155        * configure.in: Remove.
156        * configure.ac: New file, generated from configure.in by autoupdate.
157
1582001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
159
160        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
161        * Makefile.am: Use 'PREINSTALL_FILES ='.
162
1632001-07-03      Joel Sherrill <joel@OARcorp.com>
164
165        * cpu.c: Fixed typo.
166
1672000-05-24      Joel Sherrill <joel@OARcorp.com>
168
169        * rtems/score/mips.h: Added constants for MIPS exception numbers.
170        All exceptions should be given low numbers and thus can be installed
171        and processed in a uniform manner.  Variances between various MIPS
172        ISA levels were not accounted for.
173
1742001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
175
176        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
177        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
178
1792001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
180
181        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
182        the context initialization to account for floating point tasks. 
183        * rtems/score/mips.h: Added the routines mips_set_cause(),
184        mips_get_fcr31(), and mips_set_fcr31().
185        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
186
1872001-05-07      Joel Sherrill <joel@OARcorp.com>
188
189        * cpu_asm.S: Merged patches from Gregory Menke
190        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
191        stack usage and include nops in the delay slots.
192
1932001-04-20      Joel Sherrill <joel@OARcorp.com>
194
195        * cpu_asm.S: Added code to save and restore SR and EPC to
196        properly support nested interrupts.  Note that the ISR
197        (not RTEMS) enables interrupts allowing the nesting to occur.
198
1992001-03-14      Joel Sherrill <joel@OARcorp.com>
200
201        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
202        Removed unused variable _CPU_Thread_dispatch_pointer
203        and cleaned numerous comments.
204       
2052001-03-13      Joel Sherrill <joel@OARcorp.com>
206
207        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
208        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
209        Also reimplemented some assembly routines in C further reducing
210        the amount of assembly and increasing maintainability.
211
2122001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
213
214        * Makefile.am, rtems/score/Makefile.am:
215        Apply include_*HEADERS instead of H_FILES.
216
2172001-01-12      Joel Sherrill <joel@OARcorp.com>
218
219        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
220        register constraints from "general" to "register".
221
2222001-01-09      Joel Sherrill <joel@OARcorp.com>
223
224        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
225        to make it easier to conditionalize the code for various ISA levels.
226
2272001-01-08      Joel Sherrill <joel@OARcorp.com>
228
229        * idtcpu.h: Commented out definition of "wait".  It was stupid to
230        use such a common word as a macro.
231        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
232        * rtems/score/mips.h: Added include of <idtcpu.h>.
233        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
234
2352001-01-03      Joel Sherrill <joel@OARcorp.com>
236
237        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
238        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
239
2402000-12-19      Joel Sherrill <joel@OARcorp.com>
241
242        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
243        Previous code resulting in the interrupted immediately returning
244        to the caller of the routine it was inside.
245
2462000-12-19      Joel Sherrill <joel@OARcorp.com>
247
248        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
249        because it has not been allocated yet.
250
2512000-12-13      Joel Sherrill <joel@OARcorp.com>
252
253        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
254        * cpu_asm.S: Removed assembly language to vector ISR handler
255        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
256        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
257        longer a constant -- get the real value from libcpu.
258
2592000-12-13      Joel Sherrill <joel@OARcorp.com>
260
261        * cpu_asm.h: Removed.
262        * Makefile.am: Remove cpu_asm.h.
263        * rtems/score/mips64orion.h: Renamed mips.h.
264        * rtems/score/mips.h: New file, formerly mips64orion.h.
265        Header rewritten.
266        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
267        mips_disable_in_interrupt_mask): New macros.
268        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
269        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
270        few defines that were in <cpu_asm.h>.
271        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
272        MIPS ISA 3 is still in assembly for now.
273        (_CPU_Thread_Idle_body): Rewrote in C.
274        * cpu_asm.S: Rewrote file header.
275        (FRAME,ENDFRAME) now in asm.h.
276        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
277        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
278        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
279        leaves other bits in SR alone on task switch.
280        (mips_enable_interrupts,mips_disable_interrupts,
281        mips_enable_global_interrupts,mips_disable_global_interrupts,
282        disable_int, enable_int): Removed.
283        (mips_get_sr): Rewritten as C macro.
284        (_CPU_Thread_Idle_body): Rewritten in C.
285        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
286        placed in libcpu.
287        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
288        to libcpu/mips/shared/interrupts.
289        (general): Cleaned up comment blocks and #if 0 areas.
290        * idtcpu.h: Made ifdef report an error.
291        * iregdef.h: Removed warning.
292        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
293        number defined by libcpu.
294        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
295        to access SR.
296        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
297        (_CPU_Context_Initialize): Honor ISR level in task initialization.
298        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
299
3002000-12-06      Joel Sherrill <joel@OARcorp.com>
301
302        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
303        context should be 32 not 64 bits.
304
3052000-11-30      Joel Sherrill <joel@OARcorp.com>
306
307        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
308        correct name of _CPU_Context_switch_restore.  Added dummy
309        version of exc_utlb_code() so applications would link.
310
3112000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
312
313        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
314
3152000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
316
317        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
318
3192000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
320
321        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
322        Switch to GNU canonicalization.
323
3242000-10-24      Alan Cudmore <alanc@linuxstart.com> and
325        Joel Sherrill <joel@OARcorp.com>
326
327        * This is a major reworking of the mips64orion port to use
328        gcc predefines as much as possible and a big push to multilib
329        the mips port.  The mips64orion port was copied/renamed to mips
330        to be more like other GNU tools.  Alan did most of the technical
331        work of determining how to map old macro names used by the mips64orion
332        port to standard compiler macro definitions.  Joel did the merge
333        with CVS magic to keep individual file history and did the BSP
334        modifications. Details follow:
335        * Makefile.am: idtmon.h in mips64orion port not present.
336        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
337        * cpu.c: Comments added.
338        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
339        First attempt at exception/interrupt processing for ISA level 1
340        and minus any use of IDT/MON added.
341        * idtcpu.h: Conditionals changed to use gcc predefines.
342        * iregdef.h: Ditto.
343        * cpu_asm.h: No real change.  Merger required commit.
344        * rtems/Makefile.am: Ditto.
345        * rtems/score/Makefile.am: Ditto.
346        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
347        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
348        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
349
3502000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
351
352        * Makefile.am: Include compile.am.
353
3542000-08-10      Joel Sherrill <joel@OARcorp.com>
355
356        * ChangeLog: New file.
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