source: rtems/cpukit/score/cpu/mips/ChangeLog @ 53021d4

4.104.114.84.95
Last change on this file since 53021d4 was 53021d4, checked in by Ralf Corsepius <ralf.corsepius@…>, on 12/11/02 at 17:08:38

2002-12-11 Ralf Corsepius <corsepiu@…>

  • configure.ac: Require autoconf-2.57 + automake-1.7.2.
  • Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
  • Property mode set to 100644
File size: 13.5 KB
Line 
12002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
2
3        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
4        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
5
62002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
7
8        * configure.ac: Fix package name.
9
102002-11-04      Joel Sherrill <joel@OARcorp.com>
11
12        * idtcpu.h: Removed warning.
13
142002-11-01      Joel Sherrill <joel@OARcorp.com>
15
16        * idtcpu.h: Removed warnings.
17
182002-10-28      Joel Sherrill <joel@OARcorp.com>
19
20        * idtcpu.h: Removed warning by turning extra token at the end of
21        an endif into a comment.
22
232002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
24
25        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
26
272002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
28
29        * .cvsignore: Reformat.
30        Add autom4te*cache.
31        Remove autom4te.cache.
32
332002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
34
35        * cpu_asm.S: Clarified some comments, removed code that forced
36        SR_IEP on when returning from an interrupt.
37
382002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
39
40        * configure.ac: Add RTEMS_PROG_CCAS
41
422002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
43
44        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
45        Add AC_PROG_RANLIB.
46
472002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
48        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
49        deadlock caused by interrupt arriving while dispatching.
50       
512002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
52
53        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
54        Use ../../../aclocal.
55
562001-04-03      Joel Sherrill <joel@OARcorp.com>
57
58        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
59        * rtems/score/mipstypes.h: Removed.
60        * rtems/score/types.h: New file via CVS magic.
61        * Makefile.am, rtems/score/cpu.h: Account for name change.
62
632002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
64
65        * configure.ac:
66        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
67        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
68        * Makefile.am: Remove AUTOMAKE_OPTIONS.
69
702002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
71
72        * cpu_asm.S: Now compiles on 4600 and 4650.
73
742002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
75
76        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
77        * rtems/score/cpu.h: Fixed register numbering in comments and made
78        interrupt enable/disable more robust.
79       
802002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
81        * cpu_asm.S: Added support for the debug exception vector, cleaned
82        up the exception processing & exception return stuff.  Re-added
83        EPC in the task context structure so the gdb stub will know where
84        a thread is executing.  Should've left it there in the first place...
85        * idtcpu.h: Added support for the debug exception vector.
86        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
87        stack frame in an interrupt so context switch code can get the
88        userspace EPC when scheduling.
89        * rtems/score/cpu.h: Re-added EPC to the task context.
90
912002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
92
93        * cpu_asm.S: Fixed exception return address, modified FP context
94        switch so FPU is properly enabled and also doesn't screw up the
95        exception FP handling.
96        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
97        returning from exceptions.
98        * iregdef.h: Added R_TAR to the stack frame so the target address
99        can be saved on a per-exception basis.  The new entry is past the
100        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
101        stuff.
102        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
103        to obtain FPU defines without syntax errors generated by the C
104        defintions.
105        * cpu.c: Improved interrupt level saves & restores.
106       
1072002-02-08      Joel Sherrill <joel@OARcorp.com>
108
109        * iregdef.h, rtems/score/cpu.h: Reordered register in the
110        exception stack frame to better match gdb's expectations.
111
1122001-02-05      Joel Sherrill <joel@OARcorp.com>
113
114        * cpu_asm.S: Enhanced to save/restore more registers on
115        exceptions.
116        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
117        register individually and document when it is saved.
118        * idtcpu.h: Added constants for the coprocessor 1 registers
119        revision and status.
120
1212001-02-05      Joel Sherrill <joel@OARcorp.com>
122
123        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
124
1252001-02-04      Joel Sherrill <joel@OARcorp.com>
126
127        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
128        in the previous patch that has now been confirmed.
129
1302001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
131
132        * cpu.c: Enhancements and fixes for modifying the SR when changing
133        the interrupt level.
134        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
135        managed on a per-task basis, improved handling of interrupt levels,
136        and made deferred FP contexts work on the MIPS.
137        * rtems/score/cpu.h: Modified to support above changes.
138
1392002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
140
141        * rtems/Makefile.am: Removed.
142        * rtems/score/Makefile.am: Removed.
143        * configure.ac: Reflect changes above.
144        * Makefile.am: Reflect changes above.
145
1462002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
147
148        * asm.h: Remove #include <rtems/score/targopts.h>.
149        Add #include <rtems/score/cpuopts.h>.
150        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
151
152
1532001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
154
155        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
156
1572001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
158
159        * Makefile.am: Add multilib support.
160
1612001-11-28      Joel Sherrill <joel@OARcorp.com>,
162
163        This was tracked as PR91.
164        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
165        is used to specify if the port uses the standard macro for this (FALSE).
166        A TRUE setting indicates the port provides its own implementation.
167
1682001-10-12      Joel Sherrill <joel@OARcorp.com>
169
170        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
171        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
172        Wayne Bullaughey <wayne@wmi.com>.
173
1742001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
175
176        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
177        * configure.in: Remove.
178        * configure.ac: New file, generated from configure.in by autoupdate.
179
1802001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
181
182        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
183        * Makefile.am: Use 'PREINSTALL_FILES ='.
184
1852001-07-03      Joel Sherrill <joel@OARcorp.com>
186
187        * cpu.c: Fixed typo.
188
1892000-05-24      Joel Sherrill <joel@OARcorp.com>
190
191        * rtems/score/mips.h: Added constants for MIPS exception numbers.
192        All exceptions should be given low numbers and thus can be installed
193        and processed in a uniform manner.  Variances between various MIPS
194        ISA levels were not accounted for.
195
1962001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
197
198        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
199        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
200
2012001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
202
203        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
204        the context initialization to account for floating point tasks. 
205        * rtems/score/mips.h: Added the routines mips_set_cause(),
206        mips_get_fcr31(), and mips_set_fcr31().
207        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
208
2092001-05-07      Joel Sherrill <joel@OARcorp.com>
210
211        * cpu_asm.S: Merged patches from Gregory Menke
212        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
213        stack usage and include nops in the delay slots.
214
2152001-04-20      Joel Sherrill <joel@OARcorp.com>
216
217        * cpu_asm.S: Added code to save and restore SR and EPC to
218        properly support nested interrupts.  Note that the ISR
219        (not RTEMS) enables interrupts allowing the nesting to occur.
220
2212001-03-14      Joel Sherrill <joel@OARcorp.com>
222
223        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
224        Removed unused variable _CPU_Thread_dispatch_pointer
225        and cleaned numerous comments.
226       
2272001-03-13      Joel Sherrill <joel@OARcorp.com>
228
229        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
230        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
231        Also reimplemented some assembly routines in C further reducing
232        the amount of assembly and increasing maintainability.
233
2342001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
235
236        * Makefile.am, rtems/score/Makefile.am:
237        Apply include_*HEADERS instead of H_FILES.
238
2392001-01-12      Joel Sherrill <joel@OARcorp.com>
240
241        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
242        register constraints from "general" to "register".
243
2442001-01-09      Joel Sherrill <joel@OARcorp.com>
245
246        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
247        to make it easier to conditionalize the code for various ISA levels.
248
2492001-01-08      Joel Sherrill <joel@OARcorp.com>
250
251        * idtcpu.h: Commented out definition of "wait".  It was stupid to
252        use such a common word as a macro.
253        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
254        * rtems/score/mips.h: Added include of <idtcpu.h>.
255        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
256
2572001-01-03      Joel Sherrill <joel@OARcorp.com>
258
259        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
260        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
261
2622000-12-19      Joel Sherrill <joel@OARcorp.com>
263
264        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
265        Previous code resulting in the interrupted immediately returning
266        to the caller of the routine it was inside.
267
2682000-12-19      Joel Sherrill <joel@OARcorp.com>
269
270        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
271        because it has not been allocated yet.
272
2732000-12-13      Joel Sherrill <joel@OARcorp.com>
274
275        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
276        * cpu_asm.S: Removed assembly language to vector ISR handler
277        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
278        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
279        longer a constant -- get the real value from libcpu.
280
2812000-12-13      Joel Sherrill <joel@OARcorp.com>
282
283        * cpu_asm.h: Removed.
284        * Makefile.am: Remove cpu_asm.h.
285        * rtems/score/mips64orion.h: Renamed mips.h.
286        * rtems/score/mips.h: New file, formerly mips64orion.h.
287        Header rewritten.
288        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
289        mips_disable_in_interrupt_mask): New macros.
290        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
291        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
292        few defines that were in <cpu_asm.h>.
293        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
294        MIPS ISA 3 is still in assembly for now.
295        (_CPU_Thread_Idle_body): Rewrote in C.
296        * cpu_asm.S: Rewrote file header.
297        (FRAME,ENDFRAME) now in asm.h.
298        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
299        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
300        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
301        leaves other bits in SR alone on task switch.
302        (mips_enable_interrupts,mips_disable_interrupts,
303        mips_enable_global_interrupts,mips_disable_global_interrupts,
304        disable_int, enable_int): Removed.
305        (mips_get_sr): Rewritten as C macro.
306        (_CPU_Thread_Idle_body): Rewritten in C.
307        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
308        placed in libcpu.
309        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
310        to libcpu/mips/shared/interrupts.
311        (general): Cleaned up comment blocks and #if 0 areas.
312        * idtcpu.h: Made ifdef report an error.
313        * iregdef.h: Removed warning.
314        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
315        number defined by libcpu.
316        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
317        to access SR.
318        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
319        (_CPU_Context_Initialize): Honor ISR level in task initialization.
320        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
321
3222000-12-06      Joel Sherrill <joel@OARcorp.com>
323
324        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
325        context should be 32 not 64 bits.
326
3272000-11-30      Joel Sherrill <joel@OARcorp.com>
328
329        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
330        correct name of _CPU_Context_switch_restore.  Added dummy
331        version of exc_utlb_code() so applications would link.
332
3332000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
334
335        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
336
3372000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
338
339        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
340
3412000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
342
343        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
344        Switch to GNU canonicalization.
345
3462000-10-24      Alan Cudmore <alanc@linuxstart.com> and
347        Joel Sherrill <joel@OARcorp.com>
348
349        * This is a major reworking of the mips64orion port to use
350        gcc predefines as much as possible and a big push to multilib
351        the mips port.  The mips64orion port was copied/renamed to mips
352        to be more like other GNU tools.  Alan did most of the technical
353        work of determining how to map old macro names used by the mips64orion
354        port to standard compiler macro definitions.  Joel did the merge
355        with CVS magic to keep individual file history and did the BSP
356        modifications. Details follow:
357        * Makefile.am: idtmon.h in mips64orion port not present.
358        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
359        * cpu.c: Comments added.
360        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
361        First attempt at exception/interrupt processing for ISA level 1
362        and minus any use of IDT/MON added.
363        * idtcpu.h: Conditionals changed to use gcc predefines.
364        * iregdef.h: Ditto.
365        * cpu_asm.h: No real change.  Merger required commit.
366        * rtems/Makefile.am: Ditto.
367        * rtems/score/Makefile.am: Ditto.
368        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
369        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
370        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
371
3722000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
373
374        * Makefile.am: Include compile.am.
375
3762000-08-10      Joel Sherrill <joel@OARcorp.com>
377
378        * ChangeLog: New file.
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