source: rtems/cpukit/score/cpu/mips/ChangeLog @ 5236cf04

4.104.114.84.95
Last change on this file since 5236cf04 was 5236cf04, checked in by Ralf Corsepius <ralf.corsepius@…>, on 02/01/05 at 15:15:45

2005-02-01 Ralf Corsepius <ralf.corsepius@…>

PR rtems/752

  • rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .). New header guards.
  • idtcpu.h, iregdef.h: Remove.
  • Makefile.am: Reflect changes above.
  • Property mode set to 100644
File size: 16.0 KB
Line 
12005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
2
3        PR rtems/752
4        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
5        New header guards.
6        * idtcpu.h, iregdef.h: Remove.
7        * Makefile.am: Reflect changes above.
8
92004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
10
11        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
12        New header guards.
13
142005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
15
16        * rtems/score/types.h: Remove signed8, signed16, signed32,
17        unsigned8, unsigned16, unsigned32.
18
192005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
20
21        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
22
232005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
24
25        * rtems/score/types.h: #include <rtems/stdint.h>.
26
272005-01-07      Joel Sherrill <joel@OARcorp.com>
28
29        * rtems/score/cpu.h: Remove warnings.
30
312005-01-07      Ralf Corsepius <ralf.corsepius@freenet.de>
32
33        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
34
352005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
36
37        PR 739
38        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
39        when compiling cpu_asm.S.  Problem was a #define sneaked in in
40        version 1.11, no ill effects would have only affected R4000
41        builds.
42
432005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
44
45        PR 737
46        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
47        slot when compiling cpu_asm.S
48
492005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
50
51        * Makefile.am: Remove build-variant support.
52
532004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
54
55        PR 730
56        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
57        for rtems-4.7.
58
592004-04-09      Joel Sherrill <joel@OARcorp.com>
60
61        PR 605/bsps
62        * cpu.c: Do not use C++ style comments.
63
642004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
65        PR 601
66        * cpu_asm.S: Added __mips==32 support for R4000 processors running
67        32 bit code.  Fixed #define problems that caused fpu code to
68        always be included even when no fpu is present.
69
702004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
71
72        PR 598/bsps
73        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
74        status/control register on context switches. Missing this register
75        was causing intermittent floating point errors.
76
772003-09-04      Joel Sherrill <joel@OARcorp.com>
78
79        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
80        rtems/score/types.h: URL for license changed.
81
822003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
83
84        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
85
862003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
87
88        * configure.ac: Remove AC_CONFIG_AUX_DIR.
89
902002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
91
92        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
93        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
94
952002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
96
97        * configure.ac: Fix package name.
98
992002-11-04      Joel Sherrill <joel@OARcorp.com>
100
101        * idtcpu.h: Removed warning.
102
1032002-11-01      Joel Sherrill <joel@OARcorp.com>
104
105        * idtcpu.h: Removed warnings.
106
1072002-10-28      Joel Sherrill <joel@OARcorp.com>
108
109        * idtcpu.h: Removed warning by turning extra token at the end of
110        an endif into a comment.
111
1122002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
113
114        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
115
1162002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
117
118        * .cvsignore: Reformat.
119        Add autom4te*cache.
120        Remove autom4te.cache.
121
1222002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
123
124        * cpu_asm.S: Clarified some comments, removed code that forced
125        SR_IEP on when returning from an interrupt.
126
1272002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
128
129        * configure.ac: Add RTEMS_PROG_CCAS
130
1312002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
132
133        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
134        Add AC_PROG_RANLIB.
135
1362002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
137        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
138        deadlock caused by interrupt arriving while dispatching.
139       
1402002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
141
142        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
143        Use ../../../aclocal.
144
1452001-04-03      Joel Sherrill <joel@OARcorp.com>
146
147        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
148        * rtems/score/mipstypes.h: Removed.
149        * rtems/score/types.h: New file via CVS magic.
150        * Makefile.am, rtems/score/cpu.h: Account for name change.
151
1522002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
153
154        * configure.ac:
155        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
156        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
157        * Makefile.am: Remove AUTOMAKE_OPTIONS.
158
1592002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
160
161        * cpu_asm.S: Now compiles on 4600 and 4650.
162
1632002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
164
165        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
166        * rtems/score/cpu.h: Fixed register numbering in comments and made
167        interrupt enable/disable more robust.
168       
1692002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
170        * cpu_asm.S: Added support for the debug exception vector, cleaned
171        up the exception processing & exception return stuff.  Re-added
172        EPC in the task context structure so the gdb stub will know where
173        a thread is executing.  Should've left it there in the first place...
174        * idtcpu.h: Added support for the debug exception vector.
175        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
176        stack frame in an interrupt so context switch code can get the
177        userspace EPC when scheduling.
178        * rtems/score/cpu.h: Re-added EPC to the task context.
179
1802002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
181
182        * cpu_asm.S: Fixed exception return address, modified FP context
183        switch so FPU is properly enabled and also doesn't screw up the
184        exception FP handling.
185        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
186        returning from exceptions.
187        * iregdef.h: Added R_TAR to the stack frame so the target address
188        can be saved on a per-exception basis.  The new entry is past the
189        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
190        stuff.
191        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
192        to obtain FPU defines without syntax errors generated by the C
193        defintions.
194        * cpu.c: Improved interrupt level saves & restores.
195       
1962002-02-08      Joel Sherrill <joel@OARcorp.com>
197
198        * iregdef.h, rtems/score/cpu.h: Reordered register in the
199        exception stack frame to better match gdb's expectations.
200
2012001-02-05      Joel Sherrill <joel@OARcorp.com>
202
203        * cpu_asm.S: Enhanced to save/restore more registers on
204        exceptions.
205        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
206        register individually and document when it is saved.
207        * idtcpu.h: Added constants for the coprocessor 1 registers
208        revision and status.
209
2102001-02-05      Joel Sherrill <joel@OARcorp.com>
211
212        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
213
2142001-02-04      Joel Sherrill <joel@OARcorp.com>
215
216        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
217        in the previous patch that has now been confirmed.
218
2192001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
220
221        * cpu.c: Enhancements and fixes for modifying the SR when changing
222        the interrupt level.
223        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
224        managed on a per-task basis, improved handling of interrupt levels,
225        and made deferred FP contexts work on the MIPS.
226        * rtems/score/cpu.h: Modified to support above changes.
227
2282002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
229
230        * rtems/Makefile.am: Removed.
231        * rtems/score/Makefile.am: Removed.
232        * configure.ac: Reflect changes above.
233        * Makefile.am: Reflect changes above.
234
2352002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
236
237        * asm.h: Remove #include <rtems/score/targopts.h>.
238        Add #include <rtems/score/cpuopts.h>.
239        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
240
241
2422001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
243
244        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
245
2462001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
247
248        * Makefile.am: Add multilib support.
249
2502001-11-28      Joel Sherrill <joel@OARcorp.com>,
251
252        This was tracked as PR91.
253        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
254        is used to specify if the port uses the standard macro for this (FALSE).
255        A TRUE setting indicates the port provides its own implementation.
256
2572001-10-12      Joel Sherrill <joel@OARcorp.com>
258
259        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
260        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
261        Wayne Bullaughey <wayne@wmi.com>.
262
2632001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
264
265        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
266        * configure.in: Remove.
267        * configure.ac: New file, generated from configure.in by autoupdate.
268
2692001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
270
271        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
272        * Makefile.am: Use 'PREINSTALL_FILES ='.
273
2742001-07-03      Joel Sherrill <joel@OARcorp.com>
275
276        * cpu.c: Fixed typo.
277
2782000-05-24      Joel Sherrill <joel@OARcorp.com>
279
280        * rtems/score/mips.h: Added constants for MIPS exception numbers.
281        All exceptions should be given low numbers and thus can be installed
282        and processed in a uniform manner.  Variances between various MIPS
283        ISA levels were not accounted for.
284
2852001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
286
287        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
288        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
289
2902001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
291
292        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
293        the context initialization to account for floating point tasks. 
294        * rtems/score/mips.h: Added the routines mips_set_cause(),
295        mips_get_fcr31(), and mips_set_fcr31().
296        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
297
2982001-05-07      Joel Sherrill <joel@OARcorp.com>
299
300        * cpu_asm.S: Merged patches from Gregory Menke
301        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
302        stack usage and include nops in the delay slots.
303
3042001-04-20      Joel Sherrill <joel@OARcorp.com>
305
306        * cpu_asm.S: Added code to save and restore SR and EPC to
307        properly support nested interrupts.  Note that the ISR
308        (not RTEMS) enables interrupts allowing the nesting to occur.
309
3102001-03-14      Joel Sherrill <joel@OARcorp.com>
311
312        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
313        Removed unused variable _CPU_Thread_dispatch_pointer
314        and cleaned numerous comments.
315       
3162001-03-13      Joel Sherrill <joel@OARcorp.com>
317
318        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
319        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
320        Also reimplemented some assembly routines in C further reducing
321        the amount of assembly and increasing maintainability.
322
3232001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
324
325        * Makefile.am, rtems/score/Makefile.am:
326        Apply include_*HEADERS instead of H_FILES.
327
3282001-01-12      Joel Sherrill <joel@OARcorp.com>
329
330        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
331        register constraints from "general" to "register".
332
3332001-01-09      Joel Sherrill <joel@OARcorp.com>
334
335        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
336        to make it easier to conditionalize the code for various ISA levels.
337
3382001-01-08      Joel Sherrill <joel@OARcorp.com>
339
340        * idtcpu.h: Commented out definition of "wait".  It was stupid to
341        use such a common word as a macro.
342        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
343        * rtems/score/mips.h: Added include of <idtcpu.h>.
344        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
345
3462001-01-03      Joel Sherrill <joel@OARcorp.com>
347
348        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
349        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
350
3512000-12-19      Joel Sherrill <joel@OARcorp.com>
352
353        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
354        Previous code resulting in the interrupted immediately returning
355        to the caller of the routine it was inside.
356
3572000-12-19      Joel Sherrill <joel@OARcorp.com>
358
359        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
360        because it has not been allocated yet.
361
3622000-12-13      Joel Sherrill <joel@OARcorp.com>
363
364        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
365        * cpu_asm.S: Removed assembly language to vector ISR handler
366        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
367        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
368        longer a constant -- get the real value from libcpu.
369
3702000-12-13      Joel Sherrill <joel@OARcorp.com>
371
372        * cpu_asm.h: Removed.
373        * Makefile.am: Remove cpu_asm.h.
374        * rtems/score/mips64orion.h: Renamed mips.h.
375        * rtems/score/mips.h: New file, formerly mips64orion.h.
376        Header rewritten.
377        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
378        mips_disable_in_interrupt_mask): New macros.
379        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
380        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
381        few defines that were in <cpu_asm.h>.
382        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
383        MIPS ISA 3 is still in assembly for now.
384        (_CPU_Thread_Idle_body): Rewrote in C.
385        * cpu_asm.S: Rewrote file header.
386        (FRAME,ENDFRAME) now in asm.h.
387        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
388        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
389        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
390        leaves other bits in SR alone on task switch.
391        (mips_enable_interrupts,mips_disable_interrupts,
392        mips_enable_global_interrupts,mips_disable_global_interrupts,
393        disable_int, enable_int): Removed.
394        (mips_get_sr): Rewritten as C macro.
395        (_CPU_Thread_Idle_body): Rewritten in C.
396        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
397        placed in libcpu.
398        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
399        to libcpu/mips/shared/interrupts.
400        (general): Cleaned up comment blocks and #if 0 areas.
401        * idtcpu.h: Made ifdef report an error.
402        * iregdef.h: Removed warning.
403        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
404        number defined by libcpu.
405        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
406        to access SR.
407        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
408        (_CPU_Context_Initialize): Honor ISR level in task initialization.
409        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
410
4112000-12-06      Joel Sherrill <joel@OARcorp.com>
412
413        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
414        context should be 32 not 64 bits.
415
4162000-11-30      Joel Sherrill <joel@OARcorp.com>
417
418        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
419        correct name of _CPU_Context_switch_restore.  Added dummy
420        version of exc_utlb_code() so applications would link.
421
4222000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
423
424        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
425
4262000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
427
428        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
429
4302000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
431
432        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
433        Switch to GNU canonicalization.
434
4352000-10-24      Alan Cudmore <alanc@linuxstart.com> and
436        Joel Sherrill <joel@OARcorp.com>
437
438        * This is a major reworking of the mips64orion port to use
439        gcc predefines as much as possible and a big push to multilib
440        the mips port.  The mips64orion port was copied/renamed to mips
441        to be more like other GNU tools.  Alan did most of the technical
442        work of determining how to map old macro names used by the mips64orion
443        port to standard compiler macro definitions.  Joel did the merge
444        with CVS magic to keep individual file history and did the BSP
445        modifications. Details follow:
446        * Makefile.am: idtmon.h in mips64orion port not present.
447        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
448        * cpu.c: Comments added.
449        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
450        First attempt at exception/interrupt processing for ISA level 1
451        and minus any use of IDT/MON added.
452        * idtcpu.h: Conditionals changed to use gcc predefines.
453        * iregdef.h: Ditto.
454        * cpu_asm.h: No real change.  Merger required commit.
455        * rtems/Makefile.am: Ditto.
456        * rtems/score/Makefile.am: Ditto.
457        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
458        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
459        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
460
4612000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
462
463        * Makefile.am: Include compile.am.
464
4652000-08-10      Joel Sherrill <joel@OARcorp.com>
466
467        * ChangeLog: New file.
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