source: rtems/cpukit/score/cpu/mips/ChangeLog @ 4e97166

4.104.114.84.95
Last change on this file since 4e97166 was 3883f7e, checked in by Joel Sherrill <joel.sherrill@…>, on 11/18/05 at 21:11:32

2005-11-18 Joel Sherrill <joel@…>

  • rtems/score/cpu.h: Eliminate use of unsigned32.
  • Property mode set to 100644
File size: 16.9 KB
Line 
12005-11-18      Joel Sherrill <joel@OARcorp.com>
2
3        * rtems/score/cpu.h: Eliminate use of unsigned32.
4
52005-11-08      Ralf Corsepius <ralf.corsepius@rtems.org>
6
7        * rtems/score/types.h: Eliminate unsigned16, unsigned32.
8
92005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
10
11        * rtems/asm.h: Remove private version of CONCAT macros.
12        Include <rtems/concat.h> instead.
13
142005-04-26      Joel Sherrill <joel@OARcorp.com>
15
16        * rtems/asm.h: Eliminate warnings.
17
182005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
19
20        * Makefile.am: Split out preinstallation rules.
21        * preinstall.am: New (Split out from Makefile.am).
22
232005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
24
25        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
26        Header guards cleanup.
27
282005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
29
30        PR 754/rtems
31        * rtems/asm.h: New (relocated from .).
32        * asm.h: Remove (moved to rtems/asm.h).
33        * Makefile.am: Reflect changes above.
34
352005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
36
37        PR rtems/752
38        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
39        New header guards.
40        * idtcpu.h, iregdef.h: Remove.
41        * Makefile.am: Reflect changes above.
42
432004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
44
45        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
46        New header guards.
47
482005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
49
50        * rtems/score/types.h: Remove signed8, signed16, signed32,
51        unsigned8, unsigned16, unsigned32.
52
532005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
54
55        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
56
572005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
58
59        * rtems/score/types.h: #include <rtems/stdint.h>.
60
612005-01-07      Joel Sherrill <joel@OARcorp.com>
62
63        * rtems/score/cpu.h: Remove warnings.
64
652005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
66
67        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
68
692005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
70
71        PR 739
72        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
73        when compiling cpu_asm.S.  Problem was a #define sneaked in in
74        version 1.11, no ill effects would have only affected R4000
75        builds.
76
772005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
78
79        PR 737
80        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
81        slot when compiling cpu_asm.S
82
832005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
84
85        * Makefile.am: Remove build-variant support.
86
872004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
88
89        PR 730
90        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
91        for rtems-4.7.
92
932004-04-09      Joel Sherrill <joel@OARcorp.com>
94
95        PR 605/bsps
96        * cpu.c: Do not use C++ style comments.
97
982004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
99        PR 601
100        * cpu_asm.S: Added __mips==32 support for R4000 processors running
101        32 bit code.  Fixed #define problems that caused fpu code to
102        always be included even when no fpu is present.
103
1042004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
105
106        PR 598/bsps
107        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
108        status/control register on context switches. Missing this register
109        was causing intermittent floating point errors.
110
1112003-09-04      Joel Sherrill <joel@OARcorp.com>
112
113        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
114        rtems/score/types.h: URL for license changed.
115
1162003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
117
118        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
119
1202003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
121
122        * configure.ac: Remove AC_CONFIG_AUX_DIR.
123
1242002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
125
126        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
127        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
128
1292002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
130
131        * configure.ac: Fix package name.
132
1332002-11-04      Joel Sherrill <joel@OARcorp.com>
134
135        * idtcpu.h: Removed warning.
136
1372002-11-01      Joel Sherrill <joel@OARcorp.com>
138
139        * idtcpu.h: Removed warnings.
140
1412002-10-28      Joel Sherrill <joel@OARcorp.com>
142
143        * idtcpu.h: Removed warning by turning extra token at the end of
144        an endif into a comment.
145
1462002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
147
148        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
149
1502002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
151
152        * .cvsignore: Reformat.
153        Add autom4te*cache.
154        Remove autom4te.cache.
155
1562002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
157
158        * cpu_asm.S: Clarified some comments, removed code that forced
159        SR_IEP on when returning from an interrupt.
160
1612002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
162
163        * configure.ac: Add RTEMS_PROG_CCAS
164
1652002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
166
167        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
168        Add AC_PROG_RANLIB.
169
1702002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
171        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
172        deadlock caused by interrupt arriving while dispatching.
173       
1742002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
175
176        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
177        Use ../../../aclocal.
178
1792001-04-03      Joel Sherrill <joel@OARcorp.com>
180
181        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
182        * rtems/score/mipstypes.h: Removed.
183        * rtems/score/types.h: New file via CVS magic.
184        * Makefile.am, rtems/score/cpu.h: Account for name change.
185
1862002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
187
188        * configure.ac:
189        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
190        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
191        * Makefile.am: Remove AUTOMAKE_OPTIONS.
192
1932002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
194
195        * cpu_asm.S: Now compiles on 4600 and 4650.
196
1972002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
198
199        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
200        * rtems/score/cpu.h: Fixed register numbering in comments and made
201        interrupt enable/disable more robust.
202       
2032002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
204        * cpu_asm.S: Added support for the debug exception vector, cleaned
205        up the exception processing & exception return stuff.  Re-added
206        EPC in the task context structure so the gdb stub will know where
207        a thread is executing.  Should've left it there in the first place...
208        * idtcpu.h: Added support for the debug exception vector.
209        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
210        stack frame in an interrupt so context switch code can get the
211        userspace EPC when scheduling.
212        * rtems/score/cpu.h: Re-added EPC to the task context.
213
2142002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
215
216        * cpu_asm.S: Fixed exception return address, modified FP context
217        switch so FPU is properly enabled and also doesn't screw up the
218        exception FP handling.
219        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
220        returning from exceptions.
221        * iregdef.h: Added R_TAR to the stack frame so the target address
222        can be saved on a per-exception basis.  The new entry is past the
223        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
224        stuff.
225        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
226        to obtain FPU defines without syntax errors generated by the C
227        defintions.
228        * cpu.c: Improved interrupt level saves & restores.
229       
2302002-02-08      Joel Sherrill <joel@OARcorp.com>
231
232        * iregdef.h, rtems/score/cpu.h: Reordered register in the
233        exception stack frame to better match gdb's expectations.
234
2352001-02-05      Joel Sherrill <joel@OARcorp.com>
236
237        * cpu_asm.S: Enhanced to save/restore more registers on
238        exceptions.
239        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
240        register individually and document when it is saved.
241        * idtcpu.h: Added constants for the coprocessor 1 registers
242        revision and status.
243
2442001-02-05      Joel Sherrill <joel@OARcorp.com>
245
246        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
247
2482001-02-04      Joel Sherrill <joel@OARcorp.com>
249
250        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
251        in the previous patch that has now been confirmed.
252
2532001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
254
255        * cpu.c: Enhancements and fixes for modifying the SR when changing
256        the interrupt level.
257        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
258        managed on a per-task basis, improved handling of interrupt levels,
259        and made deferred FP contexts work on the MIPS.
260        * rtems/score/cpu.h: Modified to support above changes.
261
2622002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
263
264        * rtems/Makefile.am: Removed.
265        * rtems/score/Makefile.am: Removed.
266        * configure.ac: Reflect changes above.
267        * Makefile.am: Reflect changes above.
268
2692002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
270
271        * asm.h: Remove #include <rtems/score/targopts.h>.
272        Add #include <rtems/score/cpuopts.h>.
273        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
274
275
2762001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
277
278        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
279
2802001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
281
282        * Makefile.am: Add multilib support.
283
2842001-11-28      Joel Sherrill <joel@OARcorp.com>,
285
286        This was tracked as PR91.
287        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
288        is used to specify if the port uses the standard macro for this (FALSE).
289        A TRUE setting indicates the port provides its own implementation.
290
2912001-10-12      Joel Sherrill <joel@OARcorp.com>
292
293        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
294        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
295        Wayne Bullaughey <wayne@wmi.com>.
296
2972001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
298
299        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
300        * configure.in: Remove.
301        * configure.ac: New file, generated from configure.in by autoupdate.
302
3032001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
304
305        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
306        * Makefile.am: Use 'PREINSTALL_FILES ='.
307
3082001-07-03      Joel Sherrill <joel@OARcorp.com>
309
310        * cpu.c: Fixed typo.
311
3122000-05-24      Joel Sherrill <joel@OARcorp.com>
313
314        * rtems/score/mips.h: Added constants for MIPS exception numbers.
315        All exceptions should be given low numbers and thus can be installed
316        and processed in a uniform manner.  Variances between various MIPS
317        ISA levels were not accounted for.
318
3192001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
320
321        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
322        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
323
3242001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
325
326        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
327        the context initialization to account for floating point tasks. 
328        * rtems/score/mips.h: Added the routines mips_set_cause(),
329        mips_get_fcr31(), and mips_set_fcr31().
330        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
331
3322001-05-07      Joel Sherrill <joel@OARcorp.com>
333
334        * cpu_asm.S: Merged patches from Gregory Menke
335        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
336        stack usage and include nops in the delay slots.
337
3382001-04-20      Joel Sherrill <joel@OARcorp.com>
339
340        * cpu_asm.S: Added code to save and restore SR and EPC to
341        properly support nested interrupts.  Note that the ISR
342        (not RTEMS) enables interrupts allowing the nesting to occur.
343
3442001-03-14      Joel Sherrill <joel@OARcorp.com>
345
346        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
347        Removed unused variable _CPU_Thread_dispatch_pointer
348        and cleaned numerous comments.
349       
3502001-03-13      Joel Sherrill <joel@OARcorp.com>
351
352        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
353        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
354        Also reimplemented some assembly routines in C further reducing
355        the amount of assembly and increasing maintainability.
356
3572001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
358
359        * Makefile.am, rtems/score/Makefile.am:
360        Apply include_*HEADERS instead of H_FILES.
361
3622001-01-12      Joel Sherrill <joel@OARcorp.com>
363
364        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
365        register constraints from "general" to "register".
366
3672001-01-09      Joel Sherrill <joel@OARcorp.com>
368
369        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
370        to make it easier to conditionalize the code for various ISA levels.
371
3722001-01-08      Joel Sherrill <joel@OARcorp.com>
373
374        * idtcpu.h: Commented out definition of "wait".  It was stupid to
375        use such a common word as a macro.
376        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
377        * rtems/score/mips.h: Added include of <idtcpu.h>.
378        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
379
3802001-01-03      Joel Sherrill <joel@OARcorp.com>
381
382        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
383        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
384
3852000-12-19      Joel Sherrill <joel@OARcorp.com>
386
387        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
388        Previous code resulting in the interrupted immediately returning
389        to the caller of the routine it was inside.
390
3912000-12-19      Joel Sherrill <joel@OARcorp.com>
392
393        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
394        because it has not been allocated yet.
395
3962000-12-13      Joel Sherrill <joel@OARcorp.com>
397
398        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
399        * cpu_asm.S: Removed assembly language to vector ISR handler
400        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
401        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
402        longer a constant -- get the real value from libcpu.
403
4042000-12-13      Joel Sherrill <joel@OARcorp.com>
405
406        * cpu_asm.h: Removed.
407        * Makefile.am: Remove cpu_asm.h.
408        * rtems/score/mips64orion.h: Renamed mips.h.
409        * rtems/score/mips.h: New file, formerly mips64orion.h.
410        Header rewritten.
411        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
412        mips_disable_in_interrupt_mask): New macros.
413        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
414        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
415        few defines that were in <cpu_asm.h>.
416        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
417        MIPS ISA 3 is still in assembly for now.
418        (_CPU_Thread_Idle_body): Rewrote in C.
419        * cpu_asm.S: Rewrote file header.
420        (FRAME,ENDFRAME) now in asm.h.
421        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
422        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
423        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
424        leaves other bits in SR alone on task switch.
425        (mips_enable_interrupts,mips_disable_interrupts,
426        mips_enable_global_interrupts,mips_disable_global_interrupts,
427        disable_int, enable_int): Removed.
428        (mips_get_sr): Rewritten as C macro.
429        (_CPU_Thread_Idle_body): Rewritten in C.
430        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
431        placed in libcpu.
432        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
433        to libcpu/mips/shared/interrupts.
434        (general): Cleaned up comment blocks and #if 0 areas.
435        * idtcpu.h: Made ifdef report an error.
436        * iregdef.h: Removed warning.
437        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
438        number defined by libcpu.
439        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
440        to access SR.
441        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
442        (_CPU_Context_Initialize): Honor ISR level in task initialization.
443        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
444
4452000-12-06      Joel Sherrill <joel@OARcorp.com>
446
447        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
448        context should be 32 not 64 bits.
449
4502000-11-30      Joel Sherrill <joel@OARcorp.com>
451
452        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
453        correct name of _CPU_Context_switch_restore.  Added dummy
454        version of exc_utlb_code() so applications would link.
455
4562000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
457
458        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
459
4602000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
461
462        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
463
4642000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
465
466        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
467        Switch to GNU canonicalization.
468
4692000-10-24      Alan Cudmore <alanc@linuxstart.com> and
470        Joel Sherrill <joel@OARcorp.com>
471
472        * This is a major reworking of the mips64orion port to use
473        gcc predefines as much as possible and a big push to multilib
474        the mips port.  The mips64orion port was copied/renamed to mips
475        to be more like other GNU tools.  Alan did most of the technical
476        work of determining how to map old macro names used by the mips64orion
477        port to standard compiler macro definitions.  Joel did the merge
478        with CVS magic to keep individual file history and did the BSP
479        modifications. Details follow:
480        * Makefile.am: idtmon.h in mips64orion port not present.
481        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
482        * cpu.c: Comments added.
483        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
484        First attempt at exception/interrupt processing for ISA level 1
485        and minus any use of IDT/MON added.
486        * idtcpu.h: Conditionals changed to use gcc predefines.
487        * iregdef.h: Ditto.
488        * cpu_asm.h: No real change.  Merger required commit.
489        * rtems/Makefile.am: Ditto.
490        * rtems/score/Makefile.am: Ditto.
491        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
492        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
493        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
494
4952000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
496
497        * Makefile.am: Include compile.am.
498
4992000-08-10      Joel Sherrill <joel@OARcorp.com>
500
501        * ChangeLog: New file.
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