source: rtems/cpukit/score/cpu/mips/ChangeLog @ 4b89ba7

4.104.114.95
Last change on this file since 4b89ba7 was 4b89ba7, checked in by Joel Sherrill <joel.sherrill@…>, on 12/03/07 at 22:22:55

2007-12-03 Joel Sherrill <joel.sherrill@…>

  • rtems/score/cpu.h: Moved most of the remaining CPU Table fields to the Configuration Table. This included pretasking_hook, predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace, extra_mpci_receive_server_stack, stack_allocate_hook, and stack_free_hook. As a side-effect of this effort some multiprocessing code was made conditional and some style clean up occurred.
  • Property mode set to 100644
File size: 18.9 KB
Line 
12007-12-03      Joel Sherrill <joel.sherrill@OARcorp.com>
2
3        * rtems/score/cpu.h: Moved most of the remaining CPU Table fields to
4        the Configuration Table. This included pretasking_hook,
5        predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace,
6        extra_mpci_receive_server_stack, stack_allocate_hook, and
7        stack_free_hook. As a side-effect of this effort some multiprocessing
8        code was made conditional and some style clean up occurred.
9
102007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
11
12        * rtems/score/cpu.h: Eliminate the clicks_per_microsecond field in the
13        MIPS CPU Table and define another mechanism for drivers to obtain
14        this information.
15
162007-08-04      Ralf Corsépius <ralf.corsepius@rtems.org>
17
18        * rtems/score/cpu.h: Use uintptr_t instead of uint32_t.
19
202007-05-09      Ralf Corsépius <ralf.corsepius@rtems.org>
21
22        * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
23
242007-04-17      Ralf Corsépius <ralf.corsepius@rtems.org>
25
26        * rtems/score/cpu.h:
27          Use Context_Control_fp* instead of void* for fp_contexts.
28          Eliminate evil casts.
29
302006-11-17      Ralf Corsépius <ralf.corsepius@rtems.org>
31
32        * rtems/score/types.h: Remove unsigned64, signed64.
33
342006-06-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
35
36        * cpu.c: Added __mips==32 to fix build problems on those targets
37        caused by the Bruce Robinson.
38
392006-06-08 Bruce Robinson <brucer@pmccorp.com>
40
41        * cpu.c: Add int64 types for __mips==3 cpus, incorporate
42           mips_interrupt_mask() into mask computations
43        * cpu_asm.S: Add int64 register save/restores for __mips==3 cpus.  Adjustment
44           of mips1 vs mips3 macros.
45        * cpu.h: Add int64 types for __mips==3 cpus.
46       
472006-03-17      Ralf Corsepius <ralf.corsepius@rtems.org>
48
49        * cpu.c (_CPU_Initialize): Add fpu initialization.
50        * rtems/score/cpu.h: Setup CPU_*_ENDIAN from GCC's__MIPS{EL|EB}__.
51        (Partial merger of submission by Bruce Robinson <brucer@pmccorp.com>).
52
532006-01-16      Joel Sherrill <joel@OARcorp.com>
54
55        * rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
56        As a side-effect, grammar and spelling errors were corrected, spacing
57        errors were address, and some variable names were improved.
58
592005-11-18      Joel Sherrill <joel@OARcorp.com>
60
61        * rtems/score/cpu.h: Eliminate use of unsigned32.
62
632005-11-08      Ralf Corsepius <ralf.corsepius@rtems.org>
64
65        * rtems/score/types.h: Eliminate unsigned16, unsigned32.
66
672005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
68
69        * rtems/asm.h: Remove private version of CONCAT macros.
70        Include <rtems/concat.h> instead.
71
722005-04-26      Joel Sherrill <joel@OARcorp.com>
73
74        * rtems/asm.h: Eliminate warnings.
75
762005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
77
78        * Makefile.am: Split out preinstallation rules.
79        * preinstall.am: New (Split out from Makefile.am).
80
812005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
82
83        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
84        Header guards cleanup.
85
862005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
87
88        PR 754/rtems
89        * rtems/asm.h: New (relocated from .).
90        * asm.h: Remove (moved to rtems/asm.h).
91        * Makefile.am: Reflect changes above.
92
932005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
94
95        PR rtems/752
96        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
97        New header guards.
98        * idtcpu.h, iregdef.h: Remove.
99        * Makefile.am: Reflect changes above.
100
1012004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
102
103        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
104        New header guards.
105
1062005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
107
108        * rtems/score/types.h: Remove signed8, signed16, signed32,
109        unsigned8, unsigned16, unsigned32.
110
1112005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
112
113        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
114
1152005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
116
117        * rtems/score/types.h: #include <rtems/stdint.h>.
118
1192005-01-07      Joel Sherrill <joel@OARcorp.com>
120
121        * rtems/score/cpu.h: Remove warnings.
122
1232005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
124
125        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
126
1272005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
128
129        PR 739
130        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
131        when compiling cpu_asm.S.  Problem was a #define sneaked in in
132        version 1.11, no ill effects would have only affected R4000
133        builds.
134
1352005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
136
137        PR 737
138        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
139        slot when compiling cpu_asm.S
140
1412005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
142
143        * Makefile.am: Remove build-variant support.
144
1452004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
146
147        PR 730
148        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
149        for rtems-4.7.
150
1512004-04-09      Joel Sherrill <joel@OARcorp.com>
152
153        PR 605/bsps
154        * cpu.c: Do not use C++ style comments.
155
1562004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
157        PR 601
158        * cpu_asm.S: Added __mips==32 support for R4000 processors running
159        32 bit code.  Fixed #define problems that caused fpu code to
160        always be included even when no fpu is present.
161
1622004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
163
164        PR 598/bsps
165        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
166        status/control register on context switches. Missing this register
167        was causing intermittent floating point errors.
168
1692003-09-04      Joel Sherrill <joel@OARcorp.com>
170
171        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
172        rtems/score/types.h: URL for license changed.
173
1742003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
175
176        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
177
1782003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
179
180        * configure.ac: Remove AC_CONFIG_AUX_DIR.
181
1822002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
183
184        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
185        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
186
1872002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
188
189        * configure.ac: Fix package name.
190
1912002-11-04      Joel Sherrill <joel@OARcorp.com>
192
193        * idtcpu.h: Removed warning.
194
1952002-11-01      Joel Sherrill <joel@OARcorp.com>
196
197        * idtcpu.h: Removed warnings.
198
1992002-10-28      Joel Sherrill <joel@OARcorp.com>
200
201        * idtcpu.h: Removed warning by turning extra token at the end of
202        an endif into a comment.
203
2042002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
205
206        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
207
2082002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
209
210        * .cvsignore: Reformat.
211        Add autom4te*cache.
212        Remove autom4te.cache.
213
2142002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
215
216        * cpu_asm.S: Clarified some comments, removed code that forced
217        SR_IEP on when returning from an interrupt.
218
2192002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
220
221        * configure.ac: Add RTEMS_PROG_CCAS
222
2232002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
224
225        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
226        Add AC_PROG_RANLIB.
227
2282002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
229        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
230        deadlock caused by interrupt arriving while dispatching.
231       
2322002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
233
234        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
235        Use ../../../aclocal.
236
2372001-04-03      Joel Sherrill <joel@OARcorp.com>
238
239        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
240        * rtems/score/mipstypes.h: Removed.
241        * rtems/score/types.h: New file via CVS magic.
242        * Makefile.am, rtems/score/cpu.h: Account for name change.
243
2442002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
245
246        * configure.ac:
247        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
248        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
249        * Makefile.am: Remove AUTOMAKE_OPTIONS.
250
2512002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
252
253        * cpu_asm.S: Now compiles on 4600 and 4650.
254
2552002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
256
257        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
258        * rtems/score/cpu.h: Fixed register numbering in comments and made
259        interrupt enable/disable more robust.
260       
2612002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
262        * cpu_asm.S: Added support for the debug exception vector, cleaned
263        up the exception processing & exception return stuff.  Re-added
264        EPC in the task context structure so the gdb stub will know where
265        a thread is executing.  Should've left it there in the first place...
266        * idtcpu.h: Added support for the debug exception vector.
267        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
268        stack frame in an interrupt so context switch code can get the
269        userspace EPC when scheduling.
270        * rtems/score/cpu.h: Re-added EPC to the task context.
271
2722002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
273
274        * cpu_asm.S: Fixed exception return address, modified FP context
275        switch so FPU is properly enabled and also doesn't screw up the
276        exception FP handling.
277        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
278        returning from exceptions.
279        * iregdef.h: Added R_TAR to the stack frame so the target address
280        can be saved on a per-exception basis.  The new entry is past the
281        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
282        stuff.
283        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
284        to obtain FPU defines without syntax errors generated by the C
285        defintions.
286        * cpu.c: Improved interrupt level saves & restores.
287       
2882002-02-08      Joel Sherrill <joel@OARcorp.com>
289
290        * iregdef.h, rtems/score/cpu.h: Reordered register in the
291        exception stack frame to better match gdb's expectations.
292
2932001-02-05      Joel Sherrill <joel@OARcorp.com>
294
295        * cpu_asm.S: Enhanced to save/restore more registers on
296        exceptions.
297        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
298        register individually and document when it is saved.
299        * idtcpu.h: Added constants for the coprocessor 1 registers
300        revision and status.
301
3022001-02-05      Joel Sherrill <joel@OARcorp.com>
303
304        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
305
3062001-02-04      Joel Sherrill <joel@OARcorp.com>
307
308        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
309        in the previous patch that has now been confirmed.
310
3112001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
312
313        * cpu.c: Enhancements and fixes for modifying the SR when changing
314        the interrupt level.
315        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
316        managed on a per-task basis, improved handling of interrupt levels,
317        and made deferred FP contexts work on the MIPS.
318        * rtems/score/cpu.h: Modified to support above changes.
319
3202002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
321
322        * rtems/Makefile.am: Removed.
323        * rtems/score/Makefile.am: Removed.
324        * configure.ac: Reflect changes above.
325        * Makefile.am: Reflect changes above.
326
3272002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
328
329        * asm.h: Remove #include <rtems/score/targopts.h>.
330        Add #include <rtems/score/cpuopts.h>.
331        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
332
333
3342001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
335
336        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
337
3382001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
339
340        * Makefile.am: Add multilib support.
341
3422001-11-28      Joel Sherrill <joel@OARcorp.com>,
343
344        This was tracked as PR91.
345        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
346        is used to specify if the port uses the standard macro for this (FALSE).
347        A TRUE setting indicates the port provides its own implementation.
348
3492001-10-12      Joel Sherrill <joel@OARcorp.com>
350
351        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
352        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
353        Wayne Bullaughey <wayne@wmi.com>.
354
3552001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
356
357        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
358        * configure.in: Remove.
359        * configure.ac: New file, generated from configure.in by autoupdate.
360
3612001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
362
363        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
364        * Makefile.am: Use 'PREINSTALL_FILES ='.
365
3662001-07-03      Joel Sherrill <joel@OARcorp.com>
367
368        * cpu.c: Fixed typo.
369
3702000-05-24      Joel Sherrill <joel@OARcorp.com>
371
372        * rtems/score/mips.h: Added constants for MIPS exception numbers.
373        All exceptions should be given low numbers and thus can be installed
374        and processed in a uniform manner.  Variances between various MIPS
375        ISA levels were not accounted for.
376
3772001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
378
379        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
380        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
381
3822001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
383
384        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
385        the context initialization to account for floating point tasks. 
386        * rtems/score/mips.h: Added the routines mips_set_cause(),
387        mips_get_fcr31(), and mips_set_fcr31().
388        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
389
3902001-05-07      Joel Sherrill <joel@OARcorp.com>
391
392        * cpu_asm.S: Merged patches from Gregory Menke
393        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
394        stack usage and include nops in the delay slots.
395
3962001-04-20      Joel Sherrill <joel@OARcorp.com>
397
398        * cpu_asm.S: Added code to save and restore SR and EPC to
399        properly support nested interrupts.  Note that the ISR
400        (not RTEMS) enables interrupts allowing the nesting to occur.
401
4022001-03-14      Joel Sherrill <joel@OARcorp.com>
403
404        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
405        Removed unused variable _CPU_Thread_dispatch_pointer
406        and cleaned numerous comments.
407       
4082001-03-13      Joel Sherrill <joel@OARcorp.com>
409
410        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
411        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
412        Also reimplemented some assembly routines in C further reducing
413        the amount of assembly and increasing maintainability.
414
4152001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
416
417        * Makefile.am, rtems/score/Makefile.am:
418        Apply include_*HEADERS instead of H_FILES.
419
4202001-01-12      Joel Sherrill <joel@OARcorp.com>
421
422        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
423        register constraints from "general" to "register".
424
4252001-01-09      Joel Sherrill <joel@OARcorp.com>
426
427        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
428        to make it easier to conditionalize the code for various ISA levels.
429
4302001-01-08      Joel Sherrill <joel@OARcorp.com>
431
432        * idtcpu.h: Commented out definition of "wait".  It was stupid to
433        use such a common word as a macro.
434        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
435        * rtems/score/mips.h: Added include of <idtcpu.h>.
436        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
437
4382001-01-03      Joel Sherrill <joel@OARcorp.com>
439
440        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
441        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
442
4432000-12-19      Joel Sherrill <joel@OARcorp.com>
444
445        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
446        Previous code resulting in the interrupted immediately returning
447        to the caller of the routine it was inside.
448
4492000-12-19      Joel Sherrill <joel@OARcorp.com>
450
451        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
452        because it has not been allocated yet.
453
4542000-12-13      Joel Sherrill <joel@OARcorp.com>
455
456        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
457        * cpu_asm.S: Removed assembly language to vector ISR handler
458        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
459        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
460        longer a constant -- get the real value from libcpu.
461
4622000-12-13      Joel Sherrill <joel@OARcorp.com>
463
464        * cpu_asm.h: Removed.
465        * Makefile.am: Remove cpu_asm.h.
466        * rtems/score/mips64orion.h: Renamed mips.h.
467        * rtems/score/mips.h: New file, formerly mips64orion.h.
468        Header rewritten.
469        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
470        mips_disable_in_interrupt_mask): New macros.
471        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
472        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
473        few defines that were in <cpu_asm.h>.
474        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
475        MIPS ISA 3 is still in assembly for now.
476        (_CPU_Thread_Idle_body): Rewrote in C.
477        * cpu_asm.S: Rewrote file header.
478        (FRAME,ENDFRAME) now in asm.h.
479        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
480        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
481        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
482        leaves other bits in SR alone on task switch.
483        (mips_enable_interrupts,mips_disable_interrupts,
484        mips_enable_global_interrupts,mips_disable_global_interrupts,
485        disable_int, enable_int): Removed.
486        (mips_get_sr): Rewritten as C macro.
487        (_CPU_Thread_Idle_body): Rewritten in C.
488        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
489        placed in libcpu.
490        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
491        to libcpu/mips/shared/interrupts.
492        (general): Cleaned up comment blocks and #if 0 areas.
493        * idtcpu.h: Made ifdef report an error.
494        * iregdef.h: Removed warning.
495        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
496        number defined by libcpu.
497        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
498        to access SR.
499        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
500        (_CPU_Context_Initialize): Honor ISR level in task initialization.
501        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
502
5032000-12-06      Joel Sherrill <joel@OARcorp.com>
504
505        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
506        context should be 32 not 64 bits.
507
5082000-11-30      Joel Sherrill <joel@OARcorp.com>
509
510        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
511        correct name of _CPU_Context_switch_restore.  Added dummy
512        version of exc_utlb_code() so applications would link.
513
5142000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
515
516        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
517
5182000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
519
520        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
521
5222000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
523
524        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
525        Switch to GNU canonicalization.
526
5272000-10-24      Alan Cudmore <alanc@linuxstart.com> and
528        Joel Sherrill <joel@OARcorp.com>
529
530        * This is a major reworking of the mips64orion port to use
531        gcc predefines as much as possible and a big push to multilib
532        the mips port.  The mips64orion port was copied/renamed to mips
533        to be more like other GNU tools.  Alan did most of the technical
534        work of determining how to map old macro names used by the mips64orion
535        port to standard compiler macro definitions.  Joel did the merge
536        with CVS magic to keep individual file history and did the BSP
537        modifications. Details follow:
538        * Makefile.am: idtmon.h in mips64orion port not present.
539        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
540        * cpu.c: Comments added.
541        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
542        First attempt at exception/interrupt processing for ISA level 1
543        and minus any use of IDT/MON added.
544        * idtcpu.h: Conditionals changed to use gcc predefines.
545        * iregdef.h: Ditto.
546        * cpu_asm.h: No real change.  Merger required commit.
547        * rtems/Makefile.am: Ditto.
548        * rtems/score/Makefile.am: Ditto.
549        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
550        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
551        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
552
5532000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
554
555        * Makefile.am: Include compile.am.
556
5572000-08-10      Joel Sherrill <joel@OARcorp.com>
558
559        * ChangeLog: New file.
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