source: rtems/cpukit/score/cpu/mips/ChangeLog @ 3c87adba

4.104.114.95
Last change on this file since 3c87adba was 3c87adba, checked in by Joel Sherrill <joel.sherrill@…>, on 07/31/08 at 14:55:56

2008-07-31 Joel Sherrill <joel.sherrill@…>

  • cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads.
  • Property mode set to 100644
File size: 20.0 KB
Line 
12008-07-31      Joel Sherrill <joel.sherrill@OARcorp.com>
2
3        * cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads.
4
52008-06-05      Joel Sherrill <joel.sherrill@OARcorp.com>
6
7        * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
8        parameter to indicate that the port uses the Simple Vectored
9        Interrupt model or the Programmable Interrupt Controller Model. The
10        PIC model is implemented primarily in the BSP and it is responsible
11        for all memory allocation.
12
132008-06-04      Joel Sherrill <joel.sherrill@OARcorp.com>
14
15        * rtems/score/cpu.h: Use a constant for CPU_STACK_MINIMUM_SIZE so it
16        can be used in cpp expressions. Using sizeof() requires actually
17        compiling the file.
18
192007-12-17      Joel Sherrill <joel.sherrill@oarcorp.com>
20
21        * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.
22
232007-12-04      Joel Sherrill <joel.sherrill@OARcorp.com>
24
25        * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU
26        Table to Configuration Table. Eliminate CPU Table from all ports.
27        Delete references to CPU Table in all forms.
28
292007-12-03      Joel Sherrill <joel.sherrill@OARcorp.com>
30
31        * rtems/score/cpu.h: Moved most of the remaining CPU Table fields to
32        the Configuration Table. This included pretasking_hook,
33        predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace,
34        extra_mpci_receive_server_stack, stack_allocate_hook, and
35        stack_free_hook. As a side-effect of this effort some multiprocessing
36        code was made conditional and some style clean up occurred.
37
382007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
39
40        * rtems/score/cpu.h: Eliminate the clicks_per_microsecond field in the
41        MIPS CPU Table and define another mechanism for drivers to obtain
42        this information.
43
442007-08-04      Ralf Corsépius <ralf.corsepius@rtems.org>
45
46        * rtems/score/cpu.h: Use uintptr_t instead of uint32_t.
47
482007-05-09      Ralf Corsépius <ralf.corsepius@rtems.org>
49
50        * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
51
522007-04-17      Ralf Corsépius <ralf.corsepius@rtems.org>
53
54        * rtems/score/cpu.h:
55          Use Context_Control_fp* instead of void* for fp_contexts.
56          Eliminate evil casts.
57
582006-11-17      Ralf Corsépius <ralf.corsepius@rtems.org>
59
60        * rtems/score/types.h: Remove unsigned64, signed64.
61
622006-06-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
63
64        * cpu.c: Added __mips==32 to fix build problems on those targets
65        caused by the Bruce Robinson.
66
672006-06-08 Bruce Robinson <brucer@pmccorp.com>
68
69        * cpu.c: Add int64 types for __mips==3 cpus, incorporate
70           mips_interrupt_mask() into mask computations
71        * cpu_asm.S: Add int64 register save/restores for __mips==3 cpus.  Adjustment
72           of mips1 vs mips3 macros.
73        * cpu.h: Add int64 types for __mips==3 cpus.
74       
752006-03-17      Ralf Corsepius <ralf.corsepius@rtems.org>
76
77        * cpu.c (_CPU_Initialize): Add fpu initialization.
78        * rtems/score/cpu.h: Setup CPU_*_ENDIAN from GCC's__MIPS{EL|EB}__.
79        (Partial merger of submission by Bruce Robinson <brucer@pmccorp.com>).
80
812006-01-16      Joel Sherrill <joel@OARcorp.com>
82
83        * rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
84        As a side-effect, grammar and spelling errors were corrected, spacing
85        errors were address, and some variable names were improved.
86
872005-11-18      Joel Sherrill <joel@OARcorp.com>
88
89        * rtems/score/cpu.h: Eliminate use of unsigned32.
90
912005-11-08      Ralf Corsepius <ralf.corsepius@rtems.org>
92
93        * rtems/score/types.h: Eliminate unsigned16, unsigned32.
94
952005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
96
97        * rtems/asm.h: Remove private version of CONCAT macros.
98        Include <rtems/concat.h> instead.
99
1002005-04-26      Joel Sherrill <joel@OARcorp.com>
101
102        * rtems/asm.h: Eliminate warnings.
103
1042005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
105
106        * Makefile.am: Split out preinstallation rules.
107        * preinstall.am: New (Split out from Makefile.am).
108
1092005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
110
111        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
112        Header guards cleanup.
113
1142005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
115
116        PR 754/rtems
117        * rtems/asm.h: New (relocated from .).
118        * asm.h: Remove (moved to rtems/asm.h).
119        * Makefile.am: Reflect changes above.
120
1212005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
122
123        PR rtems/752
124        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
125        New header guards.
126        * idtcpu.h, iregdef.h: Remove.
127        * Makefile.am: Reflect changes above.
128
1292004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
130
131        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
132        New header guards.
133
1342005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
135
136        * rtems/score/types.h: Remove signed8, signed16, signed32,
137        unsigned8, unsigned16, unsigned32.
138
1392005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
140
141        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
142
1432005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
144
145        * rtems/score/types.h: #include <rtems/stdint.h>.
146
1472005-01-07      Joel Sherrill <joel@OARcorp.com>
148
149        * rtems/score/cpu.h: Remove warnings.
150
1512005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
152
153        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
154
1552005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
156
157        PR 739
158        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
159        when compiling cpu_asm.S.  Problem was a #define sneaked in in
160        version 1.11, no ill effects would have only affected R4000
161        builds.
162
1632005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
164
165        PR 737
166        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
167        slot when compiling cpu_asm.S
168
1692005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
170
171        * Makefile.am: Remove build-variant support.
172
1732004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
174
175        PR 730
176        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
177        for rtems-4.7.
178
1792004-04-09      Joel Sherrill <joel@OARcorp.com>
180
181        PR 605/bsps
182        * cpu.c: Do not use C++ style comments.
183
1842004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
185        PR 601
186        * cpu_asm.S: Added __mips==32 support for R4000 processors running
187        32 bit code.  Fixed #define problems that caused fpu code to
188        always be included even when no fpu is present.
189
1902004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
191
192        PR 598/bsps
193        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
194        status/control register on context switches. Missing this register
195        was causing intermittent floating point errors.
196
1972003-09-04      Joel Sherrill <joel@OARcorp.com>
198
199        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
200        rtems/score/types.h: URL for license changed.
201
2022003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
203
204        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
205
2062003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
207
208        * configure.ac: Remove AC_CONFIG_AUX_DIR.
209
2102002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
211
212        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
213        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
214
2152002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
216
217        * configure.ac: Fix package name.
218
2192002-11-04      Joel Sherrill <joel@OARcorp.com>
220
221        * idtcpu.h: Removed warning.
222
2232002-11-01      Joel Sherrill <joel@OARcorp.com>
224
225        * idtcpu.h: Removed warnings.
226
2272002-10-28      Joel Sherrill <joel@OARcorp.com>
228
229        * idtcpu.h: Removed warning by turning extra token at the end of
230        an endif into a comment.
231
2322002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
233
234        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
235
2362002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
237
238        * .cvsignore: Reformat.
239        Add autom4te*cache.
240        Remove autom4te.cache.
241
2422002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
243
244        * cpu_asm.S: Clarified some comments, removed code that forced
245        SR_IEP on when returning from an interrupt.
246
2472002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
248
249        * configure.ac: Add RTEMS_PROG_CCAS
250
2512002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
252
253        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
254        Add AC_PROG_RANLIB.
255
2562002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
257        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
258        deadlock caused by interrupt arriving while dispatching.
259       
2602002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
261
262        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
263        Use ../../../aclocal.
264
2652001-04-03      Joel Sherrill <joel@OARcorp.com>
266
267        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
268        * rtems/score/mipstypes.h: Removed.
269        * rtems/score/types.h: New file via CVS magic.
270        * Makefile.am, rtems/score/cpu.h: Account for name change.
271
2722002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
273
274        * configure.ac:
275        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
276        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
277        * Makefile.am: Remove AUTOMAKE_OPTIONS.
278
2792002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
280
281        * cpu_asm.S: Now compiles on 4600 and 4650.
282
2832002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
284
285        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
286        * rtems/score/cpu.h: Fixed register numbering in comments and made
287        interrupt enable/disable more robust.
288       
2892002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
290        * cpu_asm.S: Added support for the debug exception vector, cleaned
291        up the exception processing & exception return stuff.  Re-added
292        EPC in the task context structure so the gdb stub will know where
293        a thread is executing.  Should've left it there in the first place...
294        * idtcpu.h: Added support for the debug exception vector.
295        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
296        stack frame in an interrupt so context switch code can get the
297        userspace EPC when scheduling.
298        * rtems/score/cpu.h: Re-added EPC to the task context.
299
3002002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
301
302        * cpu_asm.S: Fixed exception return address, modified FP context
303        switch so FPU is properly enabled and also doesn't screw up the
304        exception FP handling.
305        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
306        returning from exceptions.
307        * iregdef.h: Added R_TAR to the stack frame so the target address
308        can be saved on a per-exception basis.  The new entry is past the
309        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
310        stuff.
311        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
312        to obtain FPU defines without syntax errors generated by the C
313        defintions.
314        * cpu.c: Improved interrupt level saves & restores.
315       
3162002-02-08      Joel Sherrill <joel@OARcorp.com>
317
318        * iregdef.h, rtems/score/cpu.h: Reordered register in the
319        exception stack frame to better match gdb's expectations.
320
3212001-02-05      Joel Sherrill <joel@OARcorp.com>
322
323        * cpu_asm.S: Enhanced to save/restore more registers on
324        exceptions.
325        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
326        register individually and document when it is saved.
327        * idtcpu.h: Added constants for the coprocessor 1 registers
328        revision and status.
329
3302001-02-05      Joel Sherrill <joel@OARcorp.com>
331
332        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
333
3342001-02-04      Joel Sherrill <joel@OARcorp.com>
335
336        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
337        in the previous patch that has now been confirmed.
338
3392001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
340
341        * cpu.c: Enhancements and fixes for modifying the SR when changing
342        the interrupt level.
343        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
344        managed on a per-task basis, improved handling of interrupt levels,
345        and made deferred FP contexts work on the MIPS.
346        * rtems/score/cpu.h: Modified to support above changes.
347
3482002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
349
350        * rtems/Makefile.am: Removed.
351        * rtems/score/Makefile.am: Removed.
352        * configure.ac: Reflect changes above.
353        * Makefile.am: Reflect changes above.
354
3552002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
356
357        * asm.h: Remove #include <rtems/score/targopts.h>.
358        Add #include <rtems/score/cpuopts.h>.
359        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
360
361
3622001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
363
364        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
365
3662001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
367
368        * Makefile.am: Add multilib support.
369
3702001-11-28      Joel Sherrill <joel@OARcorp.com>,
371
372        This was tracked as PR91.
373        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
374        is used to specify if the port uses the standard macro for this (FALSE).
375        A TRUE setting indicates the port provides its own implementation.
376
3772001-10-12      Joel Sherrill <joel@OARcorp.com>
378
379        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
380        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
381        Wayne Bullaughey <wayne@wmi.com>.
382
3832001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
384
385        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
386        * configure.in: Remove.
387        * configure.ac: New file, generated from configure.in by autoupdate.
388
3892001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
390
391        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
392        * Makefile.am: Use 'PREINSTALL_FILES ='.
393
3942001-07-03      Joel Sherrill <joel@OARcorp.com>
395
396        * cpu.c: Fixed typo.
397
3982000-05-24      Joel Sherrill <joel@OARcorp.com>
399
400        * rtems/score/mips.h: Added constants for MIPS exception numbers.
401        All exceptions should be given low numbers and thus can be installed
402        and processed in a uniform manner.  Variances between various MIPS
403        ISA levels were not accounted for.
404
4052001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
406
407        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
408        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
409
4102001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
411
412        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
413        the context initialization to account for floating point tasks. 
414        * rtems/score/mips.h: Added the routines mips_set_cause(),
415        mips_get_fcr31(), and mips_set_fcr31().
416        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
417
4182001-05-07      Joel Sherrill <joel@OARcorp.com>
419
420        * cpu_asm.S: Merged patches from Gregory Menke
421        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
422        stack usage and include nops in the delay slots.
423
4242001-04-20      Joel Sherrill <joel@OARcorp.com>
425
426        * cpu_asm.S: Added code to save and restore SR and EPC to
427        properly support nested interrupts.  Note that the ISR
428        (not RTEMS) enables interrupts allowing the nesting to occur.
429
4302001-03-14      Joel Sherrill <joel@OARcorp.com>
431
432        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
433        Removed unused variable _CPU_Thread_dispatch_pointer
434        and cleaned numerous comments.
435       
4362001-03-13      Joel Sherrill <joel@OARcorp.com>
437
438        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
439        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
440        Also reimplemented some assembly routines in C further reducing
441        the amount of assembly and increasing maintainability.
442
4432001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
444
445        * Makefile.am, rtems/score/Makefile.am:
446        Apply include_*HEADERS instead of H_FILES.
447
4482001-01-12      Joel Sherrill <joel@OARcorp.com>
449
450        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
451        register constraints from "general" to "register".
452
4532001-01-09      Joel Sherrill <joel@OARcorp.com>
454
455        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
456        to make it easier to conditionalize the code for various ISA levels.
457
4582001-01-08      Joel Sherrill <joel@OARcorp.com>
459
460        * idtcpu.h: Commented out definition of "wait".  It was stupid to
461        use such a common word as a macro.
462        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
463        * rtems/score/mips.h: Added include of <idtcpu.h>.
464        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
465
4662001-01-03      Joel Sherrill <joel@OARcorp.com>
467
468        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
469        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
470
4712000-12-19      Joel Sherrill <joel@OARcorp.com>
472
473        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
474        Previous code resulting in the interrupted immediately returning
475        to the caller of the routine it was inside.
476
4772000-12-19      Joel Sherrill <joel@OARcorp.com>
478
479        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
480        because it has not been allocated yet.
481
4822000-12-13      Joel Sherrill <joel@OARcorp.com>
483
484        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
485        * cpu_asm.S: Removed assembly language to vector ISR handler
486        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
487        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
488        longer a constant -- get the real value from libcpu.
489
4902000-12-13      Joel Sherrill <joel@OARcorp.com>
491
492        * cpu_asm.h: Removed.
493        * Makefile.am: Remove cpu_asm.h.
494        * rtems/score/mips64orion.h: Renamed mips.h.
495        * rtems/score/mips.h: New file, formerly mips64orion.h.
496        Header rewritten.
497        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
498        mips_disable_in_interrupt_mask): New macros.
499        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
500        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
501        few defines that were in <cpu_asm.h>.
502        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
503        MIPS ISA 3 is still in assembly for now.
504        (_CPU_Thread_Idle_body): Rewrote in C.
505        * cpu_asm.S: Rewrote file header.
506        (FRAME,ENDFRAME) now in asm.h.
507        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
508        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
509        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
510        leaves other bits in SR alone on task switch.
511        (mips_enable_interrupts,mips_disable_interrupts,
512        mips_enable_global_interrupts,mips_disable_global_interrupts,
513        disable_int, enable_int): Removed.
514        (mips_get_sr): Rewritten as C macro.
515        (_CPU_Thread_Idle_body): Rewritten in C.
516        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
517        placed in libcpu.
518        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
519        to libcpu/mips/shared/interrupts.
520        (general): Cleaned up comment blocks and #if 0 areas.
521        * idtcpu.h: Made ifdef report an error.
522        * iregdef.h: Removed warning.
523        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
524        number defined by libcpu.
525        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
526        to access SR.
527        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
528        (_CPU_Context_Initialize): Honor ISR level in task initialization.
529        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
530
5312000-12-06      Joel Sherrill <joel@OARcorp.com>
532
533        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
534        context should be 32 not 64 bits.
535
5362000-11-30      Joel Sherrill <joel@OARcorp.com>
537
538        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
539        correct name of _CPU_Context_switch_restore.  Added dummy
540        version of exc_utlb_code() so applications would link.
541
5422000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
543
544        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
545
5462000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
547
548        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
549
5502000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
551
552        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
553        Switch to GNU canonicalization.
554
5552000-10-24      Alan Cudmore <alanc@linuxstart.com> and
556        Joel Sherrill <joel@OARcorp.com>
557
558        * This is a major reworking of the mips64orion port to use
559        gcc predefines as much as possible and a big push to multilib
560        the mips port.  The mips64orion port was copied/renamed to mips
561        to be more like other GNU tools.  Alan did most of the technical
562        work of determining how to map old macro names used by the mips64orion
563        port to standard compiler macro definitions.  Joel did the merge
564        with CVS magic to keep individual file history and did the BSP
565        modifications. Details follow:
566        * Makefile.am: idtmon.h in mips64orion port not present.
567        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
568        * cpu.c: Comments added.
569        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
570        First attempt at exception/interrupt processing for ISA level 1
571        and minus any use of IDT/MON added.
572        * idtcpu.h: Conditionals changed to use gcc predefines.
573        * iregdef.h: Ditto.
574        * cpu_asm.h: No real change.  Merger required commit.
575        * rtems/Makefile.am: Ditto.
576        * rtems/score/Makefile.am: Ditto.
577        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
578        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
579        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
580
5812000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
582
583        * Makefile.am: Include compile.am.
584
5852000-08-10      Joel Sherrill <joel@OARcorp.com>
586
587        * ChangeLog: New file.
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