source: rtems/cpukit/score/cpu/mips/ChangeLog @ 3b1c100

4.104.114.84.95
Last change on this file since 3b1c100 was 3b1c100, checked in by Joel Sherrill <joel.sherrill@…>, on 09/26/03 at 21:56:41

2003-09-26 Joel Sherrill <joel@…>

  • rtems/score/cpu.h: Obsoleting HP PA-RISC port and removing all references.
  • Property mode set to 100644
File size: 14.0 KB
Line 
12003-09-26      Joel Sherrill <joel@OARcorp.com>
2
3        * rtems/score/cpu.h: Obsoleting HP PA-RISC port and removing all
4        references.
5
62003-09-04      Joel Sherrill <joel@OARcorp.com>
7
8        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
9        rtems/score/types.h: URL for license changed.
10
112003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
12
13        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
14
152003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
16
17        * configure.ac: Remove AC_CONFIG_AUX_DIR.
18
192002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
20
21        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
22        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
23
242002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
25
26        * configure.ac: Fix package name.
27
282002-11-04      Joel Sherrill <joel@OARcorp.com>
29
30        * idtcpu.h: Removed warning.
31
322002-11-01      Joel Sherrill <joel@OARcorp.com>
33
34        * idtcpu.h: Removed warnings.
35
362002-10-28      Joel Sherrill <joel@OARcorp.com>
37
38        * idtcpu.h: Removed warning by turning extra token at the end of
39        an endif into a comment.
40
412002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
42
43        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
44
452002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
46
47        * .cvsignore: Reformat.
48        Add autom4te*cache.
49        Remove autom4te.cache.
50
512002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
52
53        * cpu_asm.S: Clarified some comments, removed code that forced
54        SR_IEP on when returning from an interrupt.
55
562002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
57
58        * configure.ac: Add RTEMS_PROG_CCAS
59
602002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
61
62        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
63        Add AC_PROG_RANLIB.
64
652002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
66        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
67        deadlock caused by interrupt arriving while dispatching.
68       
692002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
70
71        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
72        Use ../../../aclocal.
73
742001-04-03      Joel Sherrill <joel@OARcorp.com>
75
76        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
77        * rtems/score/mipstypes.h: Removed.
78        * rtems/score/types.h: New file via CVS magic.
79        * Makefile.am, rtems/score/cpu.h: Account for name change.
80
812002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
82
83        * configure.ac:
84        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
85        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
86        * Makefile.am: Remove AUTOMAKE_OPTIONS.
87
882002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
89
90        * cpu_asm.S: Now compiles on 4600 and 4650.
91
922002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
93
94        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
95        * rtems/score/cpu.h: Fixed register numbering in comments and made
96        interrupt enable/disable more robust.
97       
982002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
99        * cpu_asm.S: Added support for the debug exception vector, cleaned
100        up the exception processing & exception return stuff.  Re-added
101        EPC in the task context structure so the gdb stub will know where
102        a thread is executing.  Should've left it there in the first place...
103        * idtcpu.h: Added support for the debug exception vector.
104        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
105        stack frame in an interrupt so context switch code can get the
106        userspace EPC when scheduling.
107        * rtems/score/cpu.h: Re-added EPC to the task context.
108
1092002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
110
111        * cpu_asm.S: Fixed exception return address, modified FP context
112        switch so FPU is properly enabled and also doesn't screw up the
113        exception FP handling.
114        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
115        returning from exceptions.
116        * iregdef.h: Added R_TAR to the stack frame so the target address
117        can be saved on a per-exception basis.  The new entry is past the
118        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
119        stuff.
120        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
121        to obtain FPU defines without syntax errors generated by the C
122        defintions.
123        * cpu.c: Improved interrupt level saves & restores.
124       
1252002-02-08      Joel Sherrill <joel@OARcorp.com>
126
127        * iregdef.h, rtems/score/cpu.h: Reordered register in the
128        exception stack frame to better match gdb's expectations.
129
1302001-02-05      Joel Sherrill <joel@OARcorp.com>
131
132        * cpu_asm.S: Enhanced to save/restore more registers on
133        exceptions.
134        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
135        register individually and document when it is saved.
136        * idtcpu.h: Added constants for the coprocessor 1 registers
137        revision and status.
138
1392001-02-05      Joel Sherrill <joel@OARcorp.com>
140
141        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
142
1432001-02-04      Joel Sherrill <joel@OARcorp.com>
144
145        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
146        in the previous patch that has now been confirmed.
147
1482001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
149
150        * cpu.c: Enhancements and fixes for modifying the SR when changing
151        the interrupt level.
152        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
153        managed on a per-task basis, improved handling of interrupt levels,
154        and made deferred FP contexts work on the MIPS.
155        * rtems/score/cpu.h: Modified to support above changes.
156
1572002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
158
159        * rtems/Makefile.am: Removed.
160        * rtems/score/Makefile.am: Removed.
161        * configure.ac: Reflect changes above.
162        * Makefile.am: Reflect changes above.
163
1642002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
165
166        * asm.h: Remove #include <rtems/score/targopts.h>.
167        Add #include <rtems/score/cpuopts.h>.
168        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
169
170
1712001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
172
173        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
174
1752001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
176
177        * Makefile.am: Add multilib support.
178
1792001-11-28      Joel Sherrill <joel@OARcorp.com>,
180
181        This was tracked as PR91.
182        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
183        is used to specify if the port uses the standard macro for this (FALSE).
184        A TRUE setting indicates the port provides its own implementation.
185
1862001-10-12      Joel Sherrill <joel@OARcorp.com>
187
188        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
189        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
190        Wayne Bullaughey <wayne@wmi.com>.
191
1922001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
193
194        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
195        * configure.in: Remove.
196        * configure.ac: New file, generated from configure.in by autoupdate.
197
1982001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
199
200        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
201        * Makefile.am: Use 'PREINSTALL_FILES ='.
202
2032001-07-03      Joel Sherrill <joel@OARcorp.com>
204
205        * cpu.c: Fixed typo.
206
2072000-05-24      Joel Sherrill <joel@OARcorp.com>
208
209        * rtems/score/mips.h: Added constants for MIPS exception numbers.
210        All exceptions should be given low numbers and thus can be installed
211        and processed in a uniform manner.  Variances between various MIPS
212        ISA levels were not accounted for.
213
2142001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
215
216        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
217        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
218
2192001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
220
221        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
222        the context initialization to account for floating point tasks. 
223        * rtems/score/mips.h: Added the routines mips_set_cause(),
224        mips_get_fcr31(), and mips_set_fcr31().
225        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
226
2272001-05-07      Joel Sherrill <joel@OARcorp.com>
228
229        * cpu_asm.S: Merged patches from Gregory Menke
230        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
231        stack usage and include nops in the delay slots.
232
2332001-04-20      Joel Sherrill <joel@OARcorp.com>
234
235        * cpu_asm.S: Added code to save and restore SR and EPC to
236        properly support nested interrupts.  Note that the ISR
237        (not RTEMS) enables interrupts allowing the nesting to occur.
238
2392001-03-14      Joel Sherrill <joel@OARcorp.com>
240
241        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
242        Removed unused variable _CPU_Thread_dispatch_pointer
243        and cleaned numerous comments.
244       
2452001-03-13      Joel Sherrill <joel@OARcorp.com>
246
247        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
248        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
249        Also reimplemented some assembly routines in C further reducing
250        the amount of assembly and increasing maintainability.
251
2522001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
253
254        * Makefile.am, rtems/score/Makefile.am:
255        Apply include_*HEADERS instead of H_FILES.
256
2572001-01-12      Joel Sherrill <joel@OARcorp.com>
258
259        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
260        register constraints from "general" to "register".
261
2622001-01-09      Joel Sherrill <joel@OARcorp.com>
263
264        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
265        to make it easier to conditionalize the code for various ISA levels.
266
2672001-01-08      Joel Sherrill <joel@OARcorp.com>
268
269        * idtcpu.h: Commented out definition of "wait".  It was stupid to
270        use such a common word as a macro.
271        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
272        * rtems/score/mips.h: Added include of <idtcpu.h>.
273        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
274
2752001-01-03      Joel Sherrill <joel@OARcorp.com>
276
277        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
278        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
279
2802000-12-19      Joel Sherrill <joel@OARcorp.com>
281
282        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
283        Previous code resulting in the interrupted immediately returning
284        to the caller of the routine it was inside.
285
2862000-12-19      Joel Sherrill <joel@OARcorp.com>
287
288        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
289        because it has not been allocated yet.
290
2912000-12-13      Joel Sherrill <joel@OARcorp.com>
292
293        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
294        * cpu_asm.S: Removed assembly language to vector ISR handler
295        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
296        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
297        longer a constant -- get the real value from libcpu.
298
2992000-12-13      Joel Sherrill <joel@OARcorp.com>
300
301        * cpu_asm.h: Removed.
302        * Makefile.am: Remove cpu_asm.h.
303        * rtems/score/mips64orion.h: Renamed mips.h.
304        * rtems/score/mips.h: New file, formerly mips64orion.h.
305        Header rewritten.
306        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
307        mips_disable_in_interrupt_mask): New macros.
308        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
309        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
310        few defines that were in <cpu_asm.h>.
311        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
312        MIPS ISA 3 is still in assembly for now.
313        (_CPU_Thread_Idle_body): Rewrote in C.
314        * cpu_asm.S: Rewrote file header.
315        (FRAME,ENDFRAME) now in asm.h.
316        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
317        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
318        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
319        leaves other bits in SR alone on task switch.
320        (mips_enable_interrupts,mips_disable_interrupts,
321        mips_enable_global_interrupts,mips_disable_global_interrupts,
322        disable_int, enable_int): Removed.
323        (mips_get_sr): Rewritten as C macro.
324        (_CPU_Thread_Idle_body): Rewritten in C.
325        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
326        placed in libcpu.
327        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
328        to libcpu/mips/shared/interrupts.
329        (general): Cleaned up comment blocks and #if 0 areas.
330        * idtcpu.h: Made ifdef report an error.
331        * iregdef.h: Removed warning.
332        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
333        number defined by libcpu.
334        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
335        to access SR.
336        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
337        (_CPU_Context_Initialize): Honor ISR level in task initialization.
338        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
339
3402000-12-06      Joel Sherrill <joel@OARcorp.com>
341
342        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
343        context should be 32 not 64 bits.
344
3452000-11-30      Joel Sherrill <joel@OARcorp.com>
346
347        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
348        correct name of _CPU_Context_switch_restore.  Added dummy
349        version of exc_utlb_code() so applications would link.
350
3512000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
352
353        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
354
3552000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
356
357        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
358
3592000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
360
361        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
362        Switch to GNU canonicalization.
363
3642000-10-24      Alan Cudmore <alanc@linuxstart.com> and
365        Joel Sherrill <joel@OARcorp.com>
366
367        * This is a major reworking of the mips64orion port to use
368        gcc predefines as much as possible and a big push to multilib
369        the mips port.  The mips64orion port was copied/renamed to mips
370        to be more like other GNU tools.  Alan did most of the technical
371        work of determining how to map old macro names used by the mips64orion
372        port to standard compiler macro definitions.  Joel did the merge
373        with CVS magic to keep individual file history and did the BSP
374        modifications. Details follow:
375        * Makefile.am: idtmon.h in mips64orion port not present.
376        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
377        * cpu.c: Comments added.
378        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
379        First attempt at exception/interrupt processing for ISA level 1
380        and minus any use of IDT/MON added.
381        * idtcpu.h: Conditionals changed to use gcc predefines.
382        * iregdef.h: Ditto.
383        * cpu_asm.h: No real change.  Merger required commit.
384        * rtems/Makefile.am: Ditto.
385        * rtems/score/Makefile.am: Ditto.
386        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
387        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
388        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
389
3902000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
391
392        * Makefile.am: Include compile.am.
393
3942000-08-10      Joel Sherrill <joel@OARcorp.com>
395
396        * ChangeLog: New file.
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