source: rtems/cpukit/score/cpu/mips/ChangeLog @ 32f415d

4.104.114.84.95
Last change on this file since 32f415d was 32f415d, checked in by Joel Sherrill <joel.sherrill@…>, on 12/13/00 at 18:09:48

2000-12-13 Joel Sherrill <joel@…>

  • cpu_asm.h: Removed.
  • Makefile.am: Remove cpu_asm.h.
  • rtems/score/mips64orion.h: Renamed mips.h.
  • rtems/score/mips.h: New file, formerly mips64orion.h. Header rewritten. (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask, mips_disable_in_interrupt_mask): New macros.
  • rtems/score/Makefile.am: Reflect renaming mips64orion.h.
  • asm.h: Include <mips.h> not <mips64orion.h>. Now includes the few defines that were in <cpu_asm.h>.
  • cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine. MIPS ISA 3 is still in assembly for now. (_CPU_Thread_Idle_body): Rewrote in C.
  • cpu_asm.S: Rewrote file header. (FRAME,ENDFRAME) now in asm.h. (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C. (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C. (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and leaves other bits in SR alone on task switch. (mips_enable_interrupts,mips_disable_interrupts, mips_enable_global_interrupts,mips_disable_global_interrupts, disable_int, enable_int): Removed. (mips_get_sr): Rewritten as C macro. (_CPU_Thread_Idle_body): Rewritten in C. (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and placed in libcpu. (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved to libcpu/mips/shared/interrupts. (general): Cleaned up comment blocks and #if 0 areas.
  • idtcpu.h: Made ifdef report an error.
  • iregdef.h: Removed warning.
  • rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable number defined by libcpu. (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines to access SR. (_CPU_ISR_Set_level): Rewritten as macro for ISA I. (_CPU_Context_Initialize): Honor ISR level in task initialization. (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
  • Property mode set to 100644
File size: 4.0 KB
Line 
12000-12-13      Joel Sherrill <joel@OARcorp.com>
2
3        * cpu_asm.h: Removed.
4        * Makefile.am: Remove cpu_asm.h.
5        * rtems/score/mips64orion.h: Renamed mips.h.
6        * rtems/score/mips.h: New file, formerly mips64orion.h.
7        Header rewritten.
8        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
9        mips_disable_in_interrupt_mask): New macros.
10        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
11        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
12        few defines that were in <cpu_asm.h>.
13        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
14        MIPS ISA 3 is still in assembly for now.
15        (_CPU_Thread_Idle_body): Rewrote in C.
16        * cpu_asm.S: Rewrote file header.
17        (FRAME,ENDFRAME) now in asm.h.
18        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
19        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
20        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
21        leaves other bits in SR alone on task switch.
22        (mips_enable_interrupts,mips_disable_interrupts,
23        mips_enable_global_interrupts,mips_disable_global_interrupts,
24        disable_int, enable_int): Removed.
25        (mips_get_sr): Rewritten as C macro.
26        (_CPU_Thread_Idle_body): Rewritten in C.
27        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
28        placed in libcpu.
29        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
30        to libcpu/mips/shared/interrupts.
31        (general): Cleaned up comment blocks and #if 0 areas.
32        * idtcpu.h: Made ifdef report an error.
33        * iregdef.h: Removed warning.
34        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
35        number defined by libcpu.
36        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
37        to access SR.
38        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
39        (_CPU_Context_Initialize): Honor ISR level in task initialization.
40        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
41
422000-12-06      Joel Sherrill <joel@OARcorp.com>
43
44        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
45        context should be 32 not 64 bits.
46
472000-11-30      Joel Sherrill <joel@OARcorp.com>
48
49        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
50        correct name of _CPU_Context_switch_restore.  Added dummy
51        version of exc_utlb_code() so applications would link.
52
532000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
54
55        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
56
572000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
58
59        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
60
612000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
62
63        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
64        Switch to GNU canonicalization.
65
662000-10-24      Alan Cudmore <alanc@linuxstart.com> and
67        Joel Sherrill <joel@OARcorp.com>
68
69        * This is a major reworking of the mips64orion port to use
70        gcc predefines as much as possible and a big push to multilib
71        the mips port.  The mips64orion port was copied/renamed to mips
72        to be more like other GNU tools.  Alan did most of the technical
73        work of determining how to map old macro names used by the mips64orion
74        port to standard compiler macro definitions.  Joel did the merge
75        with CVS magic to keep individual file history and did the BSP
76        modifications. Details follow:
77        * Makefile.am: idtmon.h in mips64orion port not present.
78        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
79        * cpu.c: Comments added.
80        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
81        First attempt at exception/interrupt processing for ISA level 1
82        and minus any use of IDT/MON added.
83        * idtcpu.h: Conditionals changed to use gcc predefines.
84        * iregdef.h: Ditto.
85        * cpu_asm.h: No real change.  Merger required commit.
86        * rtems/Makefile.am: Ditto.
87        * rtems/score/Makefile.am: Ditto.
88        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
89        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
90        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
91
922000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
93
94        * Makefile.am: Include compile.am.
95
962000-08-10      Joel Sherrill <joel@OARcorp.com>
97
98        * ChangeLog: New file.
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