source: rtems/cpukit/score/cpu/mips/ChangeLog @ 2fd427c

4.104.114.95
Last change on this file since 2fd427c was 2fd427c, checked in by Joel Sherrill <joel.sherrill@…>, on 06/05/08 at 14:30:07

2008-06-05 Joel Sherrill <joel.sherrill@…>

  • rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting parameter to indicate that the port uses the Simple Vectored Interrupt model or the Programmable Interrupt Controller Model. The PIC model is implemented primarily in the BSP and it is responsible for all memory allocation.
  • Property mode set to 100644
File size: 19.8 KB
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12008-06-05      Joel Sherrill <joel.sherrill@OARcorp.com>
2
3        * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
4        parameter to indicate that the port uses the Simple Vectored
5        Interrupt model or the Programmable Interrupt Controller Model. The
6        PIC model is implemented primarily in the BSP and it is responsible
7        for all memory allocation.
8
92008-06-04      Joel Sherrill <joel.sherrill@OARcorp.com>
10
11        * rtems/score/cpu.h: Use a constant for CPU_STACK_MINIMUM_SIZE so it
12        can be used in cpp expressions. Using sizeof() requires actually
13        compiling the file.
14
152007-12-17      Joel Sherrill <joel.sherrill@oarcorp.com>
16
17        * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.
18
192007-12-04      Joel Sherrill <joel.sherrill@OARcorp.com>
20
21        * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU
22        Table to Configuration Table. Eliminate CPU Table from all ports.
23        Delete references to CPU Table in all forms.
24
252007-12-03      Joel Sherrill <joel.sherrill@OARcorp.com>
26
27        * rtems/score/cpu.h: Moved most of the remaining CPU Table fields to
28        the Configuration Table. This included pretasking_hook,
29        predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace,
30        extra_mpci_receive_server_stack, stack_allocate_hook, and
31        stack_free_hook. As a side-effect of this effort some multiprocessing
32        code was made conditional and some style clean up occurred.
33
342007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
35
36        * rtems/score/cpu.h: Eliminate the clicks_per_microsecond field in the
37        MIPS CPU Table and define another mechanism for drivers to obtain
38        this information.
39
402007-08-04      Ralf Corsépius <ralf.corsepius@rtems.org>
41
42        * rtems/score/cpu.h: Use uintptr_t instead of uint32_t.
43
442007-05-09      Ralf Corsépius <ralf.corsepius@rtems.org>
45
46        * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
47
482007-04-17      Ralf Corsépius <ralf.corsepius@rtems.org>
49
50        * rtems/score/cpu.h:
51          Use Context_Control_fp* instead of void* for fp_contexts.
52          Eliminate evil casts.
53
542006-11-17      Ralf Corsépius <ralf.corsepius@rtems.org>
55
56        * rtems/score/types.h: Remove unsigned64, signed64.
57
582006-06-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
59
60        * cpu.c: Added __mips==32 to fix build problems on those targets
61        caused by the Bruce Robinson.
62
632006-06-08 Bruce Robinson <brucer@pmccorp.com>
64
65        * cpu.c: Add int64 types for __mips==3 cpus, incorporate
66           mips_interrupt_mask() into mask computations
67        * cpu_asm.S: Add int64 register save/restores for __mips==3 cpus.  Adjustment
68           of mips1 vs mips3 macros.
69        * cpu.h: Add int64 types for __mips==3 cpus.
70       
712006-03-17      Ralf Corsepius <ralf.corsepius@rtems.org>
72
73        * cpu.c (_CPU_Initialize): Add fpu initialization.
74        * rtems/score/cpu.h: Setup CPU_*_ENDIAN from GCC's__MIPS{EL|EB}__.
75        (Partial merger of submission by Bruce Robinson <brucer@pmccorp.com>).
76
772006-01-16      Joel Sherrill <joel@OARcorp.com>
78
79        * rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
80        As a side-effect, grammar and spelling errors were corrected, spacing
81        errors were address, and some variable names were improved.
82
832005-11-18      Joel Sherrill <joel@OARcorp.com>
84
85        * rtems/score/cpu.h: Eliminate use of unsigned32.
86
872005-11-08      Ralf Corsepius <ralf.corsepius@rtems.org>
88
89        * rtems/score/types.h: Eliminate unsigned16, unsigned32.
90
912005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
92
93        * rtems/asm.h: Remove private version of CONCAT macros.
94        Include <rtems/concat.h> instead.
95
962005-04-26      Joel Sherrill <joel@OARcorp.com>
97
98        * rtems/asm.h: Eliminate warnings.
99
1002005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
101
102        * Makefile.am: Split out preinstallation rules.
103        * preinstall.am: New (Split out from Makefile.am).
104
1052005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
106
107        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
108        Header guards cleanup.
109
1102005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
111
112        PR 754/rtems
113        * rtems/asm.h: New (relocated from .).
114        * asm.h: Remove (moved to rtems/asm.h).
115        * Makefile.am: Reflect changes above.
116
1172005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
118
119        PR rtems/752
120        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
121        New header guards.
122        * idtcpu.h, iregdef.h: Remove.
123        * Makefile.am: Reflect changes above.
124
1252004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
126
127        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
128        New header guards.
129
1302005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
131
132        * rtems/score/types.h: Remove signed8, signed16, signed32,
133        unsigned8, unsigned16, unsigned32.
134
1352005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
136
137        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
138
1392005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
140
141        * rtems/score/types.h: #include <rtems/stdint.h>.
142
1432005-01-07      Joel Sherrill <joel@OARcorp.com>
144
145        * rtems/score/cpu.h: Remove warnings.
146
1472005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
148
149        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
150
1512005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
152
153        PR 739
154        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
155        when compiling cpu_asm.S.  Problem was a #define sneaked in in
156        version 1.11, no ill effects would have only affected R4000
157        builds.
158
1592005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
160
161        PR 737
162        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
163        slot when compiling cpu_asm.S
164
1652005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
166
167        * Makefile.am: Remove build-variant support.
168
1692004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
170
171        PR 730
172        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
173        for rtems-4.7.
174
1752004-04-09      Joel Sherrill <joel@OARcorp.com>
176
177        PR 605/bsps
178        * cpu.c: Do not use C++ style comments.
179
1802004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
181        PR 601
182        * cpu_asm.S: Added __mips==32 support for R4000 processors running
183        32 bit code.  Fixed #define problems that caused fpu code to
184        always be included even when no fpu is present.
185
1862004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
187
188        PR 598/bsps
189        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
190        status/control register on context switches. Missing this register
191        was causing intermittent floating point errors.
192
1932003-09-04      Joel Sherrill <joel@OARcorp.com>
194
195        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
196        rtems/score/types.h: URL for license changed.
197
1982003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
199
200        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
201
2022003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
203
204        * configure.ac: Remove AC_CONFIG_AUX_DIR.
205
2062002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
207
208        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
209        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
210
2112002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
212
213        * configure.ac: Fix package name.
214
2152002-11-04      Joel Sherrill <joel@OARcorp.com>
216
217        * idtcpu.h: Removed warning.
218
2192002-11-01      Joel Sherrill <joel@OARcorp.com>
220
221        * idtcpu.h: Removed warnings.
222
2232002-10-28      Joel Sherrill <joel@OARcorp.com>
224
225        * idtcpu.h: Removed warning by turning extra token at the end of
226        an endif into a comment.
227
2282002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
229
230        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
231
2322002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
233
234        * .cvsignore: Reformat.
235        Add autom4te*cache.
236        Remove autom4te.cache.
237
2382002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
239
240        * cpu_asm.S: Clarified some comments, removed code that forced
241        SR_IEP on when returning from an interrupt.
242
2432002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
244
245        * configure.ac: Add RTEMS_PROG_CCAS
246
2472002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
248
249        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
250        Add AC_PROG_RANLIB.
251
2522002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
253        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
254        deadlock caused by interrupt arriving while dispatching.
255       
2562002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
257
258        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
259        Use ../../../aclocal.
260
2612001-04-03      Joel Sherrill <joel@OARcorp.com>
262
263        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
264        * rtems/score/mipstypes.h: Removed.
265        * rtems/score/types.h: New file via CVS magic.
266        * Makefile.am, rtems/score/cpu.h: Account for name change.
267
2682002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
269
270        * configure.ac:
271        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
272        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
273        * Makefile.am: Remove AUTOMAKE_OPTIONS.
274
2752002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
276
277        * cpu_asm.S: Now compiles on 4600 and 4650.
278
2792002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
280
281        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
282        * rtems/score/cpu.h: Fixed register numbering in comments and made
283        interrupt enable/disable more robust.
284       
2852002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
286        * cpu_asm.S: Added support for the debug exception vector, cleaned
287        up the exception processing & exception return stuff.  Re-added
288        EPC in the task context structure so the gdb stub will know where
289        a thread is executing.  Should've left it there in the first place...
290        * idtcpu.h: Added support for the debug exception vector.
291        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
292        stack frame in an interrupt so context switch code can get the
293        userspace EPC when scheduling.
294        * rtems/score/cpu.h: Re-added EPC to the task context.
295
2962002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
297
298        * cpu_asm.S: Fixed exception return address, modified FP context
299        switch so FPU is properly enabled and also doesn't screw up the
300        exception FP handling.
301        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
302        returning from exceptions.
303        * iregdef.h: Added R_TAR to the stack frame so the target address
304        can be saved on a per-exception basis.  The new entry is past the
305        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
306        stuff.
307        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
308        to obtain FPU defines without syntax errors generated by the C
309        defintions.
310        * cpu.c: Improved interrupt level saves & restores.
311       
3122002-02-08      Joel Sherrill <joel@OARcorp.com>
313
314        * iregdef.h, rtems/score/cpu.h: Reordered register in the
315        exception stack frame to better match gdb's expectations.
316
3172001-02-05      Joel Sherrill <joel@OARcorp.com>
318
319        * cpu_asm.S: Enhanced to save/restore more registers on
320        exceptions.
321        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
322        register individually and document when it is saved.
323        * idtcpu.h: Added constants for the coprocessor 1 registers
324        revision and status.
325
3262001-02-05      Joel Sherrill <joel@OARcorp.com>
327
328        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
329
3302001-02-04      Joel Sherrill <joel@OARcorp.com>
331
332        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
333        in the previous patch that has now been confirmed.
334
3352001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
336
337        * cpu.c: Enhancements and fixes for modifying the SR when changing
338        the interrupt level.
339        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
340        managed on a per-task basis, improved handling of interrupt levels,
341        and made deferred FP contexts work on the MIPS.
342        * rtems/score/cpu.h: Modified to support above changes.
343
3442002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
345
346        * rtems/Makefile.am: Removed.
347        * rtems/score/Makefile.am: Removed.
348        * configure.ac: Reflect changes above.
349        * Makefile.am: Reflect changes above.
350
3512002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
352
353        * asm.h: Remove #include <rtems/score/targopts.h>.
354        Add #include <rtems/score/cpuopts.h>.
355        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
356
357
3582001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
359
360        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
361
3622001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
363
364        * Makefile.am: Add multilib support.
365
3662001-11-28      Joel Sherrill <joel@OARcorp.com>,
367
368        This was tracked as PR91.
369        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
370        is used to specify if the port uses the standard macro for this (FALSE).
371        A TRUE setting indicates the port provides its own implementation.
372
3732001-10-12      Joel Sherrill <joel@OARcorp.com>
374
375        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
376        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
377        Wayne Bullaughey <wayne@wmi.com>.
378
3792001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
380
381        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
382        * configure.in: Remove.
383        * configure.ac: New file, generated from configure.in by autoupdate.
384
3852001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
386
387        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
388        * Makefile.am: Use 'PREINSTALL_FILES ='.
389
3902001-07-03      Joel Sherrill <joel@OARcorp.com>
391
392        * cpu.c: Fixed typo.
393
3942000-05-24      Joel Sherrill <joel@OARcorp.com>
395
396        * rtems/score/mips.h: Added constants for MIPS exception numbers.
397        All exceptions should be given low numbers and thus can be installed
398        and processed in a uniform manner.  Variances between various MIPS
399        ISA levels were not accounted for.
400
4012001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
402
403        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
404        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
405
4062001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
407
408        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
409        the context initialization to account for floating point tasks. 
410        * rtems/score/mips.h: Added the routines mips_set_cause(),
411        mips_get_fcr31(), and mips_set_fcr31().
412        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
413
4142001-05-07      Joel Sherrill <joel@OARcorp.com>
415
416        * cpu_asm.S: Merged patches from Gregory Menke
417        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
418        stack usage and include nops in the delay slots.
419
4202001-04-20      Joel Sherrill <joel@OARcorp.com>
421
422        * cpu_asm.S: Added code to save and restore SR and EPC to
423        properly support nested interrupts.  Note that the ISR
424        (not RTEMS) enables interrupts allowing the nesting to occur.
425
4262001-03-14      Joel Sherrill <joel@OARcorp.com>
427
428        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
429        Removed unused variable _CPU_Thread_dispatch_pointer
430        and cleaned numerous comments.
431       
4322001-03-13      Joel Sherrill <joel@OARcorp.com>
433
434        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
435        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
436        Also reimplemented some assembly routines in C further reducing
437        the amount of assembly and increasing maintainability.
438
4392001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
440
441        * Makefile.am, rtems/score/Makefile.am:
442        Apply include_*HEADERS instead of H_FILES.
443
4442001-01-12      Joel Sherrill <joel@OARcorp.com>
445
446        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
447        register constraints from "general" to "register".
448
4492001-01-09      Joel Sherrill <joel@OARcorp.com>
450
451        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
452        to make it easier to conditionalize the code for various ISA levels.
453
4542001-01-08      Joel Sherrill <joel@OARcorp.com>
455
456        * idtcpu.h: Commented out definition of "wait".  It was stupid to
457        use such a common word as a macro.
458        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
459        * rtems/score/mips.h: Added include of <idtcpu.h>.
460        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
461
4622001-01-03      Joel Sherrill <joel@OARcorp.com>
463
464        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
465        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
466
4672000-12-19      Joel Sherrill <joel@OARcorp.com>
468
469        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
470        Previous code resulting in the interrupted immediately returning
471        to the caller of the routine it was inside.
472
4732000-12-19      Joel Sherrill <joel@OARcorp.com>
474
475        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
476        because it has not been allocated yet.
477
4782000-12-13      Joel Sherrill <joel@OARcorp.com>
479
480        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
481        * cpu_asm.S: Removed assembly language to vector ISR handler
482        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
483        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
484        longer a constant -- get the real value from libcpu.
485
4862000-12-13      Joel Sherrill <joel@OARcorp.com>
487
488        * cpu_asm.h: Removed.
489        * Makefile.am: Remove cpu_asm.h.
490        * rtems/score/mips64orion.h: Renamed mips.h.
491        * rtems/score/mips.h: New file, formerly mips64orion.h.
492        Header rewritten.
493        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
494        mips_disable_in_interrupt_mask): New macros.
495        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
496        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
497        few defines that were in <cpu_asm.h>.
498        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
499        MIPS ISA 3 is still in assembly for now.
500        (_CPU_Thread_Idle_body): Rewrote in C.
501        * cpu_asm.S: Rewrote file header.
502        (FRAME,ENDFRAME) now in asm.h.
503        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
504        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
505        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
506        leaves other bits in SR alone on task switch.
507        (mips_enable_interrupts,mips_disable_interrupts,
508        mips_enable_global_interrupts,mips_disable_global_interrupts,
509        disable_int, enable_int): Removed.
510        (mips_get_sr): Rewritten as C macro.
511        (_CPU_Thread_Idle_body): Rewritten in C.
512        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
513        placed in libcpu.
514        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
515        to libcpu/mips/shared/interrupts.
516        (general): Cleaned up comment blocks and #if 0 areas.
517        * idtcpu.h: Made ifdef report an error.
518        * iregdef.h: Removed warning.
519        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
520        number defined by libcpu.
521        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
522        to access SR.
523        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
524        (_CPU_Context_Initialize): Honor ISR level in task initialization.
525        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
526
5272000-12-06      Joel Sherrill <joel@OARcorp.com>
528
529        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
530        context should be 32 not 64 bits.
531
5322000-11-30      Joel Sherrill <joel@OARcorp.com>
533
534        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
535        correct name of _CPU_Context_switch_restore.  Added dummy
536        version of exc_utlb_code() so applications would link.
537
5382000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
539
540        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
541
5422000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
543
544        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
545
5462000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
547
548        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
549        Switch to GNU canonicalization.
550
5512000-10-24      Alan Cudmore <alanc@linuxstart.com> and
552        Joel Sherrill <joel@OARcorp.com>
553
554        * This is a major reworking of the mips64orion port to use
555        gcc predefines as much as possible and a big push to multilib
556        the mips port.  The mips64orion port was copied/renamed to mips
557        to be more like other GNU tools.  Alan did most of the technical
558        work of determining how to map old macro names used by the mips64orion
559        port to standard compiler macro definitions.  Joel did the merge
560        with CVS magic to keep individual file history and did the BSP
561        modifications. Details follow:
562        * Makefile.am: idtmon.h in mips64orion port not present.
563        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
564        * cpu.c: Comments added.
565        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
566        First attempt at exception/interrupt processing for ISA level 1
567        and minus any use of IDT/MON added.
568        * idtcpu.h: Conditionals changed to use gcc predefines.
569        * iregdef.h: Ditto.
570        * cpu_asm.h: No real change.  Merger required commit.
571        * rtems/Makefile.am: Ditto.
572        * rtems/score/Makefile.am: Ditto.
573        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
574        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
575        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
576
5772000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
578
579        * Makefile.am: Include compile.am.
580
5812000-08-10      Joel Sherrill <joel@OARcorp.com>
582
583        * ChangeLog: New file.
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