source: rtems/cpukit/score/cpu/mips/ChangeLog @ 293c0e30

4.104.114.84.95
Last change on this file since 293c0e30 was 293c0e30, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 15, 2002 at 7:47:36 PM

2002-03-13 Greg Menke <gregory.menke@…>

  • cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
  • rtems/score/cpu.h: Fixed register numbering in comments and made interrupt enable/disable more robust.
  • Property mode set to 100644
File size: 11.5 KB
Line 
12002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
2
3        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
4        * rtems/score/cpu.h: Fixed register numbering in comments and made
5        interrupt enable/disable more robust.
6       
72002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
8        * cpu_asm.S: Added support for the debug exception vector, cleaned
9        up the exception processing & exception return stuff.  Re-added
10        EPC in the task context structure so the gdb stub will know where
11        a thread is executing.  Should've left it there in the first place...
12        * idtcpu.h: Added support for the debug exception vector.
13        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
14        stack frame in an interrupt so context switch code can get the
15        userspace EPC when scheduling.
16        * rtems/score/cpu.h: Re-added EPC to the task context.
17
182002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
19
20        * cpu_asm.S: Fixed exception return address, modified FP context
21        switch so FPU is properly enabled and also doesn't screw up the
22        exception FP handling.
23        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
24        returning from exceptions.
25        * iregdef.h: Added R_TAR to the stack frame so the target address
26        can be saved on a per-exception basis.  The new entry is past the
27        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
28        stuff.
29        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
30        to obtain FPU defines without systax errors generated by the C
31        defintions.
32        * cpu.c: Improved interrupt level saves & restores.
33       
342002-02-08      Joel Sherrill <joel@OARcorp.com>
35
36        * iregdef.h, rtems/score/cpu.h: Reordered register in the
37        exception stack frame to better match gdb's expectations.
38
392001-02-05      Joel Sherrill <joel@OARcorp.com>
40
41        * cpu_asm.S: Enhanced to save/restore more registers on
42        exceptions.
43        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
44        register individually and document when it is saved.
45        * idtcpu.h: Added constants for the coprocessor 1 registers
46        revision and status.
47
482001-02-05      Joel Sherrill <joel@OARcorp.com>
49
50        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
51
522001-02-04      Joel Sherrill <joel@OARcorp.com>
53
54        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
55        in the previous patch that has now been confirmed.
56
572001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
58
59        * cpu.c: Enhancements and fixes for modifying the SR when changing
60        the interrupt level.
61        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
62        managed on a per-task basis, improved handling of interrupt levels,
63        and made deferred FP contexts work on the MIPS.
64        * rtems/score/cpu.h: Modified to support above changes.
65
662002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
67
68        * rtems/Makefile.am: Removed.
69        * rtems/score/Makefile.am: Removed.
70        * configure.ac: Reflect changes above.
71        * Makefile.am: Reflect changes above.
72
732002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
74
75        * asm.h: Remove #include <rtems/score/targopts.h>.
76        Add #include <rtems/score/cpuopts.h>.
77        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
78
79
802001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
81
82        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
83
842001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
85
86        * Makefile.am: Add multilib support.
87
882001-11-28      Joel Sherrill <joel@OARcorp.com>,
89
90        This was tracked as PR91.
91        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
92        is used to specify if the port uses the standard macro for this (FALSE).
93        A TRUE setting indicates the port provides its own implementation.
94
952001-10-12      Joel Sherrill <joel@OARcorp.com>
96
97        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
98        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
99        Wayne Bullaughey <wayne@wmi.com>.
100
1012001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
102
103        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
104        * configure.in: Remove.
105        * configure.ac: New file, generated from configure.in by autoupdate.
106
1072001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
108
109        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
110        * Makefile.am: Use 'PREINSTALL_FILES ='.
111
1122001-07-03      Joel Sherrill <joel@OARcorp.com>
113
114        * cpu.c: Fixed typo.
115
1162000-05-24      Joel Sherrill <joel@OARcorp.com>
117
118        * rtems/score/mips.h: Added constants for MIPS exception numbers.
119        All exceptions should be given low numbers and thus can be installed
120        and processed in a uniform manner.  Variances between various MIPS
121        ISA levels were not accounted for.
122
1232001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
124
125        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
126        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
127
1282001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
129
130        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
131        the context initialization to account for floating point tasks. 
132        * rtems/score/mips.h: Added the routines mips_set_cause(),
133        mips_get_fcr31(), and mips_set_fcr31().
134        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
135
1362001-05-07      Joel Sherrill <joel@OARcorp.com>
137
138        * cpu_asm.S: Merged patches from Gregory Menke
139        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
140        stack usage and include nops in the delay slots.
141
1422001-04-20      Joel Sherrill <joel@OARcorp.com>
143
144        * cpu_asm.S: Added code to save and restore SR and EPC to
145        properly support nested interrupts.  Note that the ISR
146        (not RTEMS) enables interrupts allowing the nesting to occur.
147
1482001-03-14      Joel Sherrill <joel@OARcorp.com>
149
150        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
151        Removed unused variable _CPU_Thread_dispatch_pointer
152        and cleaned numerous comments.
153       
1542001-03-13      Joel Sherrill <joel@OARcorp.com>
155
156        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
157        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
158        Also reimplemented some assembly routines in C further reducing
159        the amount of assembly and increasing maintainability.
160
1612001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
162
163        * Makefile.am, rtems/score/Makefile.am:
164        Apply include_*HEADERS instead of H_FILES.
165
1662001-01-12      Joel Sherrill <joel@OARcorp.com>
167
168        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
169        register constraints from "general" to "register".
170
1712001-01-09      Joel Sherrill <joel@OARcorp.com>
172
173        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
174        to make it easier to conditionalize the code for various ISA levels.
175
1762001-01-08      Joel Sherrill <joel@OARcorp.com>
177
178        * idtcpu.h: Commented out definition of "wait".  It was stupid to
179        use such a common word as a macro.
180        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
181        * rtems/score/mips.h: Added include of <idtcpu.h>.
182        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
183
1842001-01-03      Joel Sherrill <joel@OARcorp.com>
185
186        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
187        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
188
1892000-12-19      Joel Sherrill <joel@OARcorp.com>
190
191        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
192        Previous code resulting in the interrupted immediately returning
193        to the caller of the routine it was inside.
194
1952000-12-19      Joel Sherrill <joel@OARcorp.com>
196
197        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
198        because it has not been allocated yet.
199
2002000-12-13      Joel Sherrill <joel@OARcorp.com>
201
202        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
203        * cpu_asm.S: Removed assembly language to vector ISR handler
204        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
205        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
206        longer a constant -- get the real value from libcpu.
207
2082000-12-13      Joel Sherrill <joel@OARcorp.com>
209
210        * cpu_asm.h: Removed.
211        * Makefile.am: Remove cpu_asm.h.
212        * rtems/score/mips64orion.h: Renamed mips.h.
213        * rtems/score/mips.h: New file, formerly mips64orion.h.
214        Header rewritten.
215        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
216        mips_disable_in_interrupt_mask): New macros.
217        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
218        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
219        few defines that were in <cpu_asm.h>.
220        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
221        MIPS ISA 3 is still in assembly for now.
222        (_CPU_Thread_Idle_body): Rewrote in C.
223        * cpu_asm.S: Rewrote file header.
224        (FRAME,ENDFRAME) now in asm.h.
225        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
226        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
227        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
228        leaves other bits in SR alone on task switch.
229        (mips_enable_interrupts,mips_disable_interrupts,
230        mips_enable_global_interrupts,mips_disable_global_interrupts,
231        disable_int, enable_int): Removed.
232        (mips_get_sr): Rewritten as C macro.
233        (_CPU_Thread_Idle_body): Rewritten in C.
234        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
235        placed in libcpu.
236        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
237        to libcpu/mips/shared/interrupts.
238        (general): Cleaned up comment blocks and #if 0 areas.
239        * idtcpu.h: Made ifdef report an error.
240        * iregdef.h: Removed warning.
241        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
242        number defined by libcpu.
243        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
244        to access SR.
245        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
246        (_CPU_Context_Initialize): Honor ISR level in task initialization.
247        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
248
2492000-12-06      Joel Sherrill <joel@OARcorp.com>
250
251        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
252        context should be 32 not 64 bits.
253
2542000-11-30      Joel Sherrill <joel@OARcorp.com>
255
256        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
257        correct name of _CPU_Context_switch_restore.  Added dummy
258        version of exc_utlb_code() so applications would link.
259
2602000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
261
262        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
263
2642000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
265
266        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
267
2682000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
269
270        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
271        Switch to GNU canonicalization.
272
2732000-10-24      Alan Cudmore <alanc@linuxstart.com> and
274        Joel Sherrill <joel@OARcorp.com>
275
276        * This is a major reworking of the mips64orion port to use
277        gcc predefines as much as possible and a big push to multilib
278        the mips port.  The mips64orion port was copied/renamed to mips
279        to be more like other GNU tools.  Alan did most of the technical
280        work of determining how to map old macro names used by the mips64orion
281        port to standard compiler macro definitions.  Joel did the merge
282        with CVS magic to keep individual file history and did the BSP
283        modifications. Details follow:
284        * Makefile.am: idtmon.h in mips64orion port not present.
285        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
286        * cpu.c: Comments added.
287        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
288        First attempt at exception/interrupt processing for ISA level 1
289        and minus any use of IDT/MON added.
290        * idtcpu.h: Conditionals changed to use gcc predefines.
291        * iregdef.h: Ditto.
292        * cpu_asm.h: No real change.  Merger required commit.
293        * rtems/Makefile.am: Ditto.
294        * rtems/score/Makefile.am: Ditto.
295        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
296        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
297        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
298
2992000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
300
301        * Makefile.am: Include compile.am.
302
3032000-08-10      Joel Sherrill <joel@OARcorp.com>
304
305        * ChangeLog: New file.
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