source: rtems/cpukit/score/cpu/mips/ChangeLog @ 1f24914a

4.104.114.84.95
Last change on this file since 1f24914a was 1f24914a, checked in by Ralf Corsepius <ralf.corsepius@…>, on Feb 4, 2005 at 5:25:15 AM

2005-02-04 Ralf Corsepius <ralf.corsepius@…>

PR 754/rtems

  • rtems/asm.h: New (relocated from .).
  • asm.h: Remove (moved to rtems/asm.h).
  • Makefile.am: Reflect changes above.
  • Property mode set to 100644
File size: 16.1 KB
Line 
12005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
2
3        PR 754/rtems
4        * rtems/asm.h: New (relocated from .).
5        * asm.h: Remove (moved to rtems/asm.h).
6        * Makefile.am: Reflect changes above.
7
82005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
9
10        PR rtems/752
11        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
12        New header guards.
13        * idtcpu.h, iregdef.h: Remove.
14        * Makefile.am: Reflect changes above.
15
162004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
17
18        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
19        New header guards.
20
212005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
22
23        * rtems/score/types.h: Remove signed8, signed16, signed32,
24        unsigned8, unsigned16, unsigned32.
25
262005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
27
28        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
29
302005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
31
32        * rtems/score/types.h: #include <rtems/stdint.h>.
33
342005-01-07      Joel Sherrill <joel@OARcorp.com>
35
36        * rtems/score/cpu.h: Remove warnings.
37
382005-01-07      Ralf Corsepius <ralf.corsepius@freenet.de>
39
40        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
41
422005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
43
44        PR 739
45        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
46        when compiling cpu_asm.S.  Problem was a #define sneaked in in
47        version 1.11, no ill effects would have only affected R4000
48        builds.
49
502005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
51
52        PR 737
53        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
54        slot when compiling cpu_asm.S
55
562005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
57
58        * Makefile.am: Remove build-variant support.
59
602004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
61
62        PR 730
63        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
64        for rtems-4.7.
65
662004-04-09      Joel Sherrill <joel@OARcorp.com>
67
68        PR 605/bsps
69        * cpu.c: Do not use C++ style comments.
70
712004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
72        PR 601
73        * cpu_asm.S: Added __mips==32 support for R4000 processors running
74        32 bit code.  Fixed #define problems that caused fpu code to
75        always be included even when no fpu is present.
76
772004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
78
79        PR 598/bsps
80        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
81        status/control register on context switches. Missing this register
82        was causing intermittent floating point errors.
83
842003-09-04      Joel Sherrill <joel@OARcorp.com>
85
86        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
87        rtems/score/types.h: URL for license changed.
88
892003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
90
91        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
92
932003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
94
95        * configure.ac: Remove AC_CONFIG_AUX_DIR.
96
972002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
98
99        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
100        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
101
1022002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
103
104        * configure.ac: Fix package name.
105
1062002-11-04      Joel Sherrill <joel@OARcorp.com>
107
108        * idtcpu.h: Removed warning.
109
1102002-11-01      Joel Sherrill <joel@OARcorp.com>
111
112        * idtcpu.h: Removed warnings.
113
1142002-10-28      Joel Sherrill <joel@OARcorp.com>
115
116        * idtcpu.h: Removed warning by turning extra token at the end of
117        an endif into a comment.
118
1192002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
120
121        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
122
1232002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
124
125        * .cvsignore: Reformat.
126        Add autom4te*cache.
127        Remove autom4te.cache.
128
1292002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
130
131        * cpu_asm.S: Clarified some comments, removed code that forced
132        SR_IEP on when returning from an interrupt.
133
1342002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
135
136        * configure.ac: Add RTEMS_PROG_CCAS
137
1382002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
139
140        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
141        Add AC_PROG_RANLIB.
142
1432002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
144        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
145        deadlock caused by interrupt arriving while dispatching.
146       
1472002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
148
149        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
150        Use ../../../aclocal.
151
1522001-04-03      Joel Sherrill <joel@OARcorp.com>
153
154        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
155        * rtems/score/mipstypes.h: Removed.
156        * rtems/score/types.h: New file via CVS magic.
157        * Makefile.am, rtems/score/cpu.h: Account for name change.
158
1592002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
160
161        * configure.ac:
162        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
163        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
164        * Makefile.am: Remove AUTOMAKE_OPTIONS.
165
1662002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
167
168        * cpu_asm.S: Now compiles on 4600 and 4650.
169
1702002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
171
172        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
173        * rtems/score/cpu.h: Fixed register numbering in comments and made
174        interrupt enable/disable more robust.
175       
1762002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
177        * cpu_asm.S: Added support for the debug exception vector, cleaned
178        up the exception processing & exception return stuff.  Re-added
179        EPC in the task context structure so the gdb stub will know where
180        a thread is executing.  Should've left it there in the first place...
181        * idtcpu.h: Added support for the debug exception vector.
182        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
183        stack frame in an interrupt so context switch code can get the
184        userspace EPC when scheduling.
185        * rtems/score/cpu.h: Re-added EPC to the task context.
186
1872002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
188
189        * cpu_asm.S: Fixed exception return address, modified FP context
190        switch so FPU is properly enabled and also doesn't screw up the
191        exception FP handling.
192        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
193        returning from exceptions.
194        * iregdef.h: Added R_TAR to the stack frame so the target address
195        can be saved on a per-exception basis.  The new entry is past the
196        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
197        stuff.
198        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
199        to obtain FPU defines without syntax errors generated by the C
200        defintions.
201        * cpu.c: Improved interrupt level saves & restores.
202       
2032002-02-08      Joel Sherrill <joel@OARcorp.com>
204
205        * iregdef.h, rtems/score/cpu.h: Reordered register in the
206        exception stack frame to better match gdb's expectations.
207
2082001-02-05      Joel Sherrill <joel@OARcorp.com>
209
210        * cpu_asm.S: Enhanced to save/restore more registers on
211        exceptions.
212        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
213        register individually and document when it is saved.
214        * idtcpu.h: Added constants for the coprocessor 1 registers
215        revision and status.
216
2172001-02-05      Joel Sherrill <joel@OARcorp.com>
218
219        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
220
2212001-02-04      Joel Sherrill <joel@OARcorp.com>
222
223        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
224        in the previous patch that has now been confirmed.
225
2262001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
227
228        * cpu.c: Enhancements and fixes for modifying the SR when changing
229        the interrupt level.
230        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
231        managed on a per-task basis, improved handling of interrupt levels,
232        and made deferred FP contexts work on the MIPS.
233        * rtems/score/cpu.h: Modified to support above changes.
234
2352002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
236
237        * rtems/Makefile.am: Removed.
238        * rtems/score/Makefile.am: Removed.
239        * configure.ac: Reflect changes above.
240        * Makefile.am: Reflect changes above.
241
2422002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
243
244        * asm.h: Remove #include <rtems/score/targopts.h>.
245        Add #include <rtems/score/cpuopts.h>.
246        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
247
248
2492001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
250
251        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
252
2532001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
254
255        * Makefile.am: Add multilib support.
256
2572001-11-28      Joel Sherrill <joel@OARcorp.com>,
258
259        This was tracked as PR91.
260        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
261        is used to specify if the port uses the standard macro for this (FALSE).
262        A TRUE setting indicates the port provides its own implementation.
263
2642001-10-12      Joel Sherrill <joel@OARcorp.com>
265
266        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
267        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
268        Wayne Bullaughey <wayne@wmi.com>.
269
2702001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
271
272        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
273        * configure.in: Remove.
274        * configure.ac: New file, generated from configure.in by autoupdate.
275
2762001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
277
278        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
279        * Makefile.am: Use 'PREINSTALL_FILES ='.
280
2812001-07-03      Joel Sherrill <joel@OARcorp.com>
282
283        * cpu.c: Fixed typo.
284
2852000-05-24      Joel Sherrill <joel@OARcorp.com>
286
287        * rtems/score/mips.h: Added constants for MIPS exception numbers.
288        All exceptions should be given low numbers and thus can be installed
289        and processed in a uniform manner.  Variances between various MIPS
290        ISA levels were not accounted for.
291
2922001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
293
294        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
295        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
296
2972001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
298
299        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
300        the context initialization to account for floating point tasks. 
301        * rtems/score/mips.h: Added the routines mips_set_cause(),
302        mips_get_fcr31(), and mips_set_fcr31().
303        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
304
3052001-05-07      Joel Sherrill <joel@OARcorp.com>
306
307        * cpu_asm.S: Merged patches from Gregory Menke
308        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
309        stack usage and include nops in the delay slots.
310
3112001-04-20      Joel Sherrill <joel@OARcorp.com>
312
313        * cpu_asm.S: Added code to save and restore SR and EPC to
314        properly support nested interrupts.  Note that the ISR
315        (not RTEMS) enables interrupts allowing the nesting to occur.
316
3172001-03-14      Joel Sherrill <joel@OARcorp.com>
318
319        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
320        Removed unused variable _CPU_Thread_dispatch_pointer
321        and cleaned numerous comments.
322       
3232001-03-13      Joel Sherrill <joel@OARcorp.com>
324
325        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
326        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
327        Also reimplemented some assembly routines in C further reducing
328        the amount of assembly and increasing maintainability.
329
3302001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
331
332        * Makefile.am, rtems/score/Makefile.am:
333        Apply include_*HEADERS instead of H_FILES.
334
3352001-01-12      Joel Sherrill <joel@OARcorp.com>
336
337        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
338        register constraints from "general" to "register".
339
3402001-01-09      Joel Sherrill <joel@OARcorp.com>
341
342        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
343        to make it easier to conditionalize the code for various ISA levels.
344
3452001-01-08      Joel Sherrill <joel@OARcorp.com>
346
347        * idtcpu.h: Commented out definition of "wait".  It was stupid to
348        use such a common word as a macro.
349        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
350        * rtems/score/mips.h: Added include of <idtcpu.h>.
351        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
352
3532001-01-03      Joel Sherrill <joel@OARcorp.com>
354
355        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
356        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
357
3582000-12-19      Joel Sherrill <joel@OARcorp.com>
359
360        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
361        Previous code resulting in the interrupted immediately returning
362        to the caller of the routine it was inside.
363
3642000-12-19      Joel Sherrill <joel@OARcorp.com>
365
366        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
367        because it has not been allocated yet.
368
3692000-12-13      Joel Sherrill <joel@OARcorp.com>
370
371        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
372        * cpu_asm.S: Removed assembly language to vector ISR handler
373        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
374        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
375        longer a constant -- get the real value from libcpu.
376
3772000-12-13      Joel Sherrill <joel@OARcorp.com>
378
379        * cpu_asm.h: Removed.
380        * Makefile.am: Remove cpu_asm.h.
381        * rtems/score/mips64orion.h: Renamed mips.h.
382        * rtems/score/mips.h: New file, formerly mips64orion.h.
383        Header rewritten.
384        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
385        mips_disable_in_interrupt_mask): New macros.
386        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
387        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
388        few defines that were in <cpu_asm.h>.
389        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
390        MIPS ISA 3 is still in assembly for now.
391        (_CPU_Thread_Idle_body): Rewrote in C.
392        * cpu_asm.S: Rewrote file header.
393        (FRAME,ENDFRAME) now in asm.h.
394        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
395        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
396        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
397        leaves other bits in SR alone on task switch.
398        (mips_enable_interrupts,mips_disable_interrupts,
399        mips_enable_global_interrupts,mips_disable_global_interrupts,
400        disable_int, enable_int): Removed.
401        (mips_get_sr): Rewritten as C macro.
402        (_CPU_Thread_Idle_body): Rewritten in C.
403        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
404        placed in libcpu.
405        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
406        to libcpu/mips/shared/interrupts.
407        (general): Cleaned up comment blocks and #if 0 areas.
408        * idtcpu.h: Made ifdef report an error.
409        * iregdef.h: Removed warning.
410        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
411        number defined by libcpu.
412        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
413        to access SR.
414        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
415        (_CPU_Context_Initialize): Honor ISR level in task initialization.
416        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
417
4182000-12-06      Joel Sherrill <joel@OARcorp.com>
419
420        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
421        context should be 32 not 64 bits.
422
4232000-11-30      Joel Sherrill <joel@OARcorp.com>
424
425        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
426        correct name of _CPU_Context_switch_restore.  Added dummy
427        version of exc_utlb_code() so applications would link.
428
4292000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
430
431        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
432
4332000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
434
435        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
436
4372000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
438
439        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
440        Switch to GNU canonicalization.
441
4422000-10-24      Alan Cudmore <alanc@linuxstart.com> and
443        Joel Sherrill <joel@OARcorp.com>
444
445        * This is a major reworking of the mips64orion port to use
446        gcc predefines as much as possible and a big push to multilib
447        the mips port.  The mips64orion port was copied/renamed to mips
448        to be more like other GNU tools.  Alan did most of the technical
449        work of determining how to map old macro names used by the mips64orion
450        port to standard compiler macro definitions.  Joel did the merge
451        with CVS magic to keep individual file history and did the BSP
452        modifications. Details follow:
453        * Makefile.am: idtmon.h in mips64orion port not present.
454        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
455        * cpu.c: Comments added.
456        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
457        First attempt at exception/interrupt processing for ISA level 1
458        and minus any use of IDT/MON added.
459        * idtcpu.h: Conditionals changed to use gcc predefines.
460        * iregdef.h: Ditto.
461        * cpu_asm.h: No real change.  Merger required commit.
462        * rtems/Makefile.am: Ditto.
463        * rtems/score/Makefile.am: Ditto.
464        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
465        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
466        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
467
4682000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
469
470        * Makefile.am: Include compile.am.
471
4722000-08-10      Joel Sherrill <joel@OARcorp.com>
473
474        * ChangeLog: New file.
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