source: rtems/cpukit/score/cpu/mips/ChangeLog @ 176e1ed8

4.104.114.84.95
Last change on this file since 176e1ed8 was 176e1ed8, checked in by Joel Sherrill <joel.sherrill@…>, on Apr 20, 2001 at 1:07:34 PM

2001-04-20 Joel Sherrill <joel@…>

  • cpu_asm.S: Added code to save and restore SR and EPC to properly support nested interrupts. Note that the ISR (not RTEMS) enables interrupts allowing the nesting to occur.
  • Property mode set to 100644
File size: 6.4 KB
Line 
12001-04-20      Joel Sherrill <joel@OARcorp.com>
2
3        * cpu_asm.S: Added code to save and restore SR and EPC to
4        properly support nested interrupts.  Note that the ISR
5        (not RTEMS) enables interrupts allowing the nesting to occur.
6
72001-03-14      Joel Sherrill <joel@OARcorp.com>
8
9        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
10        Removed unused variable _CPU_Thread_dispatch_pointer
11        and cleaned numerous comments.
12       
132001-03-13      Joel Sherrill <joel@OARcorp.com>
14
15        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
16        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
17        Also reimplemented some assembly routines in C further reducing
18        the amount of assembly and increasing maintainability.
19
202001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
21
22        * Makefile.am, rtems/score/Makefile.am:
23        Apply include_*HEADERS instead of H_FILES.
24
252001-01-12      Joel Sherrill <joel@OARcorp.com>
26
27        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
28        register constraints from "general" to "register".
29
302001-01-09      Joel Sherrill <joel@OARcorp.com>
31
32        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
33        to make it easier to conditionalize the code for various ISA levels.
34
352001-01-08      Joel Sherrill <joel@OARcorp.com>
36
37        * idtcpu.h: Commented out definition of "wait".  It was stupid to
38        use such a common word as a macro.
39        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
40        * rtems/score/mips.h: Added include of <idtcpu.h>.
41        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
42
432001-01-03      Joel Sherrill <joel@OARcorp.com>
44
45        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
46        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
47
482000-12-19      Joel Sherrill <joel@OARcorp.com>
49
50        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
51        Previous code resulting in the interrupted immediately returning
52        to the caller of the routine it was inside.
53
542000-12-19      Joel Sherrill <joel@OARcorp.com>
55
56        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
57        because it has not been allocated yet.
58
592000-12-13      Joel Sherrill <joel@OARcorp.com>
60
61        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
62        * cpu_asm.S: Removed assembly language to vector ISR handler
63        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
64        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
65        longer a constant -- get the real value from libcpu.
66
672000-12-13      Joel Sherrill <joel@OARcorp.com>
68
69        * cpu_asm.h: Removed.
70        * Makefile.am: Remove cpu_asm.h.
71        * rtems/score/mips64orion.h: Renamed mips.h.
72        * rtems/score/mips.h: New file, formerly mips64orion.h.
73        Header rewritten.
74        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
75        mips_disable_in_interrupt_mask): New macros.
76        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
77        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
78        few defines that were in <cpu_asm.h>.
79        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
80        MIPS ISA 3 is still in assembly for now.
81        (_CPU_Thread_Idle_body): Rewrote in C.
82        * cpu_asm.S: Rewrote file header.
83        (FRAME,ENDFRAME) now in asm.h.
84        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
85        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
86        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
87        leaves other bits in SR alone on task switch.
88        (mips_enable_interrupts,mips_disable_interrupts,
89        mips_enable_global_interrupts,mips_disable_global_interrupts,
90        disable_int, enable_int): Removed.
91        (mips_get_sr): Rewritten as C macro.
92        (_CPU_Thread_Idle_body): Rewritten in C.
93        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
94        placed in libcpu.
95        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
96        to libcpu/mips/shared/interrupts.
97        (general): Cleaned up comment blocks and #if 0 areas.
98        * idtcpu.h: Made ifdef report an error.
99        * iregdef.h: Removed warning.
100        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
101        number defined by libcpu.
102        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
103        to access SR.
104        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
105        (_CPU_Context_Initialize): Honor ISR level in task initialization.
106        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
107
1082000-12-06      Joel Sherrill <joel@OARcorp.com>
109
110        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
111        context should be 32 not 64 bits.
112
1132000-11-30      Joel Sherrill <joel@OARcorp.com>
114
115        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
116        correct name of _CPU_Context_switch_restore.  Added dummy
117        version of exc_utlb_code() so applications would link.
118
1192000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
120
121        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
122
1232000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
124
125        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
126
1272000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
128
129        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
130        Switch to GNU canonicalization.
131
1322000-10-24      Alan Cudmore <alanc@linuxstart.com> and
133        Joel Sherrill <joel@OARcorp.com>
134
135        * This is a major reworking of the mips64orion port to use
136        gcc predefines as much as possible and a big push to multilib
137        the mips port.  The mips64orion port was copied/renamed to mips
138        to be more like other GNU tools.  Alan did most of the technical
139        work of determining how to map old macro names used by the mips64orion
140        port to standard compiler macro definitions.  Joel did the merge
141        with CVS magic to keep individual file history and did the BSP
142        modifications. Details follow:
143        * Makefile.am: idtmon.h in mips64orion port not present.
144        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
145        * cpu.c: Comments added.
146        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
147        First attempt at exception/interrupt processing for ISA level 1
148        and minus any use of IDT/MON added.
149        * idtcpu.h: Conditionals changed to use gcc predefines.
150        * iregdef.h: Ditto.
151        * cpu_asm.h: No real change.  Merger required commit.
152        * rtems/Makefile.am: Ditto.
153        * rtems/score/Makefile.am: Ditto.
154        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
155        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
156        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
157
1582000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
159
160        * Makefile.am: Include compile.am.
161
1622000-08-10      Joel Sherrill <joel@OARcorp.com>
163
164        * ChangeLog: New file.
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