source: rtems/cpukit/score/cpu/mips/ChangeLog @ 16ad7ea

4.104.114.84.95
Last change on this file since 16ad7ea was 16ad7ea, checked in by Joel Sherrill <joel.sherrill@…>, on 01/09/01 at 16:48:26

2001-01-09 Joel Sherrill <joel@…>

  • cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants to make it easier to conditionalize the code for various ISA levels.
  • Property mode set to 100644
File size: 5.4 KB
Line 
12001-01-09      Joel Sherrill <joel@OARcorp.com>
2
3        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
4        to make it easier to conditionalize the code for various ISA levels.
5
62001-01-08      Joel Sherrill <joel@OARcorp.com>
7
8        * idtcpu.h: Commented out definition of "wait".  It was stupid to
9        use such a common word as a macro.
10        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
11        * rtems/score/mips.h: Added include of <idtcpu.h>.
12        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
13
142001-01-03      Joel Sherrill <joel@OARcorp.com>
15
16        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
17        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
18
192000-12-19      Joel Sherrill <joel@OARcorp.com>
20
21        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
22        Previous code resulting in the interrupted immediately returning
23        to the caller of the routine it was inside.
24
252000-12-19      Joel Sherrill <joel@OARcorp.com>
26
27        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
28        because it has not been allocated yet.
29
302000-12-13      Joel Sherrill <joel@OARcorp.com>
31
32        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
33        * cpu_asm.S: Removed assembly language to vector ISR handler
34        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
35        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
36        longer a constant -- get the real value from libcpu.
37
382000-12-13      Joel Sherrill <joel@OARcorp.com>
39
40        * cpu_asm.h: Removed.
41        * Makefile.am: Remove cpu_asm.h.
42        * rtems/score/mips64orion.h: Renamed mips.h.
43        * rtems/score/mips.h: New file, formerly mips64orion.h.
44        Header rewritten.
45        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
46        mips_disable_in_interrupt_mask): New macros.
47        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
48        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
49        few defines that were in <cpu_asm.h>.
50        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
51        MIPS ISA 3 is still in assembly for now.
52        (_CPU_Thread_Idle_body): Rewrote in C.
53        * cpu_asm.S: Rewrote file header.
54        (FRAME,ENDFRAME) now in asm.h.
55        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
56        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
57        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
58        leaves other bits in SR alone on task switch.
59        (mips_enable_interrupts,mips_disable_interrupts,
60        mips_enable_global_interrupts,mips_disable_global_interrupts,
61        disable_int, enable_int): Removed.
62        (mips_get_sr): Rewritten as C macro.
63        (_CPU_Thread_Idle_body): Rewritten in C.
64        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
65        placed in libcpu.
66        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
67        to libcpu/mips/shared/interrupts.
68        (general): Cleaned up comment blocks and #if 0 areas.
69        * idtcpu.h: Made ifdef report an error.
70        * iregdef.h: Removed warning.
71        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
72        number defined by libcpu.
73        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
74        to access SR.
75        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
76        (_CPU_Context_Initialize): Honor ISR level in task initialization.
77        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
78
792000-12-06      Joel Sherrill <joel@OARcorp.com>
80
81        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
82        context should be 32 not 64 bits.
83
842000-11-30      Joel Sherrill <joel@OARcorp.com>
85
86        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
87        correct name of _CPU_Context_switch_restore.  Added dummy
88        version of exc_utlb_code() so applications would link.
89
902000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
91
92        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
93
942000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
95
96        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
97
982000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
99
100        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
101        Switch to GNU canonicalization.
102
1032000-10-24      Alan Cudmore <alanc@linuxstart.com> and
104        Joel Sherrill <joel@OARcorp.com>
105
106        * This is a major reworking of the mips64orion port to use
107        gcc predefines as much as possible and a big push to multilib
108        the mips port.  The mips64orion port was copied/renamed to mips
109        to be more like other GNU tools.  Alan did most of the technical
110        work of determining how to map old macro names used by the mips64orion
111        port to standard compiler macro definitions.  Joel did the merge
112        with CVS magic to keep individual file history and did the BSP
113        modifications. Details follow:
114        * Makefile.am: idtmon.h in mips64orion port not present.
115        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
116        * cpu.c: Comments added.
117        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
118        First attempt at exception/interrupt processing for ISA level 1
119        and minus any use of IDT/MON added.
120        * idtcpu.h: Conditionals changed to use gcc predefines.
121        * iregdef.h: Ditto.
122        * cpu_asm.h: No real change.  Merger required commit.
123        * rtems/Makefile.am: Ditto.
124        * rtems/score/Makefile.am: Ditto.
125        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
126        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
127        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
128
1292000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
130
131        * Makefile.am: Include compile.am.
132
1332000-08-10      Joel Sherrill <joel@OARcorp.com>
134
135        * ChangeLog: New file.
Note: See TracBrowser for help on using the repository browser.