source: rtems/cpukit/score/cpu/mips/ChangeLog @ 11f2bf59

4.104.114.84.95
Last change on this file since 11f2bf59 was 8b56aa3, checked in by Ralf Corsepius <ralf.corsepius@…>, on 05/09/07 at 15:28:52

2007-05-09 Ralf Corsépius <ralf.corsepius@…>

  • rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
  • Property mode set to 100644
File size: 18.2 KB
Line 
12007-05-09      Ralf Corsépius <ralf.corsepius@rtems.org>
2
3        * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
4
52007-04-17      Ralf Corsépius <ralf.corsepius@rtems.org>
6
7        * rtems/score/cpu.h:
8          Use Context_Control_fp* instead of void* for fp_contexts.
9          Eliminate evil casts.
10
112006-11-17      Ralf Corsépius <ralf.corsepius@rtems.org>
12
13        * rtems/score/types.h: Remove unsigned64, signed64.
14
152006-06-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
16
17        * cpu.c: Added __mips==32 to fix build problems on those targets
18        caused by the Bruce Robinson.
19
202006-06-08 Bruce Robinson <brucer@pmccorp.com>
21
22        * cpu.c: Add int64 types for __mips==3 cpus, incorporate
23           mips_interrupt_mask() into mask computations
24        * cpu_asm.S: Add int64 register save/restores for __mips==3 cpus.  Adjustment
25           of mips1 vs mips3 macros.
26        * cpu.h: Add int64 types for __mips==3 cpus.
27       
282006-03-17      Ralf Corsepius <ralf.corsepius@rtems.org>
29
30        * cpu.c (_CPU_Initialize): Add fpu initialization.
31        * rtems/score/cpu.h: Setup CPU_*_ENDIAN from GCC's__MIPS{EL|EB}__.
32        (Partial merger of submission by Bruce Robinson <brucer@pmccorp.com>).
33
342006-01-16      Joel Sherrill <joel@OARcorp.com>
35
36        * rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
37        As a side-effect, grammar and spelling errors were corrected, spacing
38        errors were address, and some variable names were improved.
39
402005-11-18      Joel Sherrill <joel@OARcorp.com>
41
42        * rtems/score/cpu.h: Eliminate use of unsigned32.
43
442005-11-08      Ralf Corsepius <ralf.corsepius@rtems.org>
45
46        * rtems/score/types.h: Eliminate unsigned16, unsigned32.
47
482005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
49
50        * rtems/asm.h: Remove private version of CONCAT macros.
51        Include <rtems/concat.h> instead.
52
532005-04-26      Joel Sherrill <joel@OARcorp.com>
54
55        * rtems/asm.h: Eliminate warnings.
56
572005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
58
59        * Makefile.am: Split out preinstallation rules.
60        * preinstall.am: New (Split out from Makefile.am).
61
622005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
63
64        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
65        Header guards cleanup.
66
672005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
68
69        PR 754/rtems
70        * rtems/asm.h: New (relocated from .).
71        * asm.h: Remove (moved to rtems/asm.h).
72        * Makefile.am: Reflect changes above.
73
742005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
75
76        PR rtems/752
77        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
78        New header guards.
79        * idtcpu.h, iregdef.h: Remove.
80        * Makefile.am: Reflect changes above.
81
822004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
83
84        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
85        New header guards.
86
872005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
88
89        * rtems/score/types.h: Remove signed8, signed16, signed32,
90        unsigned8, unsigned16, unsigned32.
91
922005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
93
94        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
95
962005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
97
98        * rtems/score/types.h: #include <rtems/stdint.h>.
99
1002005-01-07      Joel Sherrill <joel@OARcorp.com>
101
102        * rtems/score/cpu.h: Remove warnings.
103
1042005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
105
106        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
107
1082005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
109
110        PR 739
111        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
112        when compiling cpu_asm.S.  Problem was a #define sneaked in in
113        version 1.11, no ill effects would have only affected R4000
114        builds.
115
1162005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
117
118        PR 737
119        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
120        slot when compiling cpu_asm.S
121
1222005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
123
124        * Makefile.am: Remove build-variant support.
125
1262004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
127
128        PR 730
129        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
130        for rtems-4.7.
131
1322004-04-09      Joel Sherrill <joel@OARcorp.com>
133
134        PR 605/bsps
135        * cpu.c: Do not use C++ style comments.
136
1372004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
138        PR 601
139        * cpu_asm.S: Added __mips==32 support for R4000 processors running
140        32 bit code.  Fixed #define problems that caused fpu code to
141        always be included even when no fpu is present.
142
1432004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
144
145        PR 598/bsps
146        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
147        status/control register on context switches. Missing this register
148        was causing intermittent floating point errors.
149
1502003-09-04      Joel Sherrill <joel@OARcorp.com>
151
152        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
153        rtems/score/types.h: URL for license changed.
154
1552003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
156
157        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
158
1592003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
160
161        * configure.ac: Remove AC_CONFIG_AUX_DIR.
162
1632002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
164
165        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
166        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
167
1682002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
169
170        * configure.ac: Fix package name.
171
1722002-11-04      Joel Sherrill <joel@OARcorp.com>
173
174        * idtcpu.h: Removed warning.
175
1762002-11-01      Joel Sherrill <joel@OARcorp.com>
177
178        * idtcpu.h: Removed warnings.
179
1802002-10-28      Joel Sherrill <joel@OARcorp.com>
181
182        * idtcpu.h: Removed warning by turning extra token at the end of
183        an endif into a comment.
184
1852002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
186
187        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
188
1892002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
190
191        * .cvsignore: Reformat.
192        Add autom4te*cache.
193        Remove autom4te.cache.
194
1952002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
196
197        * cpu_asm.S: Clarified some comments, removed code that forced
198        SR_IEP on when returning from an interrupt.
199
2002002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
201
202        * configure.ac: Add RTEMS_PROG_CCAS
203
2042002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
205
206        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
207        Add AC_PROG_RANLIB.
208
2092002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
210        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
211        deadlock caused by interrupt arriving while dispatching.
212       
2132002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
214
215        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
216        Use ../../../aclocal.
217
2182001-04-03      Joel Sherrill <joel@OARcorp.com>
219
220        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
221        * rtems/score/mipstypes.h: Removed.
222        * rtems/score/types.h: New file via CVS magic.
223        * Makefile.am, rtems/score/cpu.h: Account for name change.
224
2252002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
226
227        * configure.ac:
228        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
229        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
230        * Makefile.am: Remove AUTOMAKE_OPTIONS.
231
2322002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
233
234        * cpu_asm.S: Now compiles on 4600 and 4650.
235
2362002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
237
238        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
239        * rtems/score/cpu.h: Fixed register numbering in comments and made
240        interrupt enable/disable more robust.
241       
2422002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
243        * cpu_asm.S: Added support for the debug exception vector, cleaned
244        up the exception processing & exception return stuff.  Re-added
245        EPC in the task context structure so the gdb stub will know where
246        a thread is executing.  Should've left it there in the first place...
247        * idtcpu.h: Added support for the debug exception vector.
248        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
249        stack frame in an interrupt so context switch code can get the
250        userspace EPC when scheduling.
251        * rtems/score/cpu.h: Re-added EPC to the task context.
252
2532002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
254
255        * cpu_asm.S: Fixed exception return address, modified FP context
256        switch so FPU is properly enabled and also doesn't screw up the
257        exception FP handling.
258        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
259        returning from exceptions.
260        * iregdef.h: Added R_TAR to the stack frame so the target address
261        can be saved on a per-exception basis.  The new entry is past the
262        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
263        stuff.
264        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
265        to obtain FPU defines without syntax errors generated by the C
266        defintions.
267        * cpu.c: Improved interrupt level saves & restores.
268       
2692002-02-08      Joel Sherrill <joel@OARcorp.com>
270
271        * iregdef.h, rtems/score/cpu.h: Reordered register in the
272        exception stack frame to better match gdb's expectations.
273
2742001-02-05      Joel Sherrill <joel@OARcorp.com>
275
276        * cpu_asm.S: Enhanced to save/restore more registers on
277        exceptions.
278        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
279        register individually and document when it is saved.
280        * idtcpu.h: Added constants for the coprocessor 1 registers
281        revision and status.
282
2832001-02-05      Joel Sherrill <joel@OARcorp.com>
284
285        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
286
2872001-02-04      Joel Sherrill <joel@OARcorp.com>
288
289        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
290        in the previous patch that has now been confirmed.
291
2922001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
293
294        * cpu.c: Enhancements and fixes for modifying the SR when changing
295        the interrupt level.
296        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
297        managed on a per-task basis, improved handling of interrupt levels,
298        and made deferred FP contexts work on the MIPS.
299        * rtems/score/cpu.h: Modified to support above changes.
300
3012002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
302
303        * rtems/Makefile.am: Removed.
304        * rtems/score/Makefile.am: Removed.
305        * configure.ac: Reflect changes above.
306        * Makefile.am: Reflect changes above.
307
3082002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
309
310        * asm.h: Remove #include <rtems/score/targopts.h>.
311        Add #include <rtems/score/cpuopts.h>.
312        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
313
314
3152001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
316
317        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
318
3192001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
320
321        * Makefile.am: Add multilib support.
322
3232001-11-28      Joel Sherrill <joel@OARcorp.com>,
324
325        This was tracked as PR91.
326        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
327        is used to specify if the port uses the standard macro for this (FALSE).
328        A TRUE setting indicates the port provides its own implementation.
329
3302001-10-12      Joel Sherrill <joel@OARcorp.com>
331
332        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
333        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
334        Wayne Bullaughey <wayne@wmi.com>.
335
3362001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
337
338        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
339        * configure.in: Remove.
340        * configure.ac: New file, generated from configure.in by autoupdate.
341
3422001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
343
344        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
345        * Makefile.am: Use 'PREINSTALL_FILES ='.
346
3472001-07-03      Joel Sherrill <joel@OARcorp.com>
348
349        * cpu.c: Fixed typo.
350
3512000-05-24      Joel Sherrill <joel@OARcorp.com>
352
353        * rtems/score/mips.h: Added constants for MIPS exception numbers.
354        All exceptions should be given low numbers and thus can be installed
355        and processed in a uniform manner.  Variances between various MIPS
356        ISA levels were not accounted for.
357
3582001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
359
360        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
361        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
362
3632001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
364
365        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
366        the context initialization to account for floating point tasks. 
367        * rtems/score/mips.h: Added the routines mips_set_cause(),
368        mips_get_fcr31(), and mips_set_fcr31().
369        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
370
3712001-05-07      Joel Sherrill <joel@OARcorp.com>
372
373        * cpu_asm.S: Merged patches from Gregory Menke
374        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
375        stack usage and include nops in the delay slots.
376
3772001-04-20      Joel Sherrill <joel@OARcorp.com>
378
379        * cpu_asm.S: Added code to save and restore SR and EPC to
380        properly support nested interrupts.  Note that the ISR
381        (not RTEMS) enables interrupts allowing the nesting to occur.
382
3832001-03-14      Joel Sherrill <joel@OARcorp.com>
384
385        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
386        Removed unused variable _CPU_Thread_dispatch_pointer
387        and cleaned numerous comments.
388       
3892001-03-13      Joel Sherrill <joel@OARcorp.com>
390
391        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
392        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
393        Also reimplemented some assembly routines in C further reducing
394        the amount of assembly and increasing maintainability.
395
3962001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
397
398        * Makefile.am, rtems/score/Makefile.am:
399        Apply include_*HEADERS instead of H_FILES.
400
4012001-01-12      Joel Sherrill <joel@OARcorp.com>
402
403        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
404        register constraints from "general" to "register".
405
4062001-01-09      Joel Sherrill <joel@OARcorp.com>
407
408        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
409        to make it easier to conditionalize the code for various ISA levels.
410
4112001-01-08      Joel Sherrill <joel@OARcorp.com>
412
413        * idtcpu.h: Commented out definition of "wait".  It was stupid to
414        use such a common word as a macro.
415        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
416        * rtems/score/mips.h: Added include of <idtcpu.h>.
417        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
418
4192001-01-03      Joel Sherrill <joel@OARcorp.com>
420
421        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
422        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
423
4242000-12-19      Joel Sherrill <joel@OARcorp.com>
425
426        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
427        Previous code resulting in the interrupted immediately returning
428        to the caller of the routine it was inside.
429
4302000-12-19      Joel Sherrill <joel@OARcorp.com>
431
432        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
433        because it has not been allocated yet.
434
4352000-12-13      Joel Sherrill <joel@OARcorp.com>
436
437        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
438        * cpu_asm.S: Removed assembly language to vector ISR handler
439        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
440        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
441        longer a constant -- get the real value from libcpu.
442
4432000-12-13      Joel Sherrill <joel@OARcorp.com>
444
445        * cpu_asm.h: Removed.
446        * Makefile.am: Remove cpu_asm.h.
447        * rtems/score/mips64orion.h: Renamed mips.h.
448        * rtems/score/mips.h: New file, formerly mips64orion.h.
449        Header rewritten.
450        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
451        mips_disable_in_interrupt_mask): New macros.
452        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
453        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
454        few defines that were in <cpu_asm.h>.
455        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
456        MIPS ISA 3 is still in assembly for now.
457        (_CPU_Thread_Idle_body): Rewrote in C.
458        * cpu_asm.S: Rewrote file header.
459        (FRAME,ENDFRAME) now in asm.h.
460        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
461        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
462        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
463        leaves other bits in SR alone on task switch.
464        (mips_enable_interrupts,mips_disable_interrupts,
465        mips_enable_global_interrupts,mips_disable_global_interrupts,
466        disable_int, enable_int): Removed.
467        (mips_get_sr): Rewritten as C macro.
468        (_CPU_Thread_Idle_body): Rewritten in C.
469        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
470        placed in libcpu.
471        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
472        to libcpu/mips/shared/interrupts.
473        (general): Cleaned up comment blocks and #if 0 areas.
474        * idtcpu.h: Made ifdef report an error.
475        * iregdef.h: Removed warning.
476        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
477        number defined by libcpu.
478        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
479        to access SR.
480        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
481        (_CPU_Context_Initialize): Honor ISR level in task initialization.
482        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
483
4842000-12-06      Joel Sherrill <joel@OARcorp.com>
485
486        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
487        context should be 32 not 64 bits.
488
4892000-11-30      Joel Sherrill <joel@OARcorp.com>
490
491        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
492        correct name of _CPU_Context_switch_restore.  Added dummy
493        version of exc_utlb_code() so applications would link.
494
4952000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
496
497        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
498
4992000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
500
501        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
502
5032000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
504
505        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
506        Switch to GNU canonicalization.
507
5082000-10-24      Alan Cudmore <alanc@linuxstart.com> and
509        Joel Sherrill <joel@OARcorp.com>
510
511        * This is a major reworking of the mips64orion port to use
512        gcc predefines as much as possible and a big push to multilib
513        the mips port.  The mips64orion port was copied/renamed to mips
514        to be more like other GNU tools.  Alan did most of the technical
515        work of determining how to map old macro names used by the mips64orion
516        port to standard compiler macro definitions.  Joel did the merge
517        with CVS magic to keep individual file history and did the BSP
518        modifications. Details follow:
519        * Makefile.am: idtmon.h in mips64orion port not present.
520        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
521        * cpu.c: Comments added.
522        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
523        First attempt at exception/interrupt processing for ISA level 1
524        and minus any use of IDT/MON added.
525        * idtcpu.h: Conditionals changed to use gcc predefines.
526        * iregdef.h: Ditto.
527        * cpu_asm.h: No real change.  Merger required commit.
528        * rtems/Makefile.am: Ditto.
529        * rtems/score/Makefile.am: Ditto.
530        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
531        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
532        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
533
5342000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
535
536        * Makefile.am: Include compile.am.
537
5382000-08-10      Joel Sherrill <joel@OARcorp.com>
539
540        * ChangeLog: New file.
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