source: rtems/cpukit/score/cpu/mips/ChangeLog @ 0c0181d

4.115
Last change on this file since 0c0181d was 0c0181d, checked in by Jennifer Averett <jennifer.averett@…>, on 04/04/12 at 13:39:46

PR 1993 - Convert MIPS to PIC IRQ model
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12012-03-07      Jennifer Averett <Jennifer.Averett@OARcorp.com>
2
3        * rtems/score/cpu.h: In order to handle a issue in the
4        compilation of printk all tasks should be defined as
5        floating point for the MIPS processor.
6
72012-02-23      Jennifer Averett <Jennifer.Averett@OARcorp.com>
8
9        PR 1993/bsps
10        * cpu.c, rtems/score/cpu.h:
11        Mips conversion to PIC IRQ model.
12
132011-12-09      Jennifer Averett
14
15        * cpu.c: Correct typo.
16
172011-09-27      Sebastian Huber <sebastian.huber@embedded-brains.de>
18
19        PR 1914/cpukit
20        * rtems/score/cpu.h: Select timestamp implementation.
21
222011-07-24      Joel Sherrill <joel.sherrill@oarcorp.com>
23
24        * cpu.c: Remove /*PAGE markers which were interpreted by a long dead
25        print script.
26
272011-05-17      Ralf Corsépius <ralf.corsepius@rtems.org>
28
29        * Makefile.am: Reformat.
30
312011-02-11      Ralf Corsépius <ralf.corsepius@rtems.org>
32
33        * cpu.c, rtems/score/mips.h:
34        Use "__asm__" instead of "asm" for improved c99-compliance.
35
362011-01-04      Joel Sherrill <joel.sherrill@oarcorp.com>
37
38        * cpu_asm.S: _Thread_Executing was not used.
39
402010-10-21      Joel Sherrill <joel.sherrill@oarcorp.com>
41
42        * rtems/score/cpu.h: Add RTEMS_COMPILER_NO_RETURN_ATTRIBUTE to
43        _CPU_Context_restore() because it does not return. Telling GCC this
44        avoids generation of dead code.
45
462010-07-30      Gedare Bloom <giddyup44@yahoo.com>
47
48        PR 1599/cpukit
49        * cpu_asm.S: Rename _Context_Switch_necessary to
50        _Thread_Dispatch_necessary to more properly reflect the intent.
51
522010-07-29      Gedare Bloom <giddyup44@yahoo.com>
53
54        PR 1635/cpukit
55        * rtems/score/cpu.h, rtems/score/types.h: Refactoring of priority
56        handling, to isolate the bitmap implementation of priorities in the
57        supercore so that priority management is a little more modular. This
58        change is in anticipation of scheduler implementations that can
59        select how they manage tracking priority levels / finding the highest
60        priority ready task. Note that most of the changes here are simple
61        renaming, to clarify the use of the bitmap-based priority management.
62
632010-07-16      Sebastian Huber <sebastian.huber@embedded-brains.de>
64
65        * rtems/score/cpu.h: Include <rtems/score/types.h> first.
66        * rtems/score/types.h: Use <rtems/score/basedefs.h> header file.
67
682010-07-01      Joel Sherrill <joel.sherrill@oarcorp.com>
69
70        * rtems/asm.h, rtems/score/cpu.h: cpu.h defines were not available to
71        assembly programs. This resulted in percpu.h (when included from
72        assembly) not being able to detect that the MIPS does not have a
73        dedicated software managed interrupt stack.
74
752010-06-28      Joel Sherrill <joel.sherrill@oarcorp.com>
76
77        PR 1573/cpukit
78        * cpu_asm.S, rtems/score/cpu.h: Add a per cpu data structure which
79        contains the information required by RTEMS for each CPU core. This
80        encapsulates information such as thread executing, heir, idle and
81        dispatch needed.
82
832010-06-16      Joel Sherrill <joel.sherrill@oarcorp.com>
84
85        * cpu_asm.S: Remove trailing tabs.
86
872010-04-25      Joel Sherrill <joel.sherrilL@OARcorp.com>
88
89        * cpu.c, rtems/score/cpu.h: Move _CPU_Context_Initialize() to cpu.c so
90        it is easier to make warning free.
91
922010-04-25      Joel Sherrill <joel.sherrilL@OARcorp.com>
93
94        * rtems/score/cpu.h: Remove warning in _CPU_Context_Initialize.
95
962010-03-27      Joel Sherrill <joel.sherrill@oarcorp.com>
97
98        * cpu.c, cpu_asm.S: Add include of config.h
99
1002009-03-12      Joel Sherrill <joel.sherrill@OARcorp.com>
101
102        PR 1385/cpukit
103        * cpu_asm.S: When the type rtems_boolean was switched to the C99 bool,
104        the size changed from 4 bytes to 1 byte. The interrupt dispatching
105        code accesses two boolean variables for scheduling purposes and the
106        assembly implementations of this code did not get updated.
107
1082009-02-12      Joel Sherrill <joel.sherrill@oarcorp.com>
109
110        * cpu.c, rtems/score/cpu.h: Change prototype of IDLE thread to
111        consistently return void * and take a uintptr_t argument.
112
1132009-02-11      Joel Sherrill <joel.sherrill@oarcorp.com>
114
115        * cpu.c, rtems/score/cpu.h: Eliminate _CPU_Thread_dispatch_pointer and
116        passing address of _Thread_Dispatch to _CPU_Initialize. Clean up
117        comments.
118
1192008-09-11      Ralf Corsépius <ralf.corsepius@rtems.org>
120
121        * rtems/score/types.h: Do not define boolean, single_precision,
122        double_precision unless RTEMS_DEPRECATED_TYPES is given.
123
1242008-08-21      Ralf Corsépius <ralf.corsepius@rtems.org>
125
126        * rtems/score/types.h: Include stdbool.h.
127        Use bool as base-type for boolean.
128
1292008-07-31      Joel Sherrill <joel.sherrill@OARcorp.com>
130
131        * cpu.c, rtems/score/cpu.h: Correct prototype of Idle threads.
132
1332008-06-05      Joel Sherrill <joel.sherrill@OARcorp.com>
134
135        * rtems/score/cpu.h: Add CPU_SIMPLE_VECTORED_INTERRUPTS porting
136        parameter to indicate that the port uses the Simple Vectored
137        Interrupt model or the Programmable Interrupt Controller Model. The
138        PIC model is implemented primarily in the BSP and it is responsible
139        for all memory allocation.
140
1412008-06-04      Joel Sherrill <joel.sherrill@OARcorp.com>
142
143        * rtems/score/cpu.h: Use a constant for CPU_STACK_MINIMUM_SIZE so it
144        can be used in cpp expressions. Using sizeof() requires actually
145        compiling the file.
146
1472007-12-17      Joel Sherrill <joel.sherrill@oarcorp.com>
148
149        * rtems/score/cpu.h: Add _CPU_Context_Get_SP() for stack check utility.
150
1512007-12-04      Joel Sherrill <joel.sherrill@OARcorp.com>
152
153        * cpu.c, rtems/score/cpu.h: Move interrupt_stack_size field from CPU
154        Table to Configuration Table. Eliminate CPU Table from all ports.
155        Delete references to CPU Table in all forms.
156
1572007-12-03      Joel Sherrill <joel.sherrill@OARcorp.com>
158
159        * rtems/score/cpu.h: Moved most of the remaining CPU Table fields to
160        the Configuration Table. This included pretasking_hook,
161        predriver_hook, postdriver_hook, idle_task, do_zero_of_workspace,
162        extra_mpci_receive_server_stack, stack_allocate_hook, and
163        stack_free_hook. As a side-effect of this effort some multiprocessing
164        code was made conditional and some style clean up occurred.
165
1662007-11-26      Joel Sherrill <joel.sherrill@oarcorp.com>
167
168        * rtems/score/cpu.h: Eliminate the clicks_per_microsecond field in the
169        MIPS CPU Table and define another mechanism for drivers to obtain
170        this information.
171
1722007-08-04      Ralf Corsépius <ralf.corsepius@rtems.org>
173
174        * rtems/score/cpu.h: Use uintptr_t instead of uint32_t.
175
1762007-05-09      Ralf Corsépius <ralf.corsepius@rtems.org>
177
178        * rtems/score/cpu.h: Remove CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES.
179
1802007-04-17      Ralf Corsépius <ralf.corsepius@rtems.org>
181
182        * rtems/score/cpu.h:
183          Use Context_Control_fp* instead of void* for fp_contexts.
184          Eliminate evil casts.
185
1862006-11-17      Ralf Corsépius <ralf.corsepius@rtems.org>
187
188        * rtems/score/types.h: Remove unsigned64, signed64.
189
1902006-06-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
191
192        * cpu.c: Added __mips==32 to fix build problems on those targets
193        caused by the Bruce Robinson.
194
1952006-06-08 Bruce Robinson <brucer@pmccorp.com>
196
197        * cpu.c: Add int64 types for __mips==3 cpus, incorporate
198           mips_interrupt_mask() into mask computations
199        * cpu_asm.S: Add int64 register save/restores for __mips==3 cpus.  Adjustment
200           of mips1 vs mips3 macros.
201        * cpu.h: Add int64 types for __mips==3 cpus.
202       
2032006-03-17      Ralf Corsepius <ralf.corsepius@rtems.org>
204
205        * cpu.c (_CPU_Initialize): Add fpu initialization.
206        * rtems/score/cpu.h: Setup CPU_*_ENDIAN from GCC's__MIPS{EL|EB}__.
207        (Partial merger of submission by Bruce Robinson <brucer@pmccorp.com>).
208
2092006-01-16      Joel Sherrill <joel@OARcorp.com>
210
211        * rtems/score/cpu.h: Part of a large patch to improve Doxygen output.
212        As a side-effect, grammar and spelling errors were corrected, spacing
213        errors were address, and some variable names were improved.
214
2152005-11-18      Joel Sherrill <joel@OARcorp.com>
216
217        * rtems/score/cpu.h: Eliminate use of unsigned32.
218
2192005-11-08      Ralf Corsepius <ralf.corsepius@rtems.org>
220
221        * rtems/score/types.h: Eliminate unsigned16, unsigned32.
222
2232005-10-27      Ralf Corsepius <ralf.corsepius@rtems.org>
224
225        * rtems/asm.h: Remove private version of CONCAT macros.
226        Include <rtems/concat.h> instead.
227
2282005-04-26      Joel Sherrill <joel@OARcorp.com>
229
230        * rtems/asm.h: Eliminate warnings.
231
2322005-02-08      Ralf Corsepius <ralf.corsepius@rtems.org>
233
234        * Makefile.am: Split out preinstallation rules.
235        * preinstall.am: New (Split out from Makefile.am).
236
2372005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
238
239        * rtems/mips/idtcpu.h, rtems/mips/iregdef.h, rtems/score/mips.h:
240        Header guards cleanup.
241
2422005-02-04      Ralf Corsepius <ralf.corsepius@rtems.org>
243
244        PR 754/rtems
245        * rtems/asm.h: New (relocated from .).
246        * asm.h: Remove (moved to rtems/asm.h).
247        * Makefile.am: Reflect changes above.
248
2492005-02-01      Ralf Corsepius <ralf.corsepius@rtems.org>
250
251        PR rtems/752
252        * rtems/mips/idtcpu.h rtems/mips/iregdef.h: New (relocated from .).
253        New header guards.
254        * idtcpu.h, iregdef.h: Remove.
255        * Makefile.am: Reflect changes above.
256
2572004-01-28      Ralf Corsepius <ralf.corsepiu@rtems.org>
258
259        * asm.h, rtems/score/cpu.h, rtems/score/mips.h, rtems/score/types.h:
260        New header guards.
261
2622005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
263
264        * rtems/score/types.h: Remove signed8, signed16, signed32,
265        unsigned8, unsigned16, unsigned32.
266
2672005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
268
269        * rtems/score/cpu.h: *_swap_u32( uint32_t ).
270
2712005-01-24      Ralf Corsepius <ralf.corsepius@rtems.org>
272
273        * rtems/score/types.h: #include <rtems/stdint.h>.
274
2752005-01-07      Joel Sherrill <joel@OARcorp.com>
276
277        * rtems/score/cpu.h: Remove warnings.
278
2792005-01-07      Ralf Corsepius <ralf.corsepius@rtems.org>
280
281        * Makefile.am: Eliminate CFLAGS_OPTIMIZE_V.
282
2832005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
284
285        PR 739
286        * iregdef.h: Fixes gcc warning about redundant definition of R_SZ
287        when compiling cpu_asm.S.  Problem was a #define sneaked in in
288        version 1.11, no ill effects would have only affected R4000
289        builds.
290
2912005-01-03      Greg Menke <gregory.menke@gsfc.nasa.gov>
292
293        PR 737
294        * cpu_asm.S: Fixes gcc warning about instructions in branch delay
295        slot when compiling cpu_asm.S
296
2972005-01-01      Ralf Corsepius <ralf.corsepius@rtems.org>
298
299        * Makefile.am: Remove build-variant support.
300
3012004-12-02      Greg Menke <gregory.menke@gsfc.nasa.gov>
302
303        PR 730
304        * cpu_asm.S: Collected PR 601 changes for commit to cvshead
305        for rtems-4.7.
306
3072004-04-09      Joel Sherrill <joel@OARcorp.com>
308
309        PR 605/bsps
310        * cpu.c: Do not use C++ style comments.
311
3122004-04-07      Greg Menke <gregory.menke@gsfc.nasa.gov>
313        PR 601
314        * cpu_asm.S: Added __mips==32 support for R4000 processors running
315        32 bit code.  Fixed #define problems that caused fpu code to
316        always be included even when no fpu is present.
317
3182004-04-03      Art Ferrer <arturo.b.ferrer@nasa.gov>
319
320        PR 598/bsps
321        * cpu_asm.S, rtems/score/cpu.h: Add save of floating point
322        status/control register on context switches. Missing this register
323        was causing intermittent floating point errors.
324
3252003-09-04      Joel Sherrill <joel@OARcorp.com>
326
327        * cpu.c, cpu_asm.S, rtems/score/cpu.h, rtems/score/mips.h,
328        rtems/score/types.h: URL for license changed.
329
3302003-08-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
331
332        * configure.ac: Use rtems-bugs@rtems.com as bug report email address.
333
3342003-03-06      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
335
336        * configure.ac: Remove AC_CONFIG_AUX_DIR.
337
3382002-12-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
339
340        * configure.ac: Require autoconf-2.57 + automake-1.7.2.
341        * Makefile.am: Eliminate C_O_FILES, S_O_FILES, libscorecpu_a_OBJECTS.
342
3432002-11-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
344
345        * configure.ac: Fix package name.
346
3472002-11-04      Joel Sherrill <joel@OARcorp.com>
348
349        * idtcpu.h: Removed warning.
350
3512002-11-01      Joel Sherrill <joel@OARcorp.com>
352
353        * idtcpu.h: Removed warnings.
354
3552002-10-28      Joel Sherrill <joel@OARcorp.com>
356
357        * idtcpu.h: Removed warning by turning extra token at the end of
358        an endif into a comment.
359
3602002-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
361
362        * configure.ac: Add nostdinc to AM_INIT_AUTOMAKE.
363
3642002-10-21      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
365
366        * .cvsignore: Reformat.
367        Add autom4te*cache.
368        Remove autom4te.cache.
369
3702002-08-14      Greg Menke <gregory.menke@gsfc.nasa.gov>
371
372        * cpu_asm.S: Clarified some comments, removed code that forced
373        SR_IEP on when returning from an interrupt.
374
3752002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
376
377        * configure.ac: Add RTEMS_PROG_CCAS
378
3792002-06-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
380
381        * configure.ac: Use AC_CONFIG_AUX_DIR(../../../..).
382        Add AC_PROG_RANLIB.
383
3842002-06-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
385        * cpu_asm.S: Added SR_IEO to context restore to fix isr disabled
386        deadlock caused by interrupt arriving while dispatching.
387       
3882002-06-17      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
389
390        * Makefile.am: Include $(top_srcdir)/../../../automake/*.am.
391        Use ../../../aclocal.
392
3932001-04-03      Joel Sherrill <joel@OARcorp.com>
394
395        * Per PR94, all rtems/score/CPUtypes.h are named rtems/score/types.h.
396        * rtems/score/mipstypes.h: Removed.
397        * rtems/score/types.h: New file via CVS magic.
398        * Makefile.am, rtems/score/cpu.h: Account for name change.
399
4002002-03-27      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
401
402        * configure.ac:
403        AC_INIT(package,_RTEMS_VERSION,_RTEMS_BUGS).
404        AM_INIT_AUTOMAKE([no-define foreign 1.6]).
405        * Makefile.am: Remove AUTOMAKE_OPTIONS.
406
4072002-03-20      Greg Menke <gregory.menke@gsfc.nasa.gov>
408
409        * cpu_asm.S: Now compiles on 4600 and 4650.
410
4112002-03-13      Greg Menke <gregory.menke@gsfc.nasa.gov>
412
413        * cpu_asm.S: Fixed a sneaky return from int w/ ints disabled bug.
414        * rtems/score/cpu.h: Fixed register numbering in comments and made
415        interrupt enable/disable more robust.
416       
4172002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
418        * cpu_asm.S: Added support for the debug exception vector, cleaned
419        up the exception processing & exception return stuff.  Re-added
420        EPC in the task context structure so the gdb stub will know where
421        a thread is executing.  Should've left it there in the first place...
422        * idtcpu.h: Added support for the debug exception vector.
423        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
424        stack frame in an interrupt so context switch code can get the
425        userspace EPC when scheduling.
426        * rtems/score/cpu.h: Re-added EPC to the task context.
427
4282002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
429
430        * cpu_asm.S: Fixed exception return address, modified FP context
431        switch so FPU is properly enabled and also doesn't screw up the
432        exception FP handling.
433        * idtcpu.h: Added C0_TAR, the MIPS target address register used for
434        returning from exceptions.
435        * iregdef.h: Added R_TAR to the stack frame so the target address
436        can be saved on a per-exception basis.  The new entry is past the
437        end of the frame gdb cares about, so doesn't affect gdb or cpu.h
438        stuff.
439        * rtems/score/cpu.h: added an #ifdef so cpu_asm.S can include it
440        to obtain FPU defines without syntax errors generated by the C
441        defintions.
442        * cpu.c: Improved interrupt level saves & restores.
443       
4442002-02-08      Joel Sherrill <joel@OARcorp.com>
445
446        * iregdef.h, rtems/score/cpu.h: Reordered register in the
447        exception stack frame to better match gdb's expectations.
448
4492001-02-05      Joel Sherrill <joel@OARcorp.com>
450
451        * cpu_asm.S: Enhanced to save/restore more registers on
452        exceptions.
453        * rtems/score/cpu.h (CPU_Interrupt_frame): Enhanced to list every
454        register individually and document when it is saved.
455        * idtcpu.h: Added constants for the coprocessor 1 registers
456        revision and status.
457
4582001-02-05      Joel Sherrill <joel@OARcorp.com>
459
460        * rtems/Makefile.am, rtems/score/Makefile.am: Removed again.
461
4622001-02-04      Joel Sherrill <joel@OARcorp.com>
463
464        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
465        in the previous patch that has now been confirmed.
466
4672001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
468
469        * cpu.c: Enhancements and fixes for modifying the SR when changing
470        the interrupt level.
471        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
472        managed on a per-task basis, improved handling of interrupt levels,
473        and made deferred FP contexts work on the MIPS.
474        * rtems/score/cpu.h: Modified to support above changes.
475
4762002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
477
478        * rtems/Makefile.am: Removed.
479        * rtems/score/Makefile.am: Removed.
480        * configure.ac: Reflect changes above.
481        * Makefile.am: Reflect changes above.
482
4832002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
484
485        * asm.h: Remove #include <rtems/score/targopts.h>.
486        Add #include <rtems/score/cpuopts.h>.
487        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
488
489
4902001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
491
492        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
493
4942001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
495
496        * Makefile.am: Add multilib support.
497
4982001-11-28      Joel Sherrill <joel@OARcorp.com>,
499
500        This was tracked as PR91.
501        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
502        is used to specify if the port uses the standard macro for this (FALSE).
503        A TRUE setting indicates the port provides its own implementation.
504
5052001-10-12      Joel Sherrill <joel@OARcorp.com>
506
507        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
508        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
509        Wayne Bullaughey <wayne@wmi.com>.
510
5112001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
512
513        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
514        * configure.in: Remove.
515        * configure.ac: New file, generated from configure.in by autoupdate.
516
5172001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
518
519        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
520        * Makefile.am: Use 'PREINSTALL_FILES ='.
521
5222001-07-03      Joel Sherrill <joel@OARcorp.com>
523
524        * cpu.c: Fixed typo.
525
5262000-05-24      Joel Sherrill <joel@OARcorp.com>
527
528        * rtems/score/mips.h: Added constants for MIPS exception numbers.
529        All exceptions should be given low numbers and thus can be installed
530        and processed in a uniform manner.  Variances between various MIPS
531        ISA levels were not accounted for.
532
5332001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
534
535        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
536        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
537
5382001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
539
540        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
541        the context initialization to account for floating point tasks. 
542        * rtems/score/mips.h: Added the routines mips_set_cause(),
543        mips_get_fcr31(), and mips_set_fcr31().
544        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
545
5462001-05-07      Joel Sherrill <joel@OARcorp.com>
547
548        * cpu_asm.S: Merged patches from Gregory Menke
549        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
550        stack usage and include nops in the delay slots.
551
5522001-04-20      Joel Sherrill <joel@OARcorp.com>
553
554        * cpu_asm.S: Added code to save and restore SR and EPC to
555        properly support nested interrupts.  Note that the ISR
556        (not RTEMS) enables interrupts allowing the nesting to occur.
557
5582001-03-14      Joel Sherrill <joel@OARcorp.com>
559
560        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
561        Removed unused variable _CPU_Thread_dispatch_pointer
562        and cleaned numerous comments.
563       
5642001-03-13      Joel Sherrill <joel@OARcorp.com>
565
566        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
567        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
568        Also reimplemented some assembly routines in C further reducing
569        the amount of assembly and increasing maintainability.
570
5712001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
572
573        * Makefile.am, rtems/score/Makefile.am:
574        Apply include_*HEADERS instead of H_FILES.
575
5762001-01-12      Joel Sherrill <joel@OARcorp.com>
577
578        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
579        register constraints from "general" to "register".
580
5812001-01-09      Joel Sherrill <joel@OARcorp.com>
582
583        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
584        to make it easier to conditionalize the code for various ISA levels.
585
5862001-01-08      Joel Sherrill <joel@OARcorp.com>
587
588        * idtcpu.h: Commented out definition of "wait".  It was stupid to
589        use such a common word as a macro.
590        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
591        * rtems/score/mips.h: Added include of <idtcpu.h>.
592        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
593
5942001-01-03      Joel Sherrill <joel@OARcorp.com>
595
596        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
597        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
598
5992000-12-19      Joel Sherrill <joel@OARcorp.com>
600
601        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
602        Previous code resulting in the interrupted immediately returning
603        to the caller of the routine it was inside.
604
6052000-12-19      Joel Sherrill <joel@OARcorp.com>
606
607        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
608        because it has not been allocated yet.
609
6102000-12-13      Joel Sherrill <joel@OARcorp.com>
611
612        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
613        * cpu_asm.S: Removed assembly language to vector ISR handler
614        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
615        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
616        longer a constant -- get the real value from libcpu.
617
6182000-12-13      Joel Sherrill <joel@OARcorp.com>
619
620        * cpu_asm.h: Removed.
621        * Makefile.am: Remove cpu_asm.h.
622        * rtems/score/mips64orion.h: Renamed mips.h.
623        * rtems/score/mips.h: New file, formerly mips64orion.h.
624        Header rewritten.
625        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
626        mips_disable_in_interrupt_mask): New macros.
627        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
628        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
629        few defines that were in <cpu_asm.h>.
630        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
631        MIPS ISA 3 is still in assembly for now.
632        (_CPU_Thread_Idle_body): Rewrote in C.
633        * cpu_asm.S: Rewrote file header.
634        (FRAME,ENDFRAME) now in asm.h.
635        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
636        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
637        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
638        leaves other bits in SR alone on task switch.
639        (mips_enable_interrupts,mips_disable_interrupts,
640        mips_enable_global_interrupts,mips_disable_global_interrupts,
641        disable_int, enable_int): Removed.
642        (mips_get_sr): Rewritten as C macro.
643        (_CPU_Thread_Idle_body): Rewritten in C.
644        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
645        placed in libcpu.
646        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
647        to libcpu/mips/shared/interrupts.
648        (general): Cleaned up comment blocks and #if 0 areas.
649        * idtcpu.h: Made ifdef report an error.
650        * iregdef.h: Removed warning.
651        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
652        number defined by libcpu.
653        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
654        to access SR.
655        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
656        (_CPU_Context_Initialize): Honor ISR level in task initialization.
657        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
658
6592000-12-06      Joel Sherrill <joel@OARcorp.com>
660
661        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
662        context should be 32 not 64 bits.
663
6642000-11-30      Joel Sherrill <joel@OARcorp.com>
665
666        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
667        correct name of _CPU_Context_switch_restore.  Added dummy
668        version of exc_utlb_code() so applications would link.
669
6702000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
671
672        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
673
6742000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
675
676        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
677
6782000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
679
680        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
681        Switch to GNU canonicalization.
682
6832000-10-24      Alan Cudmore <alanc@linuxstart.com> and
684        Joel Sherrill <joel@OARcorp.com>
685
686        * This is a major reworking of the mips64orion port to use
687        gcc predefines as much as possible and a big push to multilib
688        the mips port.  The mips64orion port was copied/renamed to mips
689        to be more like other GNU tools.  Alan did most of the technical
690        work of determining how to map old macro names used by the mips64orion
691        port to standard compiler macro definitions.  Joel did the merge
692        with CVS magic to keep individual file history and did the BSP
693        modifications. Details follow:
694        * Makefile.am: idtmon.h in mips64orion port not present.
695        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
696        * cpu.c: Comments added.
697        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
698        First attempt at exception/interrupt processing for ISA level 1
699        and minus any use of IDT/MON added.
700        * idtcpu.h: Conditionals changed to use gcc predefines.
701        * iregdef.h: Ditto.
702        * cpu_asm.h: No real change.  Merger required commit.
703        * rtems/Makefile.am: Ditto.
704        * rtems/score/Makefile.am: Ditto.
705        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
706        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
707        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
708
7092000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
710
711        * Makefile.am: Include compile.am.
712
7132000-08-10      Joel Sherrill <joel@OARcorp.com>
714
715        * ChangeLog: New file.
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