source: rtems/cpukit/score/cpu/mips/ChangeLog @ 0bc5329

4.104.114.84.95
Last change on this file since 0bc5329 was 0bc5329, checked in by Joel Sherrill <joel.sherrill@…>, on 02/04/02 at 20:05:30

2001-02-04 Joel Sherrill <joel@…>

  • rtems/score/cpu.h: IDLE task should not be FP. This was a mistake in the previous patch that has now been confirmed.
  • Property mode set to 100644
File size: 9.4 KB
Line 
12001-02-04      Joel Sherrill <joel@OARcorp.com>
2
3        * rtems/score/cpu.h: IDLE task should not be FP.  This was a mistake
4        in the previous patch that has now been confirmed.
5
62001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
7
8        * cpu.c: Enhancements and fixes for modifying the SR when changing
9        the interrupt level.
10        * cpu_asm.S: Fixed handling of FP enable bit so it is properly
11        managed on a per-task basis, improved handling of interrupt levels,
12        and made deferred FP contexts work on the MIPS.
13        * rtems/score/cpu.h: Modified to support above changes.
14
152002-01-28      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
16
17        * rtems/Makefile.am: Removed.
18        * rtems/score/Makefile.am: Removed.
19        * configure.ac: Reflect changes above.
20        * Makefile.am: Reflect changes above.
21
222002-02-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
23
24        * asm.h: Remove #include <rtems/score/targopts.h>.
25        Add #include <rtems/score/cpuopts.h>.
26        * configure.ac: Remove RTEMS_CHECK_CUSTOM_BSP(RTEMS_BSP).
27
28
292001-12-20      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
30
31        * configure.ac: Use RTEMS_ENV_RTEMSCPU.
32
332001-12-19      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
34
35        * Makefile.am: Add multilib support.
36
372001-11-28      Joel Sherrill <joel@OARcorp.com>,
38
39        This was tracked as PR91.
40        * rtems/score/cpu.h: Added CPU_PROVIDES_ISR_IS_IN_PROGRESS macro which
41        is used to specify if the port uses the standard macro for this (FALSE).
42        A TRUE setting indicates the port provides its own implementation.
43
442001-10-12      Joel Sherrill <joel@OARcorp.com>
45
46        * cpu_asm.S: _CPU_Context_save_fp in was incorrectly in conditional
47        compilation block with (CPU_HARDWARE_FP == FALSE).  Reported by
48        Wayne Bullaughey <wayne@wmi.com>.
49
502001-10-11      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
51
52        * .cvsignore: Add autom4te.cache for autoconf > 2.52.
53        * configure.in: Remove.
54        * configure.ac: New file, generated from configure.in by autoupdate.
55
562001-09-23      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
57
58        * rtems/score/Makefile.am: Use 'PREINSTALL_FILES ='.
59        * Makefile.am: Use 'PREINSTALL_FILES ='.
60
612001-07-03      Joel Sherrill <joel@OARcorp.com>
62
63        * cpu.c: Fixed typo.
64
652000-05-24      Joel Sherrill <joel@OARcorp.com>
66
67        * rtems/score/mips.h: Added constants for MIPS exception numbers.
68        All exceptions should be given low numbers and thus can be installed
69        and processed in a uniform manner.  Variances between various MIPS
70        ISA levels were not accounted for.
71
722001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
73
74        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
75        * cpu_asm.S: Now works on Mongoose-V.  Missed in previous patch.
76
772001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
78
79        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
80        the context initialization to account for floating point tasks. 
81        * rtems/score/mips.h: Added the routines mips_set_cause(),
82        mips_get_fcr31(), and mips_set_fcr31().
83        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
84
852001-05-07      Joel Sherrill <joel@OARcorp.com>
86
87        * cpu_asm.S: Merged patches from Gregory Menke
88        <Gregory.D.Menke.1@gsfc.nasa.gov> that clean up
89        stack usage and include nops in the delay slots.
90
912001-04-20      Joel Sherrill <joel@OARcorp.com>
92
93        * cpu_asm.S: Added code to save and restore SR and EPC to
94        properly support nested interrupts.  Note that the ISR
95        (not RTEMS) enables interrupts allowing the nesting to occur.
96
972001-03-14      Joel Sherrill <joel@OARcorp.com>
98
99        * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h:
100        Removed unused variable _CPU_Thread_dispatch_pointer
101        and cleaned numerous comments.
102       
1032001-03-13      Joel Sherrill <joel@OARcorp.com>
104
105        * cpu.c, cpu_asm.S, iregdef.h, rtems/score/cpu.h, rtems/score/mips.h:
106        Merged MIPS1 and MIPS3 code reducing the number of lines of assembly.
107        Also reimplemented some assembly routines in C further reducing
108        the amount of assembly and increasing maintainability.
109
1102001-02-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
111
112        * Makefile.am, rtems/score/Makefile.am:
113        Apply include_*HEADERS instead of H_FILES.
114
1152001-01-12      Joel Sherrill <joel@OARcorp.com>
116
117        * rtems/score/mips.h (mips_get_sr, mips_set_sr): Corrected
118        register constraints from "general" to "register".
119
1202001-01-09      Joel Sherrill <joel@OARcorp.com>
121
122        * cpu_asm.S: Use SR_INTERRUPT_ENABLE_BITS instead of SR_XXX constants
123        to make it easier to conditionalize the code for various ISA levels.
124
1252001-01-08      Joel Sherrill <joel@OARcorp.com>
126
127        * idtcpu.h: Commented out definition of "wait".  It was stupid to
128        use such a common word as a macro.
129        * rtems/score/cpu.h (_CPU_ISR_Disable): Fixed for mips ISA 3.
130        * rtems/score/mips.h: Added include of <idtcpu.h>.
131        * rtems/score/mips.h (mips_enable_in_interrupt_mask): Corrected.
132
1332001-01-03      Joel Sherrill <joel@OARcorp.com>
134
135        * rtems/score/cpu.h: Added _CPU_Initialize_vectors().
136        * cpu_asm.S: Eliminated warning for duplicate definition of EXTERN.
137
1382000-12-19      Joel Sherrill <joel@OARcorp.com>
139
140        * cpu_asm.S (_ISR_Handler): Return to the address in the EPC register.
141        Previous code resulting in the interrupted immediately returning
142        to the caller of the routine it was inside.
143
1442000-12-19      Joel Sherrill <joel@OARcorp.com>
145
146        * cpu.c (_CPU_Initialize): Do not initialize _ISR_Vector_table() here
147        because it has not been allocated yet.
148
1492000-12-13      Joel Sherrill <joel@OARcorp.com>
150
151        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
152        * cpu_asm.S: Removed assembly language to vector ISR handler
153        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
154        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
155        longer a constant -- get the real value from libcpu.
156
1572000-12-13      Joel Sherrill <joel@OARcorp.com>
158
159        * cpu_asm.h: Removed.
160        * Makefile.am: Remove cpu_asm.h.
161        * rtems/score/mips64orion.h: Renamed mips.h.
162        * rtems/score/mips.h: New file, formerly mips64orion.h.
163        Header rewritten.
164        (mips_get_sr, mips_set_sr, mips_enable_in_interrupt_mask,
165        mips_disable_in_interrupt_mask): New macros.
166        * rtems/score/Makefile.am: Reflect renaming mips64orion.h.
167        * asm.h: Include <mips.h> not <mips64orion.h>. Now includes the
168        few defines that were in <cpu_asm.h>.
169        * cpu.c (_CPU_ISR_Get_level): Added MIPS ISA I version of this routine.
170        MIPS ISA 3 is still in assembly for now.
171        (_CPU_Thread_Idle_body): Rewrote in C.
172        * cpu_asm.S: Rewrote file header.
173        (FRAME,ENDFRAME) now in asm.h.
174        (_CPU_ISR_Get_level): Removed ISA I version and rewrote in C.
175        (_CPU_ISR_Set_level): Removed ISA I version and rewrote in C.
176        (_CPU_Context_switch): MIPS ISA I now manages preserves SR_IEC and
177        leaves other bits in SR alone on task switch.
178        (mips_enable_interrupts,mips_disable_interrupts,
179        mips_enable_global_interrupts,mips_disable_global_interrupts,
180        disable_int, enable_int): Removed.
181        (mips_get_sr): Rewritten as C macro.
182        (_CPU_Thread_Idle_body): Rewritten in C.
183        (init_exc_vecs): Rewritten in C as mips_install_isr_entries() and
184        placed in libcpu.
185        (exc_tlb_code, exc_xtlb_code, exc_cache_code, exc_norm_code): Moved
186        to libcpu/mips/shared/interrupts.
187        (general): Cleaned up comment blocks and #if 0 areas.
188        * idtcpu.h: Made ifdef report an error.
189        * iregdef.h: Removed warning.
190        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): Now a variable
191        number defined by libcpu.
192        (_CPU_ISR_Disable, _CPU_ISR_Enable): Rewritten to use new routines
193        to access SR.
194        (_CPU_ISR_Set_level): Rewritten as macro for ISA I.
195        (_CPU_Context_Initialize): Honor ISR level in task initialization.
196        (_CPU_Fatal_halt): Use new _CPU_ISR_Disable() macro.
197
1982000-12-06      Joel Sherrill <joel@OARcorp.com>
199
200        * rtems/score/cpu.h: When mips ISA level is 1, registers in the
201        context should be 32 not 64 bits.
202
2032000-11-30      Joel Sherrill <joel@OARcorp.com>
204
205        * cpu_asm.S: Changed "_CPU_Ccontext_switch_restore: typo to
206        correct name of _CPU_Context_switch_restore.  Added dummy
207        version of exc_utlb_code() so applications would link.
208
2092000-11-09      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
210
211        * Makefile.am: Use ... instead of RTEMS_TOPdir in ACLOCAL_AMFLAGS.
212
2132000-11-02      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
214
215        * Makefile.am: Switch to ACLOCAL_AMFLAGS = -I $(RTEMS_TOPdir)/aclocal.
216
2172000-10-25      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
218
219        * Makefile.am: ACLOCAL_AMFLAGS= -I $(RTEMS_TOPdir)/macros.
220        Switch to GNU canonicalization.
221
2222000-10-24      Alan Cudmore <alanc@linuxstart.com> and
223        Joel Sherrill <joel@OARcorp.com>
224
225        * This is a major reworking of the mips64orion port to use
226        gcc predefines as much as possible and a big push to multilib
227        the mips port.  The mips64orion port was copied/renamed to mips
228        to be more like other GNU tools.  Alan did most of the technical
229        work of determining how to map old macro names used by the mips64orion
230        port to standard compiler macro definitions.  Joel did the merge
231        with CVS magic to keep individual file history and did the BSP
232        modifications. Details follow:
233        * Makefile.am: idtmon.h in mips64orion port not present.
234        * asm.h: MIPS64ORION replaced with MIPS. Frame setup macros added.
235        * cpu.c: Comments added.
236        * cpu_asm.S: Conditionals changed.  MIPS ISA level 1 support added.
237        First attempt at exception/interrupt processing for ISA level 1
238        and minus any use of IDT/MON added.
239        * idtcpu.h: Conditionals changed to use gcc predefines.
240        * iregdef.h: Ditto.
241        * cpu_asm.h: No real change.  Merger required commit.
242        * rtems/Makefile.am: Ditto.
243        * rtems/score/Makefile.am: Ditto.
244        * rtems/score/cpu.h: Change MIPS64ORION to MIPS.
245        * rtems/score/mips64orion.h: Change MIPS64ORION to MIPS.  Convert
246        from using RTEMS_CPU_MODEL to gcc predefines to figre things out.
247
2482000-09-04      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
249
250        * Makefile.am: Include compile.am.
251
2522000-08-10      Joel Sherrill <joel@OARcorp.com>
253
254        * ChangeLog: New file.
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