1 | /* |
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2 | *------------------------------------------------------------------- |
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3 | * |
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4 | * SIM -- System Integration Module |
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5 | * |
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6 | * The system integration module (SIM) is used on many Motorola 16- |
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7 | * and 32-bit MCUs for the following functions: |
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8 | * |
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9 | * () System configuration and protection. Bus and software watchdog |
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10 | * monitors are provided in addition to periodic interrupt generators. |
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11 | * |
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12 | * () Clock signal generation for other intermodule bus (IMB) members |
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13 | * and external devices. |
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14 | * |
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15 | * () The generation of chip-select signals that simplify external |
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16 | * circuitry interface. |
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17 | * |
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18 | * () Data ports that are available for general purpose input and |
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19 | * output. |
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20 | * |
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21 | * () A system test block that is intended only for factory tests. |
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22 | * |
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23 | * For more information, refer to Motorola's "Modular Microcontroller |
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24 | * Family System Integration Module Reference Manual" (Motorola document |
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25 | * SIMRM/AD). |
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26 | * |
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27 | * This file has been created by John S. Gwynne for support of |
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28 | * Motorola's 68332 MCU in the efi332 project. |
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29 | * |
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30 | * Redistribution and use in source and binary forms are permitted |
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31 | * provided that the following conditions are met: |
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32 | * 1. Redistribution of source code and documentation must retain |
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33 | * the above authorship, this list of conditions and the |
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34 | * following disclaimer. |
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35 | * 2. The name of the author may not be used to endorse or promote |
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36 | * products derived from this software without specific prior |
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37 | * written permission. |
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38 | * |
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39 | * This software is provided "AS IS" without warranty of any kind, |
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40 | * either expressed or implied, including, but not limited to, the |
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41 | * implied warranties of merchantability, title and fitness for a |
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42 | * particular purpose. |
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43 | * |
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44 | *------------------------------------------------------------------ |
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45 | * |
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46 | * $Id$ |
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47 | */ |
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48 | |
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49 | #ifndef _SIM_H_ |
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50 | #define _SIM_H_ |
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51 | |
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52 | |
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53 | #include <efi332.h> |
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54 | |
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55 | |
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56 | /* SAM-- shift and mask */ |
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57 | #undef SAM |
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58 | #define SAM(a,b,c) ((a << b) & c) |
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59 | |
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60 | |
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61 | |
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62 | /* SIM_CRB (SIM Control Register Block) base address of the SIM |
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63 | control registers */ |
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64 | /* not included in ram_init.h */ |
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65 | #if SIM_MM == 0 |
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66 | #define SIM_CRB 0x7ffa00 |
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67 | #else |
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68 | #undef SIM_MM |
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69 | #define SIM_MM 1 |
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70 | #define SIM_CRB 0xfffa00 |
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71 | #endif |
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72 | /* end not included in ram_init.h */ |
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73 | |
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74 | |
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75 | |
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76 | #define SIMCR (volatile unsigned short int * const)(0x00 + SIM_CRB) |
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77 | /* Module Configuration Register */ |
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78 | #define EXOFF 0x8000 /* External Clock Off */ |
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79 | #define FRZSW 0x4000 /* Freeze Software Enable */ |
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80 | #define FRZBM 0x2000 /* Freeze Bus Monitor Enable */ |
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81 | #define SLVEN 0x0800 /* Factory Test Model Enabled (ro)*/ |
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82 | #define SHEN 0x0300 /* Show Cycle Enable */ |
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83 | #define SUPV 0x0080 /* Supervisor/Unrestricted Data Space */ |
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84 | #define MM 0x0040 /* Module Mapping */ |
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85 | #define IARB 0x000f /* Interrupt Arbitration Field */ |
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86 | |
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87 | |
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88 | |
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89 | #define SIMTR (volatile unsigned short int * const)(0x02 + SIM_CRB) |
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90 | /* SIM Test Register */ |
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91 | /* Used only for factor testing */ |
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92 | |
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93 | |
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94 | |
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95 | #define SYNCR (volatile unsigned short int * const)(0x04 + SIM_CRB) |
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96 | /* Clock Synthesizer Control Register */ |
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97 | #define W 0x8000 /* Frequency Control (VCO) */ |
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98 | #define X 0x4000 /* Frequency Control Bit (Prescale) */ |
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99 | #define Y 0x3f00 /* Frequency Control Counter */ |
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100 | #define EDIV 0x0080 /* ECLK Divide Rate */ |
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101 | #define SLIMP 0x0010 /* Limp Mode Status */ |
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102 | #define SLOCK 0x0008 /* Synthesizer Lock */ |
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103 | #define RSTEN 0x0004 /* Reset Enable */ |
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104 | #define STSIM 0x0002 /* Stop Mode SIM Clock */ |
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105 | #define STEXT 0x0001 /* Stop Mode External Clock */ |
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106 | |
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107 | |
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108 | |
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109 | #define RSR (volatile unsigned char * const)(0x07 + SIM_CRB) |
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110 | /* Reset Status Register */ |
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111 | #define EXT 0x0080 /* External Reset */ |
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112 | #define POW 0x0040 /* Power-On Reset */ |
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113 | #define SW 0x0020 /* Software Watchdog Reset */ |
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114 | #define DBF 0x0010 /* Double Bus Fault Reset */ |
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115 | #define LOC 0x0004 /* Loss of Clock Reset */ |
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116 | #define SYS 0x0002 /* System Reset */ |
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117 | #define TST 0x0001 /* Test Submodule Reset */ |
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118 | |
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119 | |
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120 | |
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121 | #define SIMTRE (volatile unsigned short int * const)(0x08 + SIM_CRB) |
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122 | /* System Integration Test Register */ |
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123 | /* Used only for factor testing */ |
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124 | |
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125 | |
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126 | |
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127 | #define PORTE0 (volatile unsigned char * const)(0x11 + SIM_CRB) |
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128 | #define PORTE1 (volatile unsigned char * const)(0x13 + SIM_CRB) |
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129 | /* Port E Data Register */ |
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130 | #define DDRE (volatile unsigned char * const)(0x15 + SIM_CRB) |
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131 | /* Port E Data Direction Register */ |
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132 | #define PEPAR (volatile unsigned char * const)(0x17 + SIM_CRB) |
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133 | /* Port E Pin Assignment Register */ |
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134 | /* Any bit cleared (zero) defines the corresponding pin to be an I/O |
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135 | pin. Any bit set defines the corresponding pin to be a bus control |
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136 | signal. */ |
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137 | |
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138 | |
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139 | |
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140 | #define PORTF0 (volatile unsigned char * const)(0x19 + SIM_CRB) |
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141 | #define PORTF1 (volatile unsigned char * const)(0x1b + SIM_CRB) |
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142 | /* Port F Data Register */ |
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143 | #define DDRF (volatile unsigned char * const)(0x1d + SIM_CRB) |
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144 | /* Port E Data Direction Register */ |
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145 | #define PFPAR (volatile unsigned char * const)(0x1f + SIM_CRB) |
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146 | /* Any bit cleared (zero) defines the corresponding pin to be an I/O |
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147 | pin. Any bit set defines the corresponding pin to be a bus control |
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148 | signal. */ |
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149 | |
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150 | |
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151 | |
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152 | #define SYPCR (volatile unsigned char * const)(0x21 + SIM_CRB) |
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153 | /* !!! can write to only once after reset !!! */ |
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154 | /* System Protection Control Register */ |
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155 | #define SWE 0x80 /* Software Watch Enable */ |
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156 | #define SWP 0x40 /* Software Watchdog Prescale */ |
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157 | #define SWT 0x30 /* Software Watchdog Timing */ |
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158 | #define HME 0x08 /* Halt Monitor Enable */ |
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159 | #define BME 0x04 /* Bus Monitor External Enable */ |
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160 | #define BMT 0x03 /* Bus Monitor Timing */ |
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161 | |
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162 | |
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163 | |
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164 | #define PICR (volatile unsigned short int * const)(0x22 + SIM_CRB) |
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165 | /* Periodic Interrupt Control Reg. */ |
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166 | #define PIRQL 0x0700 /* Periodic Interrupt Request Level */ |
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167 | #define PIV 0x00ff /* Periodic Interrupt Level */ |
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168 | |
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169 | |
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170 | |
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171 | #define PITR (volatile unsigned short int * const)(0x24 + SIM_CRB) |
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172 | /* Periodic Interrupt Timer Register */ |
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173 | #define PTP 0x0100 /* Periodic Timer Prescaler Control */ |
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174 | #define PITM 0x00ff /* Periodic Interrupt Timing Modulus */ |
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175 | |
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176 | |
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177 | |
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178 | #define SWSR (volatile unsigned char * const)(0x27 + SIM_CRB) |
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179 | /* Software Service Register */ |
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180 | /* write 0x55 then 0xaa to service the software watchdog */ |
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181 | |
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182 | |
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183 | |
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184 | #define TSTMSRA (volatile unsigned short int * const)(0x30 + SIM_CRB) |
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185 | /* Test Module Master Shift A */ |
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186 | #define TSTMSRB (volatile unsigned short int * const)(0x32 + SIM_CRB) |
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187 | /* Test Module Master Shift A */ |
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188 | #define TSTSC (volatile unsigned short int * const)(0x34 + SIM_CRB) |
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189 | /* Test Module Shift Count */ |
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190 | #define TSTRC (volatile unsigned short int * const)(0x36 + SIM_CRB) |
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191 | /* Test Module Repetition Counter */ |
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192 | #define CREG (volatile unsigned short int * const)(0x38 + SIM_CRB) |
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193 | /* Test Module Control */ |
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194 | #define DREG (volatile unsigned short int * const)(0x3a + SIM_CRB) |
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195 | /* Test Module Distributed */ |
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196 | /* Used only for factor testing */ |
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197 | |
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198 | |
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199 | |
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200 | #define PORTC (volatile unsigned char * const)(0x41 + SIM_CRB) |
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201 | /* Port C Data */ |
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202 | |
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203 | |
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204 | |
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205 | #define CSPAR0 (volatile unsigned short int * const)(0x44 + SIM_CRB) |
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206 | /* Chip Select Pin Assignment |
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207 | Resgister 0 */ |
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208 | /* CSPAR0 contains seven two-bit fields that determine the functions |
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209 | of corresponding chip-select pins. CSPAR0[15:14] are not |
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210 | used. These bits always read zero; write have no effect. CSPAR0 bit |
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211 | 1 always reads one; writes to CSPAR0 bit 1 have no effect. */ |
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212 | #define CSPAR1 (volatile unsigned short int * const)(0x46 + SIM_CRB) |
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213 | /* Chip Select Pin Assignment |
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214 | Register 1 */ |
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215 | /* CSPAR1 contains five two-bit fields that determine the finctions of |
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216 | corresponding chip-select pins. CSPAR1[15:10] are not used. These |
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217 | bits always read zero; writes have no effect. */ |
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218 | /* |
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219 | * |
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220 | * Bit Field | Description |
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221 | * ------------+--------------- |
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222 | * 00 | Discrete Output |
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223 | * 01 | Alternate Function |
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224 | * 10 | Chip Select (8-bit port) |
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225 | * 11 | Chip Select (16-bit port) |
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226 | */ |
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227 | #define DisOut 0x0 |
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228 | #define AltFun 0x1 |
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229 | #define CS8bit 0x2 |
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230 | #define CS16bit 0x3 |
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231 | /* |
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232 | * |
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233 | * CSPARx Field |Chip Select Signal | Alternate Signal | Discrete Output |
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234 | *-----------------+--------------------+--------------------+---------------*/ |
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235 | #define CS_5 12 /* !CS5 | FC2 | PC2 */ |
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236 | #define CS_4 10 /* !CS4 | FC1 | PC1 */ |
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237 | #define CS_3 8 /* !CS3 | FC0 | PC0 */ |
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238 | #define CS_2 6 /* !CS2 | !BGACK | */ |
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239 | #define CS_1 4 /* !CS1 | !BG | */ |
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240 | #define CS_0 2 /* !CS0 | !BR | */ |
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241 | #define CSBOOT 0 /* !CSBOOT | | */ |
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242 | /* | | | */ |
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243 | #define CS_10 8 /* !CS10 | ADDR23 | ECLK */ |
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244 | #define CS_9 6 /* !CS9 | ADDR22 | PC6 */ |
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245 | #define CS_8 4 /* !CS8 | ADDR21 | PC5 */ |
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246 | #define CS_7 2 /* !CS7 | ADDR20 | PC4 */ |
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247 | #define CS_6 0 /* !CS6 | ADDR19 | PC3 */ |
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248 | |
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249 | #define BS_2K 0x0 |
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250 | #define BS_8K 0x1 |
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251 | #define BS_16K 0x2 |
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252 | #define BS_64K 0x3 |
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253 | #define BS_128K 0x4 |
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254 | #define BS_256K 0x5 |
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255 | #define BS_512K 0x6 |
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256 | #define BS_1M 0x7 |
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257 | |
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258 | #define CSBARBT (volatile unsigned short int * const)(0x48 + SIM_CRB) |
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259 | #define CSBAR0 (volatile unsigned short int * const)(0x4c + SIM_CRB) |
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260 | #define CSBAR1 (volatile unsigned short int * const)(0x50 + SIM_CRB) |
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261 | #define CSBAR2 (volatile unsigned short int * const)(0x54 + SIM_CRB) |
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262 | #define CSBAR3 (volatile unsigned short int * const)(0x58 + SIM_CRB) |
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263 | #define CSBAR4 (volatile unsigned short int * const)(0x5c + SIM_CRB) |
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264 | #define CSBAR5 (volatile unsigned short int * const)(0x60 + SIM_CRB) |
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265 | #define CSBAR6 (volatile unsigned short int * const)(0x64 + SIM_CRB) |
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266 | #define CSBAR7 (volatile unsigned short int * const)(0x68 + SIM_CRB) |
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267 | #define CSBAR8 (volatile unsigned short int * const)(0x6c + SIM_CRB) |
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268 | #define CSBAR9 (volatile unsigned short int * const)(0x70 + SIM_CRB) |
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269 | #define CSBAR10 (volatile unsigned short int * const)(0x74 + SIM_CRB) |
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270 | |
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271 | #define MODE 0x8000 |
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272 | #define Disable 0 |
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273 | #define LowerByte 0x2000 |
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274 | #define UpperByte 0x4000 |
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275 | #define BothBytes 0x6000 |
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276 | #define ReadOnly 0x0800 |
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277 | #define WriteOnly 0x1000 |
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278 | #define ReadWrite 0x1800 |
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279 | #define SyncAS 0x0 |
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280 | #define SyncDS 0x0400 |
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281 | |
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282 | #define WaitStates_0 (0x0 << 6) |
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283 | #define WaitStates_1 (0x1 << 6) |
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284 | #define WaitStates_2 (0x2 << 6) |
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285 | #define WaitStates_3 (0x3 << 6) |
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286 | #define WaitStates_4 (0x4 << 6) |
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287 | #define WaitStates_5 (0x5 << 6) |
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288 | #define WaitStates_6 (0x6 << 6) |
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289 | #define WaitStates_7 (0x7 << 6) |
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290 | #define WaitStates_8 (0x8 << 6) |
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291 | #define WaitStates_9 (0x9 << 6) |
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292 | #define WaitStates_10 (0xa << 6) |
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293 | #define WaitStates_11 (0xb << 6) |
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294 | #define WaitStates_12 (0xc << 6) |
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295 | #define WaitStates_13 (0xd << 6) |
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296 | #define FastTerm (0xe << 6) |
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297 | #define External (0xf << 6) |
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298 | |
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299 | #define CPUSpace (0x0 << 4) |
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300 | #define UserSpace (0x1 << 4) |
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301 | #define SupSpace (0x2 << 4) |
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302 | #define UserSupSpace (0x3 << 4) |
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303 | |
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304 | #define IPLevel_any 0x0 |
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305 | #define IPLevel_1 0x2 |
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306 | #define IPLevel_2 0x4 |
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307 | #define IPLevel_3 0x6 |
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308 | #define IPLevel_4 0x8 |
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309 | #define IPLevel_5 0xa |
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310 | #define IPLevel_6 0xc |
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311 | #define IPLevel_7 0xe |
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312 | |
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313 | #define AVEC 1 |
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314 | |
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315 | #define CSORBT (volatile unsigned short int * const)(0x4a + SIM_CRB) |
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316 | #define CSOR0 (volatile unsigned short int * const)(0x4e + SIM_CRB) |
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317 | #define CSOR1 (volatile unsigned short int * const)(0x52 + SIM_CRB) |
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318 | #define CSOR2 (volatile unsigned short int * const)(0x56 + SIM_CRB) |
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319 | #define CSOR3 (volatile unsigned short int * const)(0x5a + SIM_CRB) |
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320 | #define CSOR4 (volatile unsigned short int * const)(0x5e + SIM_CRB) |
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321 | #define CSOR5 (volatile unsigned short int * const)(0x62 + SIM_CRB) |
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322 | #define CSOR6 (volatile unsigned short int * const)(0x66 + SIM_CRB) |
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323 | #define CSOR7 (volatile unsigned short int * const)(0x6a + SIM_CRB) |
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324 | #define CSOR8 (volatile unsigned short int * const)(0x6e + SIM_CRB) |
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325 | #define CSOR9 (volatile unsigned short int * const)(0x72 + SIM_CRB) |
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326 | #define CSOR10 (volatile unsigned short int * const)(0x76 + SIM_CRB) |
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327 | |
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328 | #endif /* _SIM_h_ */ |
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