source: rtems/cpukit/score/cpu/m68k/sim.h @ 8bdcfc4

4.104.114.84.95
Last change on this file since 8bdcfc4 was eb5a7e07, checked in by Joel Sherrill <joel.sherrill@…>, on Oct 6, 1995 at 8:48:38 PM

fixed missing CVS IDs

  • Property mode set to 100644
File size: 11.9 KB
Line 
1/*
2 *-------------------------------------------------------------------
3 *
4 *   SIM -- System Integration Module
5 *
6 * The system integration module (SIM) is used on many Motorola 16-
7 * and 32-bit MCUs for the following functions:
8 *
9 *  () System configuration and protection. Bus and software watchdog
10 *  monitors are provided in addition to periodic interrupt generators.
11 *
12 *  () Clock signal generation for other intermodule bus (IMB) members
13 *  and external devices.
14 *
15 *  () The generation of chip-select signals that simplify external
16 *  circuitry interface.
17 *
18 *  () Data ports that are available for general purpose input and
19 *  output.
20 *
21 *  () A system test block that is intended only for factory tests.
22 *
23 * For more information, refer to Motorola's "Modular Microcontroller
24 * Family System Integration Module Reference Manual" (Motorola document
25 * SIMRM/AD).
26 *
27 * This file has been created by John S. Gwynne for support of
28 * Motorola's 68332 MCU in the efi332 project.
29 *
30 * Redistribution and use in source and binary forms are permitted
31 * provided that the following conditions are met:
32 * 1. Redistribution of source code and documentation must retain
33 *    the above authorship, this list of conditions and the
34 *    following disclaimer.
35 * 2. The name of the author may not be used to endorse or promote
36 *    products derived from this software without specific prior
37 *    written permission.
38 *
39 * This software is provided "AS IS" without warranty of any kind,
40 * either expressed or implied, including, but not limited to, the
41 * implied warranties of merchantability, title and fitness for a
42 * particular purpose.
43 *
44 *------------------------------------------------------------------
45 *
46 *  $Id$
47 */
48
49#ifndef _SIM_H_
50#define _SIM_H_
51
52
53#include <efi332.h>
54
55
56/* SAM-- shift and mask */
57#undef  SAM
58#define SAM(a,b,c) ((a << b) & c)
59
60
61
62/* SIM_CRB (SIM Control Register Block) base address of the SIM
63   control registers */
64/* not included in ram_init.h */
65#if SIM_MM == 0
66#define SIM_CRB 0x7ffa00
67#else
68#undef SIM_MM
69#define SIM_MM 1
70#define SIM_CRB 0xfffa00
71#endif
72/* end not included in ram_init.h */
73
74
75
76#define SIMCR (volatile unsigned short int * const)(0x00 + SIM_CRB)
77                                /* Module Configuration Register */
78#define    EXOFF 0x8000         /*    External Clock Off */
79#define    FRZSW 0x4000         /*    Freeze Software Enable */
80#define    FRZBM 0x2000         /*    Freeze Bus Monitor Enable */
81#define    SLVEN 0x0800         /*    Factory Test Model Enabled (ro)*/
82#define    SHEN  0x0300         /*    Show Cycle Enable */
83#define    SUPV  0x0080         /*    Supervisor/Unrestricted Data Space */
84#define    MM    0x0040         /*    Module Mapping */
85#define    IARB  0x000f         /*    Interrupt Arbitration Field */
86
87
88
89#define SIMTR (volatile unsigned short int * const)(0x02 + SIM_CRB)
90                                /* SIM Test Register */
91/* Used only for factor testing */
92
93
94
95#define SYNCR (volatile unsigned short int * const)(0x04 + SIM_CRB)
96                                /* Clock Synthesizer Control Register */
97#define    W     0x8000         /*    Frequency Control (VCO) */
98#define    X     0x4000         /*    Frequency Control Bit (Prescale) */
99#define    Y     0x3f00         /*    Frequency Control Counter */
100#define    EDIV  0x0080         /*    ECLK Divide Rate */
101#define    SLIMP 0x0010         /*    Limp Mode Status */
102#define    SLOCK 0x0008         /*    Synthesizer Lock */
103#define    RSTEN 0x0004         /*    Reset Enable */
104#define    STSIM 0x0002         /*    Stop Mode SIM Clock */
105#define    STEXT 0x0001         /*    Stop Mode External Clock */
106
107
108
109#define RSR (volatile unsigned char * const)(0x07 + SIM_CRB)
110                                /* Reset Status Register */
111#define    EXT   0x0080         /*    External Reset */
112#define    POW   0x0040         /*    Power-On Reset */
113#define    SW    0x0020         /*    Software Watchdog Reset */
114#define    DBF   0x0010         /*    Double Bus Fault Reset */
115#define    LOC   0x0004         /*    Loss of Clock Reset */
116#define    SYS   0x0002         /*    System Reset */
117#define    TST   0x0001         /*    Test Submodule Reset */
118
119
120
121#define SIMTRE (volatile unsigned short int * const)(0x08 + SIM_CRB)
122                                /* System Integration Test Register */
123/* Used only for factor testing */
124
125
126
127#define PORTE0 (volatile unsigned char * const)(0x11 + SIM_CRB)
128#define PORTE1 (volatile unsigned char * const)(0x13 + SIM_CRB)
129                                /* Port E Data Register */
130#define DDRE (volatile unsigned char * const)(0x15 + SIM_CRB)
131                                /* Port E Data Direction Register */
132#define PEPAR (volatile unsigned char * const)(0x17 + SIM_CRB)
133                                /* Port E Pin Assignment Register */
134/* Any bit cleared (zero) defines the corresponding pin to be an I/O
135   pin. Any bit set defines the corresponding pin to be a bus control
136   signal. */
137
138
139
140#define PORTF0 (volatile unsigned char * const)(0x19 + SIM_CRB)
141#define PORTF1 (volatile unsigned char * const)(0x1b + SIM_CRB)
142                                /* Port F Data Register */
143#define DDRF (volatile unsigned char * const)(0x1d + SIM_CRB)
144                                /* Port E Data Direction Register */
145#define PFPAR (volatile unsigned char * const)(0x1f + SIM_CRB)
146/* Any bit cleared (zero) defines the corresponding pin to be an I/O
147   pin. Any bit set defines the corresponding pin to be a bus control
148   signal. */
149
150
151
152#define SYPCR (volatile unsigned char * const)(0x21 + SIM_CRB)
153/* !!! can write to only once after reset !!! */
154                                /* System Protection Control Register */
155#define    SWE   0x80           /*    Software Watch Enable */
156#define    SWP   0x40           /*    Software Watchdog Prescale */
157#define    SWT   0x30           /*    Software Watchdog Timing */
158#define    HME   0x08           /*    Halt Monitor Enable */
159#define    BME   0x04           /*    Bus Monitor External Enable */
160#define    BMT   0x03           /*    Bus Monitor Timing */
161
162
163
164#define PICR (volatile unsigned short int * const)(0x22 + SIM_CRB)
165                                /* Periodic Interrupt Control Reg. */
166#define    PIRQL 0x0700         /*    Periodic Interrupt Request Level */
167#define    PIV   0x00ff         /*    Periodic Interrupt Level */
168
169
170
171#define PITR (volatile unsigned short int * const)(0x24 + SIM_CRB)
172                                /* Periodic Interrupt Timer Register */
173#define    PTP   0x0100         /*    Periodic Timer Prescaler Control */
174#define    PITM  0x00ff         /*    Periodic Interrupt Timing Modulus */
175
176
177
178#define SWSR (volatile unsigned char * const)(0x27 + SIM_CRB)
179                                /* Software Service Register */
180/* write 0x55 then 0xaa to service the software watchdog */
181
182
183
184#define TSTMSRA (volatile unsigned short int * const)(0x30 + SIM_CRB)
185                                /* Test Module Master Shift A */
186#define TSTMSRB (volatile unsigned short int * const)(0x32 + SIM_CRB)
187                                /* Test Module Master Shift A */
188#define TSTSC (volatile unsigned short int * const)(0x34 + SIM_CRB)
189                                /* Test Module Shift Count */
190#define TSTRC (volatile unsigned short int * const)(0x36 + SIM_CRB)
191                                /* Test Module Repetition Counter */
192#define CREG (volatile unsigned short int * const)(0x38 + SIM_CRB)
193                                /* Test Module Control */
194#define DREG (volatile unsigned short int * const)(0x3a + SIM_CRB)
195                                /* Test Module Distributed */
196/* Used only for factor testing */
197
198
199
200#define PORTC (volatile unsigned char * const)(0x41 + SIM_CRB)
201                                /* Port C Data */
202
203
204
205#define CSPAR0 (volatile unsigned short int * const)(0x44 + SIM_CRB)
206                                /* Chip Select Pin Assignment
207                                   Resgister 0 */
208/* CSPAR0 contains seven two-bit fields that determine the functions
209   of corresponding chip-select pins. CSPAR0[15:14] are not
210   used. These bits always read zero; write have no effect. CSPAR0 bit
211   1 always reads one; writes to CSPAR0 bit 1 have no effect. */
212#define CSPAR1 (volatile unsigned short int * const)(0x46 + SIM_CRB)
213                                /* Chip Select Pin Assignment
214                                   Register 1 */
215/* CSPAR1 contains five two-bit fields that determine the finctions of
216   corresponding chip-select pins. CSPAR1[15:10] are not used. These
217   bits always read zero; writes have no effect. */
218/*
219 *
220 *                      Bit Field  |  Description
221 *                     ------------+---------------
222 *                         00      | Discrete Output
223 *                         01      | Alternate Function
224 *                         10      | Chip Select (8-bit port)
225 *                         11      | Chip Select (16-bit port)
226 */
227#define DisOut 0x0
228#define AltFun 0x1
229#define CS8bit 0x2
230#define CS16bit 0x3
231/*
232 *
233 * CSPARx Field    |Chip Select Signal  |  Alternate Signal  |  Discrete Output
234 *-----------------+--------------------+--------------------+---------------*/
235#define CS_5    12 /*     !CS5          |         FC2        |       PC2     */
236#define CS_4    10 /*     !CS4          |         FC1        |       PC1     */
237#define CS_3     8 /*     !CS3          |         FC0        |       PC0     */
238#define CS_2     6 /*     !CS2          |       !BGACK       |               */
239#define CS_1     4 /*     !CS1          |         !BG        |               */
240#define CS_0     2 /*     !CS0          |         !BR        |               */
241#define CSBOOT   0 /*     !CSBOOT       |                    |               */
242/*                 |                    |                    |               */
243#define CS_10    8 /*     !CS10         |       ADDR23       |      ECLK     */
244#define CS_9     6 /*     !CS9          |       ADDR22       |       PC6     */
245#define CS_8     4 /*     !CS8          |       ADDR21       |       PC5     */
246#define CS_7     2 /*     !CS7          |       ADDR20       |       PC4     */
247#define CS_6     0 /*     !CS6          |       ADDR19       |       PC3     */
248
249#define BS_2K 0x0
250#define BS_8K 0x1
251#define BS_16K 0x2
252#define BS_64K 0x3
253#define BS_128K 0x4
254#define BS_256K 0x5
255#define BS_512K 0x6
256#define BS_1M 0x7
257
258#define CSBARBT (volatile unsigned short int * const)(0x48 + SIM_CRB)
259#define CSBAR0 (volatile unsigned short int * const)(0x4c + SIM_CRB)
260#define CSBAR1 (volatile unsigned short int * const)(0x50 + SIM_CRB)
261#define CSBAR2 (volatile unsigned short int * const)(0x54 + SIM_CRB)
262#define CSBAR3 (volatile unsigned short int * const)(0x58 + SIM_CRB)
263#define CSBAR4 (volatile unsigned short int * const)(0x5c + SIM_CRB)
264#define CSBAR5 (volatile unsigned short int * const)(0x60 + SIM_CRB)
265#define CSBAR6 (volatile unsigned short int * const)(0x64 + SIM_CRB)
266#define CSBAR7 (volatile unsigned short int * const)(0x68 + SIM_CRB)
267#define CSBAR8 (volatile unsigned short int * const)(0x6c + SIM_CRB)
268#define CSBAR9 (volatile unsigned short int * const)(0x70 + SIM_CRB)
269#define CSBAR10 (volatile unsigned short int * const)(0x74 + SIM_CRB)
270
271#define MODE 0x8000
272#define Disable 0
273#define LowerByte 0x2000
274#define UpperByte 0x4000
275#define BothBytes 0x6000
276#define ReadOnly 0x0800
277#define WriteOnly 0x1000
278#define ReadWrite 0x1800
279#define SyncAS 0x0
280#define SyncDS 0x0400
281
282#define WaitStates_0 (0x0 << 6)
283#define WaitStates_1 (0x1 << 6)
284#define WaitStates_2 (0x2 << 6)
285#define WaitStates_3 (0x3 << 6)
286#define WaitStates_4 (0x4 << 6)
287#define WaitStates_5 (0x5 << 6)
288#define WaitStates_6 (0x6 << 6)
289#define WaitStates_7 (0x7 << 6)
290#define WaitStates_8 (0x8 << 6)
291#define WaitStates_9 (0x9 << 6)
292#define WaitStates_10 (0xa << 6)
293#define WaitStates_11 (0xb << 6)
294#define WaitStates_12 (0xc << 6)
295#define WaitStates_13 (0xd << 6)
296#define FastTerm (0xe << 6)
297#define External (0xf << 6)
298
299#define CPUSpace (0x0 << 4)
300#define UserSpace (0x1 << 4)
301#define SupSpace (0x2 << 4)
302#define UserSupSpace (0x3 << 4)
303
304#define IPLevel_any 0x0
305#define IPLevel_1 0x2
306#define IPLevel_2 0x4
307#define IPLevel_3 0x6
308#define IPLevel_4 0x8
309#define IPLevel_5 0xa
310#define IPLevel_6 0xc
311#define IPLevel_7 0xe
312
313#define AVEC 1
314
315#define CSORBT (volatile unsigned short int * const)(0x4a + SIM_CRB)
316#define CSOR0 (volatile unsigned short int * const)(0x4e + SIM_CRB)
317#define CSOR1 (volatile unsigned short int * const)(0x52 + SIM_CRB)
318#define CSOR2 (volatile unsigned short int * const)(0x56 + SIM_CRB)
319#define CSOR3 (volatile unsigned short int * const)(0x5a + SIM_CRB)
320#define CSOR4 (volatile unsigned short int * const)(0x5e + SIM_CRB)
321#define CSOR5 (volatile unsigned short int * const)(0x62 + SIM_CRB)
322#define CSOR6 (volatile unsigned short int * const)(0x66 + SIM_CRB)
323#define CSOR7 (volatile unsigned short int * const)(0x6a + SIM_CRB)
324#define CSOR8 (volatile unsigned short int * const)(0x6e + SIM_CRB)
325#define CSOR9 (volatile unsigned short int * const)(0x72 + SIM_CRB)
326#define CSOR10 (volatile unsigned short int * const)(0x76 + SIM_CRB)
327
328#endif /* _SIM_h_ */
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