source: rtems/cpukit/score/cpu/m68k/rtems/score/m68k.h @ 97c73ed

4.104.114.84.95
Last change on this file since 97c73ed was 97c73ed, checked in by Ralf Corsepius <ralf.corsepius@…>, on Jul 31, 2007 at 4:48:38 PM

Replace M68K_COLDFIRE_ARCH with mcoldfire.

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File size: 12.2 KB
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1/**
2 * @file rtems/score/m68k.h
3 */
4
5/*
6 *  This include file contains information pertaining to the Motorola
7 *  m68xxx processor family.
8 *
9 *  COPYRIGHT (c) 1989-1999.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18
19#ifndef _RTEMS_SCORE_M68K_H
20#define _RTEMS_SCORE_M68K_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26/*
27 *  This section contains the information required to build
28 *  RTEMS for a particular member of the Motorola MC68xxx
29 *  family.  It does this by setting variables to indicate
30 *  which implementation dependent features are present in
31 *  a particular member of the family.
32 *
33 *  Currently recognized:
34 *     -m68000
35 *     -m68000 -msoft-float
36 *     -m68020
37 *     -m68020 -msoft-float
38 *     -m68030
39 *     -m68040 -msoft-float
40 *     -m68040
41 *     -m68040 -msoft-float
42 *     -m68060
43 *     -m68060 -msoft-float
44 *     -m68302        (no FP) (deprecated, use -m68000)
45 *     -m68332        (no FP) (deprecated, use -mcpu32)
46 *     -mcpu32        (no FP)
47 *     -m5200         (no FP)
48 *     -m528x         (no FP, ISA A+)
49 *
50 *  As of gcc 2.8.1 and egcs 1.1, there is no distinction made between
51 *  the CPU32 and CPU32+.  The option -mcpu32 generates code which can
52 *  be run on either core.  RTEMS distinguishes between these two cores
53 *  because they have different alignment rules which impact performance.
54 *  If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should
55 *  be defined in your custom file (see make/custom/gen68360.cfg for an
56 *  example of how to do this.  If gcc ever distinguishes between these
57 *  two cores, then RTEMS__mcpu32p__ usage will be replaced with the
58 *  appropriate compiler defined predefine.
59 *
60 *  Here is some information on the 040 variants (courtesy of Doug McBride,
61 *  mcbride@rodin.colorado.edu):
62 *
63 *    "The 68040 is a superset of the 68EC040 and the 68LC040.  The
64 *    68EC040 and 68LC040 do not have FPU's.  The 68LC040 and the
65 *    68EC040 have renamed the DLE pin as JS0 which must be tied to
66 *    Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1.  The
67 *    68EC040 has access control units instead of memory management units.
68 *    The 68EC040 should not have the PFLUSH or PTEST instructions executed
69 *    (cause an indeterminate result).  The 68EC040 and 68LC040 do not
70 *    implement the DLE or multiplexed bus modes.  The 68EC040 does not
71 *    implement the output buffer impedance selection mode of operation."
72 *
73 *  M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
74 *  which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
75 *  68010, 68302, 68306, 68307).  This instruction is available on the 68020
76 *  up and the cpu32 based models. 
77 *
78 *  M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned
79 *  data access (68020, 68030, 68040, 68060, CPU32+).
80 *
81 *  NOTE:
82 *    Eventually it would be nice to evaluate doing a lot of this section
83 *    by having each model specify which core it uses and then go from there.
84 */
85
86/*
87 *  Figure out all CPU Model Feature Flags based upon compiler
88 *  predefines.   Notice the only exception to this is that
89 *  gcc does not distinguish between CPU32 and CPU32+.  This
90 *  feature selection logic is setup such that if RTEMS__mcpu32p__
91 *  is defined, then CPU32+ rules are used.  Otherwise, the safe
92 *  but less efficient CPU32 rules are used for the CPU32+.
93 */
94
95#if (defined(__mc68020__) && !defined(__mcpu32__))
96 
97#define CPU_MODEL_NAME          "m68020"
98#define M68K_HAS_VBR             1
99#define M68K_HAS_SEPARATE_STACKS 1
100#define M68K_HAS_BFFFO           1
101#define M68K_HAS_PREINDEXING     1
102#define M68K_HAS_EXTB_L          1
103#define M68K_HAS_MISALIGNED      1
104# if defined (__HAVE_68881__)
105# define M68K_HAS_FPU            1
106# define M68K_HAS_FPSP_PACKAGE   0
107# else
108# define M68K_HAS_FPU            0
109# define M68K_HAS_FPSP_PACKAGE   0
110# endif
111 
112#elif defined(__mc68030__)
113 
114#define CPU_MODEL_NAME          "m68030"
115#define M68K_HAS_VBR             1
116#define M68K_HAS_SEPARATE_STACKS 1
117#define M68K_HAS_BFFFO           1
118#define M68K_HAS_PREINDEXING     1
119#define M68K_HAS_EXTB_L          1
120#define M68K_HAS_MISALIGNED      1
121# if defined (__HAVE_68881__)
122# define M68K_HAS_FPU            1
123# define M68K_HAS_FPSP_PACKAGE   0
124# else
125# define M68K_HAS_FPU            0
126# define M68K_HAS_FPSP_PACKAGE   0
127# endif
128 
129#elif defined(__mc68040__)
130
131#define CPU_MODEL_NAME          "m68040"
132#define M68K_HAS_VBR             1
133#define M68K_HAS_SEPARATE_STACKS 1
134#define M68K_HAS_BFFFO           1
135#define M68K_HAS_PREINDEXING     1
136#define M68K_HAS_EXTB_L          1
137#define M68K_HAS_MISALIGNED      1
138# if defined (__HAVE_68881__)
139# define M68K_HAS_FPU            1
140# define M68K_HAS_FPSP_PACKAGE   1
141# else
142# define M68K_HAS_FPU            0
143# define M68K_HAS_FPSP_PACKAGE   0
144# endif
145 
146#elif defined(__mc68060__)
147
148#define CPU_MODEL_NAME          "m68060"
149#define M68K_HAS_VBR             1
150#define M68K_HAS_SEPARATE_STACKS 0
151#define M68K_HAS_BFFFO           1
152#define M68K_HAS_PREINDEXING     1
153#define M68K_HAS_EXTB_L          1
154#define M68K_HAS_MISALIGNED      1
155# if defined (__HAVE_68881__)
156# define M68K_HAS_FPU            1
157# define M68K_HAS_FPSP_PACKAGE   0
158# else
159# define M68K_HAS_FPU            0
160# define M68K_HAS_FPSP_PACKAGE   0
161# endif
162 
163#elif defined(__mc68302__)
164
165#define CPU_MODEL_NAME          "m68302"
166#define M68K_HAS_VBR             0
167#define M68K_HAS_SEPARATE_STACKS 0
168#define M68K_HAS_BFFFO           0
169#define M68K_HAS_PREINDEXING     0
170#define M68K_HAS_EXTB_L          0
171#define M68K_HAS_MISALIGNED      0
172#define M68K_HAS_FPU             0
173#define M68K_HAS_FPSP_PACKAGE    0
174
175  /* gcc and egcs do not distinguish between CPU32 and CPU32+ */
176#elif defined(RTEMS__mcpu32p__)
177 
178#define CPU_MODEL_NAME          "mcpu32+"
179#define M68K_HAS_VBR             1
180#define M68K_HAS_SEPARATE_STACKS 0
181#define M68K_HAS_BFFFO           0
182#define M68K_HAS_PREINDEXING     1
183#define M68K_HAS_EXTB_L          1
184#define M68K_HAS_MISALIGNED      1
185#define M68K_HAS_FPU             0
186#define M68K_HAS_FPSP_PACKAGE    0
187
188#elif defined(__mcpu32__)
189 
190#define CPU_MODEL_NAME          "mcpu32"
191#define M68K_HAS_VBR             1
192#define M68K_HAS_SEPARATE_STACKS 0
193#define M68K_HAS_BFFFO           0
194#define M68K_HAS_PREINDEXING     1
195#define M68K_HAS_EXTB_L          1
196#define M68K_HAS_MISALIGNED      0
197#define M68K_HAS_FPU             0
198#define M68K_HAS_FPSP_PACKAGE    0
199
200#elif defined(__mcf528x__)
201/* Motorola ColdFire ISA A+ - RISC/68020 hybrid */ 
202#define CPU_MODEL_NAME         "m528x"
203#define M68K_HAS_VBR             1
204#define M68K_HAS_BFFFO           0
205#define M68K_HAS_SEPARATE_STACKS 0
206#define M68K_HAS_PREINDEXING     0
207#define M68K_HAS_EXTB_L          1
208#define M68K_HAS_MISALIGNED      1
209#define M68K_HAS_FPU             0
210#define M68K_HAS_FPSP_PACKAGE    0
211#define M68K_HAS_ISA_APLUS       1
212
213#elif defined(__mcf5200__)
214/* Motorola ColdFire V2 core - RISC/68020 hybrid */ 
215#define CPU_MODEL_NAME         "m5200"
216#define M68K_HAS_VBR             1
217#define M68K_HAS_BFFFO           0
218#define M68K_HAS_SEPARATE_STACKS 0
219#define M68K_HAS_PREINDEXING     0
220#define M68K_HAS_EXTB_L          1
221#define M68K_HAS_MISALIGNED      1
222#define M68K_HAS_FPU             0
223#define M68K_HAS_FPSP_PACKAGE    0
224#define M68K_HAS_ISA_APLUS       0
225
226#elif defined(__mc68000__)
227 
228#define CPU_MODEL_NAME          "m68000"
229#define M68K_HAS_VBR             0
230#define M68K_HAS_SEPARATE_STACKS 0
231#define M68K_HAS_BFFFO           0
232#define M68K_HAS_PREINDEXING     0
233#define M68K_HAS_EXTB_L          0
234#define M68K_HAS_MISALIGNED      0
235# if defined (__HAVE_68881__)
236# define M68K_HAS_FPU            1
237# define M68K_HAS_FPSP_PACKAGE   0
238# else
239# define M68K_HAS_FPU            0
240# define M68K_HAS_FPSP_PACKAGE   0
241# endif
242
243#else
244
245#error "Unsupported CPU model -- are you sure you're running a 68k compiler?"
246
247#endif
248
249#ifndef ASM
250#include <rtems/score/types.h>
251#include <rtems/stdint.h>
252#endif
253
254/*
255 * OBSOLETE: Backward compatibility only - Don't use.
256 * Use __mcoldfire__ instead.
257 */
258#if defined(__mcoldfire__)
259#define M68K_COLDFIRE_ARCH      1
260#else
261#define M68K_COLDFIRE_ARCH      0
262#endif
263
264/*
265 *  Define the name of the CPU family.
266 */
267
268#if ( defined(__mcoldfire__) )
269  #define CPU_NAME "Motorola ColdFire"
270#else
271  #define CPU_NAME "Motorola MC68xxx"
272#endif
273
274#ifndef ASM
275
276#if ( defined(__mcoldfire__) )
277#define m68k_disable_interrupts( _level ) \
278   do { register uint32_t   _tmpsr = 0x0700; \
279        asm volatile ( "move.w %%sr,%0\n\t" \
280                       "or.l   %0,%1\n\t" \
281                       "move.w %1,%%sr" \
282                       : "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) \
283               : "cc" ); \
284   } while( 0 )
285#else
286#define m68k_disable_interrupts( _level ) \
287  asm volatile ( "move.w  %%sr,%0\n\t" \
288                 "or.w    #0x0700,%%sr" \
289                    : "=d" (_level) \
290                    : : "cc" )
291#endif
292
293#define m68k_enable_interrupts( _level ) \
294  asm volatile ( "move.w  %0,%%sr " : : "d" (_level) : "cc");
295
296#if ( defined(__mcoldfire__) )
297#define m68k_flash_interrupts( _level ) \
298   do { register uint32_t   _tmpsr = 0x0700; \
299        asm volatile ( "move.w %2,%%sr\n\t" \
300                       "or.l   %2,%1\n\t" \
301                       "move.w %1,%%sr" \
302                       : "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) \
303               : "cc"); \
304   } while( 0 )
305#else
306#define m68k_flash_interrupts( _level ) \
307  asm volatile ( "move.w  %0,%%sr\n\t" \
308                 "or.w    #0x0700,%%sr" \
309                    : : "d" (_level) \
310                    : "cc" )
311#endif
312
313#define m68k_get_interrupt_level( _level ) \
314  do { \
315    register uint32_t   _tmpsr; \
316    \
317    asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
318    _level = (_tmpsr & 0x0700) >> 8; \
319  } while (0)
320   
321#define m68k_set_interrupt_level( _newlevel ) \
322  do { \
323    register uint32_t   _tmpsr; \
324    \
325    asm volatile( "move.w  %%sr,%0" : "=d" (_tmpsr)); \
326    _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
327    asm volatile( "move.w  %0,%%sr" : : "d" (_tmpsr)); \
328  } while (0)
329
330#if ( M68K_HAS_VBR == 1 && !defined(__mcoldfire__) )
331#define m68k_get_vbr( vbr ) \
332  asm volatile ( "movec   %%vbr,%0 " : "=r" (vbr))
333
334#define m68k_set_vbr( vbr ) \
335  asm volatile ( "movec   %0,%%vbr " : : "r" (vbr))
336
337#elif ( defined(__mcoldfire__) )
338extern void*                     _VBR; 
339#define m68k_get_vbr( _vbr ) _vbr = &_VBR
340
341#define m68k_set_vbr( _vbr ) \
342  do { \
343    asm volatile ( "movec   %0,%%vbr " : : "r" (_vbr)); \
344    _VBR = (void *)_vbr; \
345  } while(0)
346 
347#else
348#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
349#define m68k_set_vbr( _vbr )
350#endif
351
352/*
353 *  The following routine swaps the endian format of an unsigned int.
354 *  It must be static because it is referenced indirectly.
355 */
356#if ( defined(__mcoldfire__) )
357
358/* There are no rotate commands in Coldfire architecture. We will use
359 * generic implementation of endian swapping for Coldfire.
360 */
361static inline uint32_t m68k_swap_u32(
362  uint32_t value
363  )
364{
365  uint32_t   byte1, byte2, byte3, byte4, swapped;
366   
367  byte4 = (value >> 24) & 0xff;
368  byte3 = (value >> 16) & 0xff;
369  byte2 = (value >> 8)  & 0xff;
370  byte1 =  value        & 0xff;
371           
372  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
373  return( swapped );
374}
375 
376static inline uint16_t m68k_swap_u16(
377  uint16_t value
378)
379{
380  return (((value & 0xff) << 8) | ((value >> 8) & 0xff));
381}
382                 
383#else
384
385static inline uint32_t m68k_swap_u32(
386  uint32_t value
387)
388{
389  uint32_t swapped = value;
390
391  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
392  asm volatile( "swap  %0"    : "=d" (swapped) : "0" (swapped) );
393  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
394
395  return( swapped );
396}
397
398static inline uint16_t m68k_swap_u16(
399  uint16_t value
400)
401{
402  uint16_t swapped = value;
403
404  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
405
406  return( swapped );
407}
408#endif
409
410#define CPU_swap_u32( value )  m68k_swap_u32( value )
411#define CPU_swap_u16( value )  m68k_swap_u16( value )
412
413
414/*
415 *  _CPU_virtual_to_physical
416 *
417 *  DESCRIPTION:
418 *
419 *      This function is used to map virtual addresses to physical
420 *      addresses.
421 *
422 *      FIXME: ASSUMES THAT VIRTUAL ADDRESSES ARE THE SAME AS THE
423 *      PHYSICAL ADDRESSES
424 */
425static inline void * _CPU_virtual_to_physical (
426  const void * d_addr )
427{
428  return (void *) d_addr;
429}
430
431
432#endif  /* !ASM */
433
434#ifdef __cplusplus
435}
436#endif
437
438#endif /* _RTEMS_SCORE_M68K_H */
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