source: rtems/cpukit/score/cpu/m68k/rtems/score/m68k.h @ 544a600

4.104.114.84.9
Last change on this file since 544a600 was 544a600, checked in by Joel Sherrill <joel.sherrill@…>, on Mar 15, 2002 at 1:56:21 PM

2002-03-15 Ralf Corsepius <corsepiu@…>

  • rtems/score/m68k.h: m68k_swap_u32 fix typo.
  • Property mode set to 100644
File size: 11.6 KB
Line 
1/*  m68k.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef __M68k_h
17#define __M68k_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23/*
24 *  This section contains the information required to build
25 *  RTEMS for a particular member of the Motorola MC68xxx
26 *  family.  It does this by setting variables to indicate
27 *  which implementation dependent features are present in
28 *  a particular member of the family.
29 *
30 *  Currently recognized:
31 *     -m68000
32 *     -m68000 -msoft-float
33 *     -m68020
34 *     -m68020 -msoft-float
35 *     -m68030
36 *     -m68040 -msoft-float
37 *     -m68040
38 *     -m68040 -msoft-float
39 *     -m68060
40 *     -m68060 -msoft-float
41 *     -m68302        (no FP) (deprecated, use -m68000)
42 *     -m68332        (no FP) (deprecated, use -mcpu32)
43 *     -mcpu32        (no FP)
44 *     -m5200         (no FP)
45 *
46 *  As of gcc 2.8.1 and egcs 1.1, there is no distinction made between
47 *  the CPU32 and CPU32+.  The option -mcpu32 generates code which can
48 *  be run on either core.  RTEMS distinguishes between these two cores
49 *  because they have different alignment rules which impact performance.
50 *  If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should
51 *  be defined in your custom file (see make/custom/gen68360.cfg for an
52 *  example of how to do this.  If gcc ever distinguishes between these
53 *  two cores, then RTEMS__mcpu32p__ usage will be replaced with the
54 *  appropriate compiler defined predefine.
55 *
56 *  Here is some information on the 040 variants (courtesy of Doug McBride,
57 *  mcbride@rodin.colorado.edu):
58 *
59 *    "The 68040 is a superset of the 68EC040 and the 68LC040.  The
60 *    68EC040 and 68LC040 do not have FPU's.  The 68LC040 and the
61 *    68EC040 have renamed the DLE pin as JS0 which must be tied to
62 *    Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1.  The
63 *    68EC040 has access control units instead of memory management units.
64 *    The 68EC040 should not have the PFLUSH or PTEST instructions executed
65 *    (cause an indeterminate result).  The 68EC040 and 68LC040 do not
66 *    implement the DLE or multiplexed bus modes.  The 68EC040 does not
67 *    implement the output buffer impedance selection mode of operation."
68 *
69 *  M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
70 *  which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
71 *  68010, 68302, 68306, 68307).  This instruction is available on the 68020
72 *  up and the cpu32 based models. 
73 *
74 *  M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned
75 *  data access (68020, 68030, 68040, 68060, CPU32+).
76 *
77 *  NOTE:
78 *    Eventually it would be nice to evaluate doing a lot of this section
79 *    by having each model specify which core it uses and then go from there.
80 */
81
82/*
83 *  Figure out all CPU Model Feature Flags based upon compiler
84 *  predefines.   Notice the only exception to this is that
85 *  gcc does not distinguish between CPU32 and CPU32+.  This
86 *  feature selection logic is setup such that if RTEMS__mcpu32p__
87 *  is defined, then CPU32+ rules are used.  Otherwise, the safe
88 *  but less efficient CPU32 rules are used for the CPU32+.
89 */
90
91#if defined(__mc68020__)
92 
93#define CPU_MODEL_NAME          "m68020"
94#define M68K_HAS_VBR             1
95#define M68K_HAS_SEPARATE_STACKS 1
96#define M68K_HAS_BFFFO           1
97#define M68K_HAS_PREINDEXING     1
98#define M68K_HAS_EXTB_L          1
99#define M68K_HAS_MISALIGNED      1
100# if defined (__HAVE_68881__)
101# define M68K_HAS_FPU            1
102# define M68K_HAS_FPSP_PACKAGE   0
103# else
104# define M68K_HAS_FPU            0
105# define M68K_HAS_FPSP_PACKAGE   0
106# endif
107 
108#elif defined(__mc68030__)
109 
110#define CPU_MODEL_NAME          "m68030"
111#define M68K_HAS_VBR             1
112#define M68K_HAS_SEPARATE_STACKS 1
113#define M68K_HAS_BFFFO           1
114#define M68K_HAS_PREINDEXING     1
115#define M68K_HAS_EXTB_L          1
116#define M68K_HAS_MISALIGNED      1
117# if defined (__HAVE_68881__)
118# define M68K_HAS_FPU            1
119# define M68K_HAS_FPSP_PACKAGE   0
120# else
121# define M68K_HAS_FPU            0
122# define M68K_HAS_FPSP_PACKAGE   0
123# endif
124 
125#elif defined(__mc68040__)
126
127#define CPU_MODEL_NAME          "m68040"
128#define M68K_HAS_VBR             1
129#define M68K_HAS_SEPARATE_STACKS 1
130#define M68K_HAS_BFFFO           1
131#define M68K_HAS_PREINDEXING     1
132#define M68K_HAS_EXTB_L          1
133#define M68K_HAS_MISALIGNED      1
134# if defined (__HAVE_68881__)
135# define M68K_HAS_FPU            1
136# define M68K_HAS_FPSP_PACKAGE   1
137# else
138# define M68K_HAS_FPU            0
139# define M68K_HAS_FPSP_PACKAGE   0
140# endif
141 
142#elif defined(__mc68060__)
143
144#define CPU_MODEL_NAME          "m68060"
145#define M68K_HAS_VBR             1
146#define M68K_HAS_SEPARATE_STACKS 0
147#define M68K_HAS_BFFFO           1
148#define M68K_HAS_PREINDEXING     1
149#define M68K_HAS_EXTB_L          1
150#define M68K_HAS_MISALIGNED      1
151# if defined (__HAVE_68881__)
152# define M68K_HAS_FPU            1
153# define M68K_HAS_FPSP_PACKAGE   1
154# else
155# define M68K_HAS_FPU            0
156# define M68K_HAS_FPSP_PACKAGE   0
157# endif
158 
159#elif defined(__mc68302__)
160
161#define CPU_MODEL_NAME          "m68302"
162#define M68K_HAS_VBR             0
163#define M68K_HAS_SEPARATE_STACKS 0
164#define M68K_HAS_BFFFO           0
165#define M68K_HAS_PREINDEXING     0
166#define M68K_HAS_EXTB_L          0
167#define M68K_HAS_MISALIGNED      0
168#define M68K_HAS_FPU             0
169#define M68K_HAS_FPSP_PACKAGE    0
170
171  /* gcc and egcs do not distinguish between CPU32 and CPU32+ */
172#elif defined(RTEMS__mcpu32p__)
173 
174#define CPU_MODEL_NAME          "mcpu32+"
175#define M68K_HAS_VBR             1
176#define M68K_HAS_SEPARATE_STACKS 0
177#define M68K_HAS_BFFFO           0
178#define M68K_HAS_PREINDEXING     1
179#define M68K_HAS_EXTB_L          1
180#define M68K_HAS_MISALIGNED      1
181#define M68K_HAS_FPU             0
182#define M68K_HAS_FPSP_PACKAGE    0
183
184#elif defined(__mcpu32__)
185 
186#define CPU_MODEL_NAME          "mcpu32"
187#define M68K_HAS_VBR             1
188#define M68K_HAS_SEPARATE_STACKS 0
189#define M68K_HAS_BFFFO           0
190#define M68K_HAS_PREINDEXING     1
191#define M68K_HAS_EXTB_L          1
192#define M68K_HAS_MISALIGNED      0
193#define M68K_HAS_FPU             0
194#define M68K_HAS_FPSP_PACKAGE    0
195
196#elif defined(__mcf5200__)
197/* Motorola ColdFire V2 core - RISC/68020 hybrid */ 
198#define CPU_MODEL_NAME         "m5200"
199#define M68K_HAS_VBR             1
200#define M68K_HAS_BFFFO           0
201#define M68K_HAS_SEPARATE_STACKS 0
202#define M68K_HAS_PREINDEXING     0
203#define M68K_HAS_EXTB_L          1
204#define M68K_HAS_MISALIGNED      1
205#define M68K_HAS_FPU             0
206#define M68K_HAS_FPSP_PACKAGE    0
207#define M68K_COLDFIRE_ARCH       1
208
209#elif defined(__mc68000__)
210 
211#define CPU_MODEL_NAME          "m68000"
212#define M68K_HAS_VBR             0
213#define M68K_HAS_SEPARATE_STACKS 0
214#define M68K_HAS_BFFFO           0
215#define M68K_HAS_PREINDEXING     0
216#define M68K_HAS_EXTB_L          0
217#define M68K_HAS_MISALIGNED      0
218# if defined (__HAVE_68881__)
219# define M68K_HAS_FPU            1
220# define M68K_HAS_FPSP_PACKAGE   0
221# else
222# define M68K_HAS_FPU            0
223# define M68K_HAS_FPSP_PACKAGE   0
224# endif
225
226#else
227
228#error "Unsupported CPU model -- are you sure you're running a 68k compiler?"
229
230#endif
231
232#ifndef ASM
233#include <rtems/score/m68ktypes.h>
234#endif
235
236/*
237 *  If the above did not specify a ColdFire architecture, then set
238 *  this flag to indicate that it is not a ColdFire CPU.
239 */
240
241#if !defined(M68K_COLDFIRE_ARCH)
242#define M68K_COLDFIRE_ARCH       0
243#endif
244
245/*
246 *  Define the name of the CPU family.
247 */
248
249#if ( M68K_COLDFIRE_ARCH == 1 )
250  #define CPU_NAME "Motorola ColdFire"
251#else
252  #define CPU_NAME "Motorola MC68xxx"
253#endif
254
255#ifndef ASM
256
257#if ( M68K_COLDFIRE_ARCH == 1 )
258#define m68k_disable_interrupts( _level ) \
259   do { register unsigned32 _tmpsr = 0x0700; \
260        asm volatile ( "move.w %%sr,%0\n\t" \
261                       "or.l   %0,%1\n\t" \
262                       "move.w %1,%%sr" \
263                       : "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) ); \
264   } while( 0 )
265#else
266#define m68k_disable_interrupts( _level ) \
267  asm volatile ( "move.w  %%sr,%0\n\t" \
268                 "or.w    #0x0700,%%sr" \
269                    : "=d" (_level))
270#endif
271
272#define m68k_enable_interrupts( _level ) \
273  asm volatile ( "move.w  %0,%%sr " : : "d" (_level));
274
275#if ( M68K_COLDFIRE_ARCH == 1 )
276#define m68k_flash_interrupts( _level ) \
277   do { register unsigned32 _tmpsr = 0x0700; \
278        asm volatile ( "move.w %2,%%sr\n\t" \
279                       "or.l   %2,%1\n\t" \
280                       "move.w %1,%%sr" \
281                       : "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) ); \
282   } while( 0 )
283#else
284#define m68k_flash_interrupts( _level ) \
285  asm volatile ( "move.w  %0,%%sr\n\t" \
286                 "or.w    #0x0700,%%sr" \
287                    : : "d" (_level))
288#endif
289
290#define m68k_get_interrupt_level( _level ) \
291  do { \
292    register unsigned32 _tmpsr; \
293    \
294    asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
295    _level = (_tmpsr & 0x0700) >> 8; \
296  } while (0)
297   
298#define m68k_set_interrupt_level( _newlevel ) \
299  do { \
300    register unsigned32 _tmpsr; \
301    \
302    asm volatile( "move.w  %%sr,%0" : "=d" (_tmpsr)); \
303    _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
304    asm volatile( "move.w  %0,%%sr" : : "d" (_tmpsr)); \
305  } while (0)
306
307#if ( M68K_HAS_VBR == 1 && M68K_COLDFIRE_ARCH == 0 )
308#define m68k_get_vbr( vbr ) \
309  asm volatile ( "movec   %%vbr,%0 " : "=r" (vbr))
310
311#define m68k_set_vbr( vbr ) \
312  asm volatile ( "movec   %0,%%vbr " : : "r" (vbr))
313
314#elif ( M68K_COLDFIRE_ARCH == 1 )
315#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
316
317#define m68k_set_vbr( _vbr ) \
318    asm volatile ("move.l  %%a7,%%d1 \n\t" \
319                  "move.l  %0,%%a7\n\t"    \
320                  "movec   %%a7,%%vbr\n\t" \
321                  "move.l  %%d1,%%a7\n\t"  \
322                  : : "d" (_vbr) : "d1" );
323 
324#else
325#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
326#define m68k_set_vbr( _vbr )
327#endif
328
329/*
330 *  The following routine swaps the endian format of an unsigned int.
331 *  It must be static because it is referenced indirectly.
332 */
333#if ( M68K_COLDFIRE_ARCH == 1 )
334
335/* There are no rotate commands in Coldfire architecture. We will use
336 * generic implementation of endian swapping for Coldfire.
337 */
338static inline unsigned int m68k_swap_u32(
339  unsigned int value
340  )
341{
342  unsigned32 byte1, byte2, byte3, byte4, swapped;
343   
344  byte4 = (value >> 24) & 0xff;
345  byte3 = (value >> 16) & 0xff;
346  byte2 = (value >> 8)  & 0xff;
347  byte1 =  value        & 0xff;
348           
349  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
350  return( swapped );
351}
352 
353static inline unsigned int m68k_swap_u16(
354  unsigned int value
355)
356{
357  return (((value & 0xff) << 8) | ((value >> 8) & 0xff));
358}
359                 
360#else
361
362static inline unsigned int m68k_swap_u32(
363  unsigned int value
364)
365{
366  unsigned int swapped = value;
367
368  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
369  asm volatile( "swap  %0"    : "=d" (swapped) : "0" (swapped) );
370  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
371
372  return( swapped );
373}
374
375static inline unsigned int m68k_swap_u16(
376  unsigned int value
377)
378{
379  unsigned short swapped = value;
380
381  asm volatile( "rorw  #8,%0" : "=d" (swapped) : "0" (swapped) );
382
383  return( swapped );
384}
385#endif
386
387#define CPU_swap_u32( value )  m68k_swap_u32( value )
388#define CPU_swap_u16( value )  m68k_swap_u16( value )
389
390
391/*
392 *  _CPU_virtual_to_physical
393 *
394 *  DESCRIPTION:
395 *
396 *      This function is used to map virtual addresses to physical
397 *      addresses.
398 *
399 *      FIXME: ASSUMES THAT VIRTUAL ADDRESSES ARE THE SAME AS THE
400 *      PHYSICAL ADDRESSES
401 */
402static inline void * _CPU_virtual_to_physical (
403  const void * d_addr )
404{
405  return (void *) d_addr;
406}
407
408
409#endif  /* !ASM */
410
411#ifdef __cplusplus
412}
413#endif
414
415#endif /* __M68K_h */
416/* end of include file */
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