| 1 | /** |
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| 2 | * @file rtems/score/m68k.h |
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| 3 | */ |
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| 4 | |
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| 5 | /* |
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| 6 | * This include file contains information pertaining to the Motorola |
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| 7 | * m68xxx processor family. |
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| 8 | * |
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| 9 | * COPYRIGHT (c) 1989-1999. |
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| 10 | * On-Line Applications Research Corporation (OAR). |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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| 14 | * http://www.rtems.com/license/LICENSE. |
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| 15 | * |
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| 16 | * $Id$ |
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| 17 | */ |
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| 18 | |
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| 19 | #ifndef _RTEMS_SCORE_M68K_H |
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| 20 | #define _RTEMS_SCORE_M68K_H |
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| 21 | |
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| 22 | #ifdef __cplusplus |
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| 23 | extern "C" { |
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| 24 | #endif |
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| 25 | |
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| 26 | /* |
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| 27 | * This section contains the information required to build |
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| 28 | * RTEMS for a particular member of the Motorola MC68xxx |
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| 29 | * family. It does this by setting variables to indicate |
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| 30 | * which implementation dependent features are present in |
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| 31 | * a particular member of the family. |
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| 32 | * |
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| 33 | * Currently recognized: |
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| 34 | * -m68000 |
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| 35 | * -m68000 -msoft-float |
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| 36 | * -m68020 |
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| 37 | * -m68020 -msoft-float |
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| 38 | * -m68030 |
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| 39 | * -m68040 -msoft-float |
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| 40 | * -m68040 |
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| 41 | * -m68040 -msoft-float |
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| 42 | * -m68060 |
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| 43 | * -m68060 -msoft-float |
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| 44 | * -m68302 (no FP) (deprecated, use -m68000) |
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| 45 | * -m68332 (no FP) (deprecated, use -mcpu32) |
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| 46 | * -mcpu32 (no FP) |
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| 47 | * -m5200 (no FP) |
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| 48 | * -m528x (no FP, ISA A+) |
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| 49 | * |
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| 50 | * As of gcc 2.8.1 and egcs 1.1, there is no distinction made between |
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| 51 | * the CPU32 and CPU32+. The option -mcpu32 generates code which can |
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| 52 | * be run on either core. RTEMS distinguishes between these two cores |
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| 53 | * because they have different alignment rules which impact performance. |
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| 54 | * If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should |
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| 55 | * be defined in your custom file (see make/custom/gen68360.cfg for an |
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| 56 | * example of how to do this. If gcc ever distinguishes between these |
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| 57 | * two cores, then RTEMS__mcpu32p__ usage will be replaced with the |
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| 58 | * appropriate compiler defined predefine. |
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| 59 | * |
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| 60 | * Here is some information on the 040 variants (courtesy of Doug McBride, |
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| 61 | * mcbride@rodin.colorado.edu): |
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| 62 | * |
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| 63 | * "The 68040 is a superset of the 68EC040 and the 68LC040. The |
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| 64 | * 68EC040 and 68LC040 do not have FPU's. The 68LC040 and the |
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| 65 | * 68EC040 have renamed the DLE pin as JS0 which must be tied to |
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| 66 | * Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1. The |
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| 67 | * 68EC040 has access control units instead of memory management units. |
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| 68 | * The 68EC040 should not have the PFLUSH or PTEST instructions executed |
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| 69 | * (cause an indeterminate result). The 68EC040 and 68LC040 do not |
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| 70 | * implement the DLE or multiplexed bus modes. The 68EC040 does not |
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| 71 | * implement the output buffer impedance selection mode of operation." |
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| 72 | * |
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| 73 | * M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction |
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| 74 | * which is not available for 68000 or 68ec000 cores (68000, 68001, 68008, |
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| 75 | * 68010, 68302, 68306, 68307). This instruction is available on the 68020 |
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| 76 | * up and the cpu32 based models. |
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| 77 | * |
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| 78 | * M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned |
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| 79 | * data access (68020, 68030, 68040, 68060, CPU32+). |
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| 80 | * |
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| 81 | * NOTE: |
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| 82 | * Eventually it would be nice to evaluate doing a lot of this section |
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| 83 | * by having each model specify which core it uses and then go from there. |
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| 84 | */ |
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| 85 | |
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| 86 | /* |
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| 87 | * Handle the Coldfire family based on the instruction set. |
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| 88 | */ |
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| 89 | #if defined(__mcoldfire__) |
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| 90 | |
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| 91 | # define CPU_NAME "Motorola ColdFire" |
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| 92 | |
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| 93 | # if defined(__mcfisaa__) |
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| 94 | /* Motorola ColdFire ISA A */ |
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| 95 | # define CPU_MODEL_NAME "mcfisaa" |
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| 96 | # define M68K_HAS_VBR 1 |
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| 97 | # define M68K_HAS_BFFFO 0 |
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| 98 | # define M68K_HAS_SEPARATE_STACKS 0 |
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| 99 | # define M68K_HAS_PREINDEXING 0 |
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| 100 | # define M68K_HAS_EXTB_L 1 |
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| 101 | # define M68K_HAS_MISALIGNED 1 |
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| 102 | |
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| 103 | # elif defined(__mcfisaaplus__) |
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| 104 | /* Motorola ColdFire ISA A+ */ |
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| 105 | # define CPU_MODEL_NAME "mcfisaaplus" |
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| 106 | # define M68K_HAS_VBR 1 |
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| 107 | # define M68K_HAS_BFFFO 0 |
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| 108 | # define M68K_HAS_SEPARATE_STACKS 0 |
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| 109 | # define M68K_HAS_PREINDEXING 0 |
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| 110 | # define M68K_HAS_EXTB_L 1 |
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| 111 | # define M68K_HAS_MISALIGNED 1 |
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| 112 | |
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| 113 | # elif defined(__mcfisab__) |
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| 114 | /* Motorola ColdFire ISA B */ |
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| 115 | # define CPU_MODEL_NAME "mcfisab" |
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| 116 | # define M68K_HAS_VBR 1 |
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| 117 | # define M68K_HAS_BFFFO 0 |
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| 118 | # define M68K_HAS_SEPARATE_STACKS 0 |
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| 119 | # define M68K_HAS_PREINDEXING 0 |
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| 120 | # define M68K_HAS_EXTB_L 1 |
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| 121 | # define M68K_HAS_MISALIGNED 1 |
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| 122 | |
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| 123 | # else |
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| 124 | # error "Unsupported Coldfire ISA -- Please notify RTEMS" |
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| 125 | # endif |
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| 126 | |
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| 127 | /* |
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| 128 | * Assume the FPU support is independent. I think it is just the ISA B |
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| 129 | * instruction set. |
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| 130 | */ |
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| 131 | # if defined (__mcffpu__) |
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| 132 | # define M68K_HAS_FPU 1 |
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| 133 | /* |
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| 134 | * td: can we be sure that all CFs with FPU also have an EMAC? |
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| 135 | */ |
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| 136 | # define M68K_HAS_EMAC 1 |
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| 137 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 138 | # else |
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| 139 | # define M68K_HAS_FPU 0 |
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| 140 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 141 | # endif |
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| 142 | |
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| 143 | /* |
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| 144 | * Tiny RTEMS support. Small stack and limited priorities. |
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| 145 | * |
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| 146 | * These CPUs have very limited on-CPU memory which cannot |
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| 147 | * be expanded. We have to be gentle with them or nothing |
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| 148 | * will every run. |
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| 149 | */ |
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| 150 | # if (defined(__mcf_cpu_52221) || \ |
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| 151 | defined(__mcf_cpu_52223) || \ |
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| 152 | defined(__mcf_cpu_52230) || \ |
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| 153 | defined(__mcf_cpu_52231) || \ |
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| 154 | defined(__mcf_cpu_52232) || \ |
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| 155 | defined(__mcf_cpu_52233) || \ |
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| 156 | defined(__mcf_cpu_52234) || \ |
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| 157 | defined(__mcf_cpu_52235) || \ |
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| 158 | defined(__mcf_cpu_52225) || \ |
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| 159 | defined(__mcf_cpu_52235)) |
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| 160 | #define M68K_CPU_STACK_MINIMUM_SIZE 1024 |
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| 161 | /* Define the lowest priority. Based from 0 to this is 16 levels. */ |
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| 162 | #define M68K_CPU_PRIORITY_MAXIMUM 15 |
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| 163 | # else |
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| 164 | #define M68K_CPU_STACK_MINIMUM_SIZE 4096 |
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| 165 | /* Use the default number of priorities */ |
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| 166 | #define M68K_CPU_PRIORITY_MAXIMUM 255 |
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| 167 | # endif |
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| 168 | |
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| 169 | #else |
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| 170 | |
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| 171 | /* |
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| 172 | * Figure out all CPU Model Feature Flags based upon compiler |
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| 173 | * predefines. Notice the only exception to this is that |
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| 174 | * gcc does not distinguish between CPU32 and CPU32+. This |
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| 175 | * feature selection logic is setup such that if RTEMS__mcpu32p__ |
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| 176 | * is defined, then CPU32+ rules are used. Otherwise, the safe |
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| 177 | * but less efficient CPU32 rules are used for the CPU32+. |
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| 178 | */ |
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| 179 | |
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| 180 | # define CPU_NAME "Motorola MC68xxx" |
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| 181 | |
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| 182 | /* |
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| 183 | * One stack size fits all 68000 processors. |
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| 184 | */ |
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| 185 | # define M68K_CPU_STACK_MINIMUM_SIZE 4096 |
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| 186 | |
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| 187 | # if (defined(__mc68020__) && !defined(__mcpu32__)) |
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| 188 | |
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| 189 | # define CPU_MODEL_NAME "m68020" |
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| 190 | # define M68K_HAS_VBR 1 |
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| 191 | # define M68K_HAS_SEPARATE_STACKS 1 |
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| 192 | # define M68K_HAS_BFFFO 1 |
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| 193 | # define M68K_HAS_PREINDEXING 1 |
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| 194 | # define M68K_HAS_EXTB_L 1 |
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| 195 | # define M68K_HAS_MISALIGNED 1 |
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| 196 | # if defined (__HAVE_68881__) |
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| 197 | # define M68K_HAS_FPU 1 |
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| 198 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 199 | # else |
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| 200 | # define M68K_HAS_FPU 0 |
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| 201 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 202 | # endif |
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| 203 | |
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| 204 | # elif defined(__mc68030__) |
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| 205 | |
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| 206 | # define CPU_MODEL_NAME "m68030" |
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| 207 | # define M68K_HAS_VBR 1 |
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| 208 | # define M68K_HAS_SEPARATE_STACKS 1 |
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| 209 | # define M68K_HAS_BFFFO 1 |
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| 210 | # define M68K_HAS_PREINDEXING 1 |
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| 211 | # define M68K_HAS_EXTB_L 1 |
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| 212 | # define M68K_HAS_MISALIGNED 1 |
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| 213 | # if defined (__HAVE_68881__) |
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| 214 | # define M68K_HAS_FPU 1 |
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| 215 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 216 | # else |
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| 217 | # define M68K_HAS_FPU 0 |
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| 218 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 219 | # endif |
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| 220 | |
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| 221 | # elif defined(__mc68040__) |
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| 222 | |
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| 223 | # define CPU_MODEL_NAME "m68040" |
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| 224 | # define M68K_HAS_VBR 1 |
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| 225 | # define M68K_HAS_SEPARATE_STACKS 1 |
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| 226 | # define M68K_HAS_BFFFO 1 |
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| 227 | # define M68K_HAS_PREINDEXING 1 |
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| 228 | # define M68K_HAS_EXTB_L 1 |
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| 229 | # define M68K_HAS_MISALIGNED 1 |
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| 230 | # if defined (__HAVE_68881__) |
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| 231 | # define M68K_HAS_FPU 1 |
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| 232 | # define M68K_HAS_FPSP_PACKAGE 1 |
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| 233 | # else |
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| 234 | # define M68K_HAS_FPU 0 |
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| 235 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 236 | # endif |
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| 237 | |
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| 238 | # elif defined(__mc68060__) |
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| 239 | |
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| 240 | # define CPU_MODEL_NAME "m68060" |
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| 241 | # define M68K_HAS_VBR 1 |
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| 242 | # define M68K_HAS_SEPARATE_STACKS 0 |
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| 243 | # define M68K_HAS_BFFFO 1 |
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| 244 | # define M68K_HAS_PREINDEXING 1 |
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| 245 | # define M68K_HAS_EXTB_L 1 |
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| 246 | # define M68K_HAS_MISALIGNED 1 |
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| 247 | # if defined (__HAVE_68881__) |
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| 248 | # define M68K_HAS_FPU 1 |
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| 249 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 250 | # else |
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| 251 | # define M68K_HAS_FPU 0 |
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| 252 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 253 | # endif |
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| 254 | |
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| 255 | # elif defined(__mc68302__) |
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| 256 | |
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| 257 | # define CPU_MODEL_NAME "m68302" |
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| 258 | # define M68K_HAS_VBR 0 |
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| 259 | # define M68K_HAS_SEPARATE_STACKS 0 |
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| 260 | # define M68K_HAS_BFFFO 0 |
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| 261 | # define M68K_HAS_PREINDEXING 0 |
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| 262 | # define M68K_HAS_EXTB_L 0 |
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| 263 | # define M68K_HAS_MISALIGNED 0 |
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| 264 | # define M68K_HAS_FPU 0 |
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| 265 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 266 | |
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| 267 | /* gcc and egcs do not distinguish between CPU32 and CPU32+ */ |
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| 268 | # elif defined(RTEMS__mcpu32p__) |
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| 269 | |
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| 270 | # define CPU_MODEL_NAME "mcpu32+" |
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| 271 | # define M68K_HAS_VBR 1 |
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| 272 | # define M68K_HAS_SEPARATE_STACKS 0 |
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| 273 | # define M68K_HAS_BFFFO 0 |
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| 274 | # define M68K_HAS_PREINDEXING 1 |
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| 275 | # define M68K_HAS_EXTB_L 1 |
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| 276 | # define M68K_HAS_MISALIGNED 1 |
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| 277 | # define M68K_HAS_FPU 0 |
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| 278 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 279 | |
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| 280 | # elif defined(__mcpu32__) |
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| 281 | |
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| 282 | # define CPU_MODEL_NAME "mcpu32" |
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| 283 | # define M68K_HAS_VBR 1 |
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| 284 | # define M68K_HAS_SEPARATE_STACKS 0 |
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| 285 | # define M68K_HAS_BFFFO 0 |
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| 286 | # define M68K_HAS_PREINDEXING 1 |
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| 287 | # define M68K_HAS_EXTB_L 1 |
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| 288 | # define M68K_HAS_MISALIGNED 0 |
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| 289 | # define M68K_HAS_FPU 0 |
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| 290 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 291 | |
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| 292 | # elif defined(__mc68000__) |
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| 293 | |
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| 294 | # define CPU_MODEL_NAME "m68000" |
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| 295 | # define M68K_HAS_VBR 0 |
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| 296 | # define M68K_HAS_SEPARATE_STACKS 0 |
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| 297 | # define M68K_HAS_BFFFO 0 |
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| 298 | # define M68K_HAS_PREINDEXING 0 |
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| 299 | # define M68K_HAS_EXTB_L 0 |
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| 300 | # define M68K_HAS_MISALIGNED 0 |
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| 301 | # if defined (__HAVE_68881__) |
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| 302 | # define M68K_HAS_FPU 1 |
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| 303 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 304 | # else |
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| 305 | # define M68K_HAS_FPU 0 |
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| 306 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 307 | # endif |
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| 308 | |
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| 309 | # else |
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| 310 | |
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| 311 | # error "Unsupported 68000 CPU model -- are you sure you're running a 68k compiler?" |
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| 312 | |
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| 313 | # endif |
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| 314 | |
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| 315 | /* |
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| 316 | * No Tiny RTEMS support on the standard 68000 family. |
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| 317 | */ |
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| 318 | # define M68K_CPU_STACK_MINIMUM_SIZE 4096 |
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| 319 | # define M68K_CPU_PRIORITY_MAXIMUM 255 |
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| 320 | |
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| 321 | #endif |
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| 322 | |
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| 323 | #ifndef ASM |
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| 324 | #include <rtems/score/types.h> |
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| 325 | #include <rtems/stdint.h> |
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| 326 | #endif |
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| 327 | |
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| 328 | /* |
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| 329 | * OBSOLETE: Backward compatibility only - Don't use. |
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| 330 | * Use __mcoldfire__ instead. |
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| 331 | */ |
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| 332 | #if defined(__mcoldfire__) |
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| 333 | #define M68K_COLDFIRE_ARCH 1 |
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| 334 | #else |
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| 335 | #define M68K_COLDFIRE_ARCH 0 |
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| 336 | #endif |
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| 337 | |
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| 338 | #ifndef ASM |
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| 339 | |
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| 340 | #if ( defined(__mcoldfire__) ) |
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| 341 | #define m68k_disable_interrupts( _level ) \ |
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| 342 | do { register uint32_t _tmpsr = 0x0700; \ |
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| 343 | asm volatile ( "move.w %%sr,%0\n\t" \ |
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| 344 | "or.l %0,%1\n\t" \ |
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| 345 | "move.w %1,%%sr" \ |
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| 346 | : "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) \ |
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| 347 | : "cc" ); \ |
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| 348 | } while( 0 ) |
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| 349 | #else |
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| 350 | #define m68k_disable_interrupts( _level ) \ |
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| 351 | asm volatile ( "move.w %%sr,%0\n\t" \ |
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| 352 | "or.w #0x0700,%%sr" \ |
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| 353 | : "=d" (_level) \ |
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| 354 | : : "cc" ) |
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| 355 | #endif |
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| 356 | |
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| 357 | #define m68k_enable_interrupts( _level ) \ |
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| 358 | asm volatile ( "move.w %0,%%sr " : : "d" (_level) : "cc"); |
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| 359 | |
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| 360 | #if ( defined(__mcoldfire__) ) |
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| 361 | #define m68k_flash_interrupts( _level ) \ |
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| 362 | do { register uint32_t _tmpsr = 0x0700; \ |
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| 363 | asm volatile ( "move.w %2,%%sr\n\t" \ |
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| 364 | "or.l %2,%1\n\t" \ |
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| 365 | "move.w %1,%%sr" \ |
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| 366 | : "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) \ |
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| 367 | : "cc"); \ |
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| 368 | } while( 0 ) |
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| 369 | #else |
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| 370 | #define m68k_flash_interrupts( _level ) \ |
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| 371 | asm volatile ( "move.w %0,%%sr\n\t" \ |
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| 372 | "or.w #0x0700,%%sr" \ |
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| 373 | : : "d" (_level) \ |
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| 374 | : "cc" ) |
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| 375 | #endif |
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| 376 | |
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| 377 | #define m68k_get_interrupt_level( _level ) \ |
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| 378 | do { \ |
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| 379 | register uint32_t _tmpsr; \ |
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| 380 | \ |
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| 381 | asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ |
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| 382 | _level = (_tmpsr & 0x0700) >> 8; \ |
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| 383 | } while (0) |
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| 384 | |
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| 385 | #define m68k_set_interrupt_level( _newlevel ) \ |
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| 386 | do { \ |
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| 387 | register uint32_t _tmpsr; \ |
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| 388 | \ |
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| 389 | asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ |
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| 390 | _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \ |
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| 391 | asm volatile( "move.w %0,%%sr" : : "d" (_tmpsr)); \ |
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| 392 | } while (0) |
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| 393 | |
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| 394 | #if ( M68K_HAS_VBR == 1 && !defined(__mcoldfire__) ) |
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| 395 | #define m68k_get_vbr( vbr ) \ |
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| 396 | asm volatile ( "movec %%vbr,%0 " : "=r" (vbr)) |
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| 397 | |
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| 398 | #define m68k_set_vbr( vbr ) \ |
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| 399 | asm volatile ( "movec %0,%%vbr " : : "r" (vbr)) |
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| 400 | |
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| 401 | #elif ( defined(__mcoldfire__) ) |
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| 402 | extern void* _VBR; |
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| 403 | #define m68k_get_vbr( _vbr ) _vbr = &_VBR |
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| 404 | |
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| 405 | #define m68k_set_vbr( _vbr ) \ |
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| 406 | do { \ |
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| 407 | asm volatile ( "movec %0,%%vbr " : : "r" (_vbr)); \ |
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| 408 | _VBR = (void *)_vbr; \ |
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| 409 | } while(0) |
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| 410 | |
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| 411 | #else |
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| 412 | #define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR |
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| 413 | #define m68k_set_vbr( _vbr ) |
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| 414 | #endif |
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| 415 | |
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| 416 | /* |
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| 417 | * Access Control Registers |
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| 418 | */ |
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| 419 | #define m68k_set_cacr(_cacr) asm volatile ("movec %0,%%cacr" : : "d" (_cacr)) |
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| 420 | #define m68k_set_acr0(_acr0) asm volatile ("movec %0,%%acr0" : : "d" (_acr0)) |
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| 421 | #define m68k_set_acr1(_acr1) asm volatile ("movec %0,%%acr1" : : "d" (_acr1)) |
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| 422 | |
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| 423 | /* |
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| 424 | * The following routine swaps the endian format of an unsigned int. |
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| 425 | * It must be static because it is referenced indirectly. |
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| 426 | */ |
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| 427 | #if ( defined(__mcoldfire__) ) |
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| 428 | |
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| 429 | /* There are no rotate commands in Coldfire architecture. We will use |
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| 430 | * generic implementation of endian swapping for Coldfire. |
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| 431 | */ |
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| 432 | static inline uint32_t m68k_swap_u32( |
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| 433 | uint32_t value |
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| 434 | ) |
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| 435 | { |
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| 436 | uint32_t byte1, byte2, byte3, byte4, swapped; |
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| 437 | |
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| 438 | byte4 = (value >> 24) & 0xff; |
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| 439 | byte3 = (value >> 16) & 0xff; |
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| 440 | byte2 = (value >> 8) & 0xff; |
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| 441 | byte1 = value & 0xff; |
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| 442 | |
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| 443 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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| 444 | return( swapped ); |
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| 445 | } |
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| 446 | |
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| 447 | static inline uint16_t m68k_swap_u16( |
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| 448 | uint16_t value |
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| 449 | ) |
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| 450 | { |
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| 451 | return (((value & 0xff) << 8) | ((value >> 8) & 0xff)); |
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| 452 | } |
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| 453 | |
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| 454 | #else |
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| 455 | |
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| 456 | static inline uint32_t m68k_swap_u32( |
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| 457 | uint32_t value |
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| 458 | ) |
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| 459 | { |
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| 460 | uint32_t swapped = value; |
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| 461 | |
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| 462 | asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); |
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| 463 | asm volatile( "swap %0" : "=d" (swapped) : "0" (swapped) ); |
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| 464 | asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); |
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| 465 | |
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| 466 | return( swapped ); |
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| 467 | } |
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| 468 | |
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| 469 | static inline uint16_t m68k_swap_u16( |
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| 470 | uint16_t value |
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| 471 | ) |
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| 472 | { |
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| 473 | uint16_t swapped = value; |
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| 474 | |
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| 475 | asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); |
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| 476 | |
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| 477 | return( swapped ); |
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| 478 | } |
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| 479 | #endif |
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| 480 | |
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| 481 | #define CPU_swap_u32( value ) m68k_swap_u32( value ) |
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| 482 | #define CPU_swap_u16( value ) m68k_swap_u16( value ) |
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| 483 | |
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| 484 | |
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| 485 | /* |
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| 486 | * _CPU_virtual_to_physical |
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| 487 | * |
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| 488 | * DESCRIPTION: |
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| 489 | * |
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| 490 | * This function is used to map virtual addresses to physical |
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| 491 | * addresses. |
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| 492 | * |
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| 493 | * FIXME: ASSUMES THAT VIRTUAL ADDRESSES ARE THE SAME AS THE |
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| 494 | * PHYSICAL ADDRESSES |
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| 495 | */ |
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| 496 | static inline void * _CPU_virtual_to_physical ( |
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| 497 | const void * d_addr ) |
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| 498 | { |
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| 499 | return (void *) d_addr; |
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| 500 | } |
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| 501 | |
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| 502 | |
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| 503 | #endif /* !ASM */ |
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| 504 | |
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| 505 | #ifdef __cplusplus |
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| 506 | } |
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| 507 | #endif |
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| 508 | |
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| 509 | #endif /* _RTEMS_SCORE_M68K_H */ |
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