| 1 | /** |
|---|
| 2 | * @file rtems/score/m68k.h |
|---|
| 3 | */ |
|---|
| 4 | |
|---|
| 5 | /* |
|---|
| 6 | * This include file contains information pertaining to the Motorola |
|---|
| 7 | * m68xxx processor family. |
|---|
| 8 | * |
|---|
| 9 | * COPYRIGHT (c) 1989-1999. |
|---|
| 10 | * On-Line Applications Research Corporation (OAR). |
|---|
| 11 | * |
|---|
| 12 | * The license and distribution terms for this file may be |
|---|
| 13 | * found in the file LICENSE in this distribution or at |
|---|
| 14 | * http://www.rtems.com/license/LICENSE. |
|---|
| 15 | * |
|---|
| 16 | * $Id$ |
|---|
| 17 | */ |
|---|
| 18 | |
|---|
| 19 | #ifndef _RTEMS_SCORE_M68K_H |
|---|
| 20 | #define _RTEMS_SCORE_M68K_H |
|---|
| 21 | |
|---|
| 22 | #ifdef __cplusplus |
|---|
| 23 | extern "C" { |
|---|
| 24 | #endif |
|---|
| 25 | |
|---|
| 26 | /* |
|---|
| 27 | * This section contains the information required to build |
|---|
| 28 | * RTEMS for a particular member of the Motorola MC68xxx |
|---|
| 29 | * family. It does this by setting variables to indicate |
|---|
| 30 | * which implementation dependent features are present in |
|---|
| 31 | * a particular member of the family. |
|---|
| 32 | * |
|---|
| 33 | * Currently recognized: |
|---|
| 34 | * -m68000 |
|---|
| 35 | * -m68000 -msoft-float |
|---|
| 36 | * -m68020 |
|---|
| 37 | * -m68020 -msoft-float |
|---|
| 38 | * -m68030 |
|---|
| 39 | * -m68040 -msoft-float |
|---|
| 40 | * -m68040 |
|---|
| 41 | * -m68040 -msoft-float |
|---|
| 42 | * -m68060 |
|---|
| 43 | * -m68060 -msoft-float |
|---|
| 44 | * -m68302 (no FP) (deprecated, use -m68000) |
|---|
| 45 | * -m68332 (no FP) (deprecated, use -mcpu32) |
|---|
| 46 | * -mcpu32 (no FP) |
|---|
| 47 | * -m5200 (no FP) |
|---|
| 48 | * -m528x (no FP, ISA A+) |
|---|
| 49 | * |
|---|
| 50 | * As of gcc 2.8.1 and egcs 1.1, there is no distinction made between |
|---|
| 51 | * the CPU32 and CPU32+. The option -mcpu32 generates code which can |
|---|
| 52 | * be run on either core. RTEMS distinguishes between these two cores |
|---|
| 53 | * because they have different alignment rules which impact performance. |
|---|
| 54 | * If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should |
|---|
| 55 | * be defined in your custom file (see make/custom/gen68360.cfg for an |
|---|
| 56 | * example of how to do this. If gcc ever distinguishes between these |
|---|
| 57 | * two cores, then RTEMS__mcpu32p__ usage will be replaced with the |
|---|
| 58 | * appropriate compiler defined predefine. |
|---|
| 59 | * |
|---|
| 60 | * Here is some information on the 040 variants (courtesy of Doug McBride, |
|---|
| 61 | * mcbride@rodin.colorado.edu): |
|---|
| 62 | * |
|---|
| 63 | * "The 68040 is a superset of the 68EC040 and the 68LC040. The |
|---|
| 64 | * 68EC040 and 68LC040 do not have FPU's. The 68LC040 and the |
|---|
| 65 | * 68EC040 have renamed the DLE pin as JS0 which must be tied to |
|---|
| 66 | * Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1. The |
|---|
| 67 | * 68EC040 has access control units instead of memory management units. |
|---|
| 68 | * The 68EC040 should not have the PFLUSH or PTEST instructions executed |
|---|
| 69 | * (cause an indeterminate result). The 68EC040 and 68LC040 do not |
|---|
| 70 | * implement the DLE or multiplexed bus modes. The 68EC040 does not |
|---|
| 71 | * implement the output buffer impedance selection mode of operation." |
|---|
| 72 | * |
|---|
| 73 | * M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction |
|---|
| 74 | * which is not available for 68000 or 68ec000 cores (68000, 68001, 68008, |
|---|
| 75 | * 68010, 68302, 68306, 68307). This instruction is available on the 68020 |
|---|
| 76 | * up and the cpu32 based models. |
|---|
| 77 | * |
|---|
| 78 | * M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned |
|---|
| 79 | * data access (68020, 68030, 68040, 68060, CPU32+). |
|---|
| 80 | * |
|---|
| 81 | * NOTE: |
|---|
| 82 | * Eventually it would be nice to evaluate doing a lot of this section |
|---|
| 83 | * by having each model specify which core it uses and then go from there. |
|---|
| 84 | */ |
|---|
| 85 | |
|---|
| 86 | /* |
|---|
| 87 | * Figure out all CPU Model Feature Flags based upon compiler |
|---|
| 88 | * predefines. Notice the only exception to this is that |
|---|
| 89 | * gcc does not distinguish between CPU32 and CPU32+. This |
|---|
| 90 | * feature selection logic is setup such that if RTEMS__mcpu32p__ |
|---|
| 91 | * is defined, then CPU32+ rules are used. Otherwise, the safe |
|---|
| 92 | * but less efficient CPU32 rules are used for the CPU32+. |
|---|
| 93 | */ |
|---|
| 94 | |
|---|
| 95 | #if (defined(__mc68020__) && !defined(__mcpu32__)) |
|---|
| 96 | |
|---|
| 97 | #define CPU_MODEL_NAME "m68020" |
|---|
| 98 | #define M68K_HAS_VBR 1 |
|---|
| 99 | #define M68K_HAS_SEPARATE_STACKS 1 |
|---|
| 100 | #define M68K_HAS_BFFFO 1 |
|---|
| 101 | #define M68K_HAS_PREINDEXING 1 |
|---|
| 102 | #define M68K_HAS_EXTB_L 1 |
|---|
| 103 | #define M68K_HAS_MISALIGNED 1 |
|---|
| 104 | # if defined (__HAVE_68881__) |
|---|
| 105 | # define M68K_HAS_FPU 1 |
|---|
| 106 | # define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 107 | # else |
|---|
| 108 | # define M68K_HAS_FPU 0 |
|---|
| 109 | # define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 110 | # endif |
|---|
| 111 | |
|---|
| 112 | #elif defined(__mc68030__) |
|---|
| 113 | |
|---|
| 114 | #define CPU_MODEL_NAME "m68030" |
|---|
| 115 | #define M68K_HAS_VBR 1 |
|---|
| 116 | #define M68K_HAS_SEPARATE_STACKS 1 |
|---|
| 117 | #define M68K_HAS_BFFFO 1 |
|---|
| 118 | #define M68K_HAS_PREINDEXING 1 |
|---|
| 119 | #define M68K_HAS_EXTB_L 1 |
|---|
| 120 | #define M68K_HAS_MISALIGNED 1 |
|---|
| 121 | # if defined (__HAVE_68881__) |
|---|
| 122 | # define M68K_HAS_FPU 1 |
|---|
| 123 | # define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 124 | # else |
|---|
| 125 | # define M68K_HAS_FPU 0 |
|---|
| 126 | # define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 127 | # endif |
|---|
| 128 | |
|---|
| 129 | #elif defined(__mc68040__) |
|---|
| 130 | |
|---|
| 131 | #define CPU_MODEL_NAME "m68040" |
|---|
| 132 | #define M68K_HAS_VBR 1 |
|---|
| 133 | #define M68K_HAS_SEPARATE_STACKS 1 |
|---|
| 134 | #define M68K_HAS_BFFFO 1 |
|---|
| 135 | #define M68K_HAS_PREINDEXING 1 |
|---|
| 136 | #define M68K_HAS_EXTB_L 1 |
|---|
| 137 | #define M68K_HAS_MISALIGNED 1 |
|---|
| 138 | # if defined (__HAVE_68881__) |
|---|
| 139 | # define M68K_HAS_FPU 1 |
|---|
| 140 | # define M68K_HAS_FPSP_PACKAGE 1 |
|---|
| 141 | # else |
|---|
| 142 | # define M68K_HAS_FPU 0 |
|---|
| 143 | # define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 144 | # endif |
|---|
| 145 | |
|---|
| 146 | #elif defined(__mc68060__) |
|---|
| 147 | |
|---|
| 148 | #define CPU_MODEL_NAME "m68060" |
|---|
| 149 | #define M68K_HAS_VBR 1 |
|---|
| 150 | #define M68K_HAS_SEPARATE_STACKS 0 |
|---|
| 151 | #define M68K_HAS_BFFFO 1 |
|---|
| 152 | #define M68K_HAS_PREINDEXING 1 |
|---|
| 153 | #define M68K_HAS_EXTB_L 1 |
|---|
| 154 | #define M68K_HAS_MISALIGNED 1 |
|---|
| 155 | # if defined (__HAVE_68881__) |
|---|
| 156 | # define M68K_HAS_FPU 1 |
|---|
| 157 | # define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 158 | # else |
|---|
| 159 | # define M68K_HAS_FPU 0 |
|---|
| 160 | # define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 161 | # endif |
|---|
| 162 | |
|---|
| 163 | #elif defined(__mc68302__) |
|---|
| 164 | |
|---|
| 165 | #define CPU_MODEL_NAME "m68302" |
|---|
| 166 | #define M68K_HAS_VBR 0 |
|---|
| 167 | #define M68K_HAS_SEPARATE_STACKS 0 |
|---|
| 168 | #define M68K_HAS_BFFFO 0 |
|---|
| 169 | #define M68K_HAS_PREINDEXING 0 |
|---|
| 170 | #define M68K_HAS_EXTB_L 0 |
|---|
| 171 | #define M68K_HAS_MISALIGNED 0 |
|---|
| 172 | #define M68K_HAS_FPU 0 |
|---|
| 173 | #define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 174 | |
|---|
| 175 | /* gcc and egcs do not distinguish between CPU32 and CPU32+ */ |
|---|
| 176 | #elif defined(RTEMS__mcpu32p__) |
|---|
| 177 | |
|---|
| 178 | #define CPU_MODEL_NAME "mcpu32+" |
|---|
| 179 | #define M68K_HAS_VBR 1 |
|---|
| 180 | #define M68K_HAS_SEPARATE_STACKS 0 |
|---|
| 181 | #define M68K_HAS_BFFFO 0 |
|---|
| 182 | #define M68K_HAS_PREINDEXING 1 |
|---|
| 183 | #define M68K_HAS_EXTB_L 1 |
|---|
| 184 | #define M68K_HAS_MISALIGNED 1 |
|---|
| 185 | #define M68K_HAS_FPU 0 |
|---|
| 186 | #define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 187 | |
|---|
| 188 | #elif defined(__mcpu32__) |
|---|
| 189 | |
|---|
| 190 | #define CPU_MODEL_NAME "mcpu32" |
|---|
| 191 | #define M68K_HAS_VBR 1 |
|---|
| 192 | #define M68K_HAS_SEPARATE_STACKS 0 |
|---|
| 193 | #define M68K_HAS_BFFFO 0 |
|---|
| 194 | #define M68K_HAS_PREINDEXING 1 |
|---|
| 195 | #define M68K_HAS_EXTB_L 1 |
|---|
| 196 | #define M68K_HAS_MISALIGNED 0 |
|---|
| 197 | #define M68K_HAS_FPU 0 |
|---|
| 198 | #define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 199 | |
|---|
| 200 | #elif defined(__mcf528x__) |
|---|
| 201 | /* Motorola ColdFire ISA A+ - RISC/68020 hybrid */ |
|---|
| 202 | #define CPU_MODEL_NAME "m528x" |
|---|
| 203 | #define M68K_HAS_VBR 1 |
|---|
| 204 | #define M68K_HAS_BFFFO 0 |
|---|
| 205 | #define M68K_HAS_SEPARATE_STACKS 0 |
|---|
| 206 | #define M68K_HAS_PREINDEXING 0 |
|---|
| 207 | #define M68K_HAS_EXTB_L 1 |
|---|
| 208 | #define M68K_HAS_MISALIGNED 1 |
|---|
| 209 | #define M68K_HAS_FPU 0 |
|---|
| 210 | #define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 211 | #define M68K_HAS_ISA_APLUS 1 |
|---|
| 212 | |
|---|
| 213 | #elif defined(__mcf5200__) |
|---|
| 214 | /* Motorola ColdFire V2 core - RISC/68020 hybrid */ |
|---|
| 215 | #define CPU_MODEL_NAME "m5200" |
|---|
| 216 | #define M68K_HAS_VBR 1 |
|---|
| 217 | #define M68K_HAS_BFFFO 0 |
|---|
| 218 | #define M68K_HAS_SEPARATE_STACKS 0 |
|---|
| 219 | #define M68K_HAS_PREINDEXING 0 |
|---|
| 220 | #define M68K_HAS_EXTB_L 1 |
|---|
| 221 | #define M68K_HAS_MISALIGNED 1 |
|---|
| 222 | #define M68K_HAS_FPU 0 |
|---|
| 223 | #define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 224 | #define M68K_HAS_ISA_APLUS 0 |
|---|
| 225 | |
|---|
| 226 | #elif defined(__mcf5307__) |
|---|
| 227 | /* UNCHECKED */ |
|---|
| 228 | /* Motorola ColdFire 5307 */ |
|---|
| 229 | #define CPU_MODEL_NAME "m5307" |
|---|
| 230 | #define M68K_HAS_VBR 1 |
|---|
| 231 | #define M68K_HAS_BFFFO 0 |
|---|
| 232 | #define M68K_HAS_SEPARATE_STACKS 0 |
|---|
| 233 | #define M68K_HAS_PREINDEXING 0 |
|---|
| 234 | #define M68K_HAS_EXTB_L 1 |
|---|
| 235 | #define M68K_HAS_MISALIGNED 1 |
|---|
| 236 | #define M68K_HAS_FPU 0 |
|---|
| 237 | #define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 238 | #define M68K_HAS_ISA_APLUS 0 |
|---|
| 239 | |
|---|
| 240 | #elif defined(__mcf5407__) |
|---|
| 241 | #if defined(__mcfv4e__) |
|---|
| 242 | /* UNCHECKED */ |
|---|
| 243 | /* Motorola ColdFire V4e */ |
|---|
| 244 | #define CPU_MODEL_NAME "mcfv4e" |
|---|
| 245 | #define M68K_HAS_VBR 1 |
|---|
| 246 | #define M68K_HAS_BFFFO 0 |
|---|
| 247 | #define M68K_HAS_SEPARATE_STACKS 0 |
|---|
| 248 | #define M68K_HAS_PREINDEXING 0 |
|---|
| 249 | #define M68K_HAS_EXTB_L 1 |
|---|
| 250 | #define M68K_HAS_MISALIGNED 1 |
|---|
| 251 | #define M68K_HAS_FPU 0 |
|---|
| 252 | #define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 253 | #define M68K_HAS_ISA_APLUS 0 |
|---|
| 254 | #else |
|---|
| 255 | /* UNCHECKED */ |
|---|
| 256 | /* Motorola ColdFire 5407 */ |
|---|
| 257 | #define CPU_MODEL_NAME "m5407" |
|---|
| 258 | #define M68K_HAS_VBR 1 |
|---|
| 259 | #define M68K_HAS_BFFFO 0 |
|---|
| 260 | #define M68K_HAS_SEPARATE_STACKS 0 |
|---|
| 261 | #define M68K_HAS_PREINDEXING 0 |
|---|
| 262 | #define M68K_HAS_EXTB_L 1 |
|---|
| 263 | #define M68K_HAS_MISALIGNED 1 |
|---|
| 264 | #define M68K_HAS_FPU 0 |
|---|
| 265 | #define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 266 | #define M68K_HAS_ISA_APLUS 0 |
|---|
| 267 | #endif |
|---|
| 268 | |
|---|
| 269 | #elif defined(__mc68000__) |
|---|
| 270 | |
|---|
| 271 | #define CPU_MODEL_NAME "m68000" |
|---|
| 272 | #define M68K_HAS_VBR 0 |
|---|
| 273 | #define M68K_HAS_SEPARATE_STACKS 0 |
|---|
| 274 | #define M68K_HAS_BFFFO 0 |
|---|
| 275 | #define M68K_HAS_PREINDEXING 0 |
|---|
| 276 | #define M68K_HAS_EXTB_L 0 |
|---|
| 277 | #define M68K_HAS_MISALIGNED 0 |
|---|
| 278 | # if defined (__HAVE_68881__) |
|---|
| 279 | # define M68K_HAS_FPU 1 |
|---|
| 280 | # define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 281 | # else |
|---|
| 282 | # define M68K_HAS_FPU 0 |
|---|
| 283 | # define M68K_HAS_FPSP_PACKAGE 0 |
|---|
| 284 | # endif |
|---|
| 285 | |
|---|
| 286 | #else |
|---|
| 287 | |
|---|
| 288 | #error "Unsupported CPU model -- are you sure you're running a 68k compiler?" |
|---|
| 289 | |
|---|
| 290 | #endif |
|---|
| 291 | |
|---|
| 292 | #ifndef ASM |
|---|
| 293 | #include <rtems/score/types.h> |
|---|
| 294 | #include <rtems/stdint.h> |
|---|
| 295 | #endif |
|---|
| 296 | |
|---|
| 297 | /* |
|---|
| 298 | * OBSOLETE: Backward compatibility only - Don't use. |
|---|
| 299 | * Use __mcoldfire__ instead. |
|---|
| 300 | */ |
|---|
| 301 | #if defined(__mcoldfire__) |
|---|
| 302 | #define M68K_COLDFIRE_ARCH 1 |
|---|
| 303 | #else |
|---|
| 304 | #define M68K_COLDFIRE_ARCH 0 |
|---|
| 305 | #endif |
|---|
| 306 | |
|---|
| 307 | /* |
|---|
| 308 | * Define the name of the CPU family. |
|---|
| 309 | */ |
|---|
| 310 | |
|---|
| 311 | #if ( defined(__mcoldfire__) ) |
|---|
| 312 | #define CPU_NAME "Motorola ColdFire" |
|---|
| 313 | #else |
|---|
| 314 | #define CPU_NAME "Motorola MC68xxx" |
|---|
| 315 | #endif |
|---|
| 316 | |
|---|
| 317 | #ifndef ASM |
|---|
| 318 | |
|---|
| 319 | #if ( defined(__mcoldfire__) ) |
|---|
| 320 | #define m68k_disable_interrupts( _level ) \ |
|---|
| 321 | do { register uint32_t _tmpsr = 0x0700; \ |
|---|
| 322 | asm volatile ( "move.w %%sr,%0\n\t" \ |
|---|
| 323 | "or.l %0,%1\n\t" \ |
|---|
| 324 | "move.w %1,%%sr" \ |
|---|
| 325 | : "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) \ |
|---|
| 326 | : "cc" ); \ |
|---|
| 327 | } while( 0 ) |
|---|
| 328 | #else |
|---|
| 329 | #define m68k_disable_interrupts( _level ) \ |
|---|
| 330 | asm volatile ( "move.w %%sr,%0\n\t" \ |
|---|
| 331 | "or.w #0x0700,%%sr" \ |
|---|
| 332 | : "=d" (_level) \ |
|---|
| 333 | : : "cc" ) |
|---|
| 334 | #endif |
|---|
| 335 | |
|---|
| 336 | #define m68k_enable_interrupts( _level ) \ |
|---|
| 337 | asm volatile ( "move.w %0,%%sr " : : "d" (_level) : "cc"); |
|---|
| 338 | |
|---|
| 339 | #if ( defined(__mcoldfire__) ) |
|---|
| 340 | #define m68k_flash_interrupts( _level ) \ |
|---|
| 341 | do { register uint32_t _tmpsr = 0x0700; \ |
|---|
| 342 | asm volatile ( "move.w %2,%%sr\n\t" \ |
|---|
| 343 | "or.l %2,%1\n\t" \ |
|---|
| 344 | "move.w %1,%%sr" \ |
|---|
| 345 | : "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) \ |
|---|
| 346 | : "cc"); \ |
|---|
| 347 | } while( 0 ) |
|---|
| 348 | #else |
|---|
| 349 | #define m68k_flash_interrupts( _level ) \ |
|---|
| 350 | asm volatile ( "move.w %0,%%sr\n\t" \ |
|---|
| 351 | "or.w #0x0700,%%sr" \ |
|---|
| 352 | : : "d" (_level) \ |
|---|
| 353 | : "cc" ) |
|---|
| 354 | #endif |
|---|
| 355 | |
|---|
| 356 | #define m68k_get_interrupt_level( _level ) \ |
|---|
| 357 | do { \ |
|---|
| 358 | register uint32_t _tmpsr; \ |
|---|
| 359 | \ |
|---|
| 360 | asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ |
|---|
| 361 | _level = (_tmpsr & 0x0700) >> 8; \ |
|---|
| 362 | } while (0) |
|---|
| 363 | |
|---|
| 364 | #define m68k_set_interrupt_level( _newlevel ) \ |
|---|
| 365 | do { \ |
|---|
| 366 | register uint32_t _tmpsr; \ |
|---|
| 367 | \ |
|---|
| 368 | asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ |
|---|
| 369 | _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \ |
|---|
| 370 | asm volatile( "move.w %0,%%sr" : : "d" (_tmpsr)); \ |
|---|
| 371 | } while (0) |
|---|
| 372 | |
|---|
| 373 | #if ( M68K_HAS_VBR == 1 && !defined(__mcoldfire__) ) |
|---|
| 374 | #define m68k_get_vbr( vbr ) \ |
|---|
| 375 | asm volatile ( "movec %%vbr,%0 " : "=r" (vbr)) |
|---|
| 376 | |
|---|
| 377 | #define m68k_set_vbr( vbr ) \ |
|---|
| 378 | asm volatile ( "movec %0,%%vbr " : : "r" (vbr)) |
|---|
| 379 | |
|---|
| 380 | #elif ( defined(__mcoldfire__) ) |
|---|
| 381 | extern void* _VBR; |
|---|
| 382 | #define m68k_get_vbr( _vbr ) _vbr = &_VBR |
|---|
| 383 | |
|---|
| 384 | #define m68k_set_vbr( _vbr ) \ |
|---|
| 385 | do { \ |
|---|
| 386 | asm volatile ( "movec %0,%%vbr " : : "r" (_vbr)); \ |
|---|
| 387 | _VBR = (void *)_vbr; \ |
|---|
| 388 | } while(0) |
|---|
| 389 | |
|---|
| 390 | #else |
|---|
| 391 | #define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR |
|---|
| 392 | #define m68k_set_vbr( _vbr ) |
|---|
| 393 | #endif |
|---|
| 394 | |
|---|
| 395 | /* |
|---|
| 396 | * The following routine swaps the endian format of an unsigned int. |
|---|
| 397 | * It must be static because it is referenced indirectly. |
|---|
| 398 | */ |
|---|
| 399 | #if ( defined(__mcoldfire__) ) |
|---|
| 400 | |
|---|
| 401 | /* There are no rotate commands in Coldfire architecture. We will use |
|---|
| 402 | * generic implementation of endian swapping for Coldfire. |
|---|
| 403 | */ |
|---|
| 404 | static inline uint32_t m68k_swap_u32( |
|---|
| 405 | uint32_t value |
|---|
| 406 | ) |
|---|
| 407 | { |
|---|
| 408 | uint32_t byte1, byte2, byte3, byte4, swapped; |
|---|
| 409 | |
|---|
| 410 | byte4 = (value >> 24) & 0xff; |
|---|
| 411 | byte3 = (value >> 16) & 0xff; |
|---|
| 412 | byte2 = (value >> 8) & 0xff; |
|---|
| 413 | byte1 = value & 0xff; |
|---|
| 414 | |
|---|
| 415 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
|---|
| 416 | return( swapped ); |
|---|
| 417 | } |
|---|
| 418 | |
|---|
| 419 | static inline uint16_t m68k_swap_u16( |
|---|
| 420 | uint16_t value |
|---|
| 421 | ) |
|---|
| 422 | { |
|---|
| 423 | return (((value & 0xff) << 8) | ((value >> 8) & 0xff)); |
|---|
| 424 | } |
|---|
| 425 | |
|---|
| 426 | #else |
|---|
| 427 | |
|---|
| 428 | static inline uint32_t m68k_swap_u32( |
|---|
| 429 | uint32_t value |
|---|
| 430 | ) |
|---|
| 431 | { |
|---|
| 432 | uint32_t swapped = value; |
|---|
| 433 | |
|---|
| 434 | asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); |
|---|
| 435 | asm volatile( "swap %0" : "=d" (swapped) : "0" (swapped) ); |
|---|
| 436 | asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); |
|---|
| 437 | |
|---|
| 438 | return( swapped ); |
|---|
| 439 | } |
|---|
| 440 | |
|---|
| 441 | static inline uint16_t m68k_swap_u16( |
|---|
| 442 | uint16_t value |
|---|
| 443 | ) |
|---|
| 444 | { |
|---|
| 445 | uint16_t swapped = value; |
|---|
| 446 | |
|---|
| 447 | asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); |
|---|
| 448 | |
|---|
| 449 | return( swapped ); |
|---|
| 450 | } |
|---|
| 451 | #endif |
|---|
| 452 | |
|---|
| 453 | #define CPU_swap_u32( value ) m68k_swap_u32( value ) |
|---|
| 454 | #define CPU_swap_u16( value ) m68k_swap_u16( value ) |
|---|
| 455 | |
|---|
| 456 | |
|---|
| 457 | /* |
|---|
| 458 | * _CPU_virtual_to_physical |
|---|
| 459 | * |
|---|
| 460 | * DESCRIPTION: |
|---|
| 461 | * |
|---|
| 462 | * This function is used to map virtual addresses to physical |
|---|
| 463 | * addresses. |
|---|
| 464 | * |
|---|
| 465 | * FIXME: ASSUMES THAT VIRTUAL ADDRESSES ARE THE SAME AS THE |
|---|
| 466 | * PHYSICAL ADDRESSES |
|---|
| 467 | */ |
|---|
| 468 | static inline void * _CPU_virtual_to_physical ( |
|---|
| 469 | const void * d_addr ) |
|---|
| 470 | { |
|---|
| 471 | return (void *) d_addr; |
|---|
| 472 | } |
|---|
| 473 | |
|---|
| 474 | |
|---|
| 475 | #endif /* !ASM */ |
|---|
| 476 | |
|---|
| 477 | #ifdef __cplusplus |
|---|
| 478 | } |
|---|
| 479 | #endif |
|---|
| 480 | |
|---|
| 481 | #endif /* _RTEMS_SCORE_M68K_H */ |
|---|
![[RTEMS Logo]](/images/logo.png){kind=logo}
