[a911a77] | 1 | /** |
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| 2 | * @file rtems/score/m68k.h |
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| 3 | */ |
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| 4 | |
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| 5 | /* |
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[7908ba5b] | 6 | * This include file contains information pertaining to the Motorola |
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| 7 | * m68xxx processor family. |
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| 8 | * |
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[08311cc3] | 9 | * COPYRIGHT (c) 1989-1999. |
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[7908ba5b] | 10 | * On-Line Applications Research Corporation (OAR). |
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| 11 | * |
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| 12 | * The license and distribution terms for this file may be |
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| 13 | * found in the file LICENSE in this distribution or at |
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[05a98b7] | 14 | * http://www.rtems.com/license/LICENSE. |
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[7908ba5b] | 15 | * |
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| 16 | * $Id$ |
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| 17 | */ |
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| 18 | |
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[7f70d1b7] | 19 | #ifndef _RTEMS_SCORE_M68K_H |
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| 20 | #define _RTEMS_SCORE_M68K_H |
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[7908ba5b] | 21 | |
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| 22 | #ifdef __cplusplus |
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| 23 | extern "C" { |
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| 24 | #endif |
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| 25 | |
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| 26 | /* |
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| 27 | * This section contains the information required to build |
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| 28 | * RTEMS for a particular member of the Motorola MC68xxx |
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| 29 | * family. It does this by setting variables to indicate |
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| 30 | * which implementation dependent features are present in |
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| 31 | * a particular member of the family. |
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| 32 | * |
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| 33 | * Currently recognized: |
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| 34 | * -m68000 |
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| 35 | * -m68000 -msoft-float |
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| 36 | * -m68020 |
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| 37 | * -m68020 -msoft-float |
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| 38 | * -m68030 |
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| 39 | * -m68040 -msoft-float |
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| 40 | * -m68040 |
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| 41 | * -m68040 -msoft-float |
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| 42 | * -m68060 |
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| 43 | * -m68060 -msoft-float |
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| 44 | * -m68302 (no FP) (deprecated, use -m68000) |
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| 45 | * -m68332 (no FP) (deprecated, use -mcpu32) |
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| 46 | * -mcpu32 (no FP) |
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| 47 | * -m5200 (no FP) |
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[fa9fa1e4] | 48 | * -m528x (no FP, ISA A+) |
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[7908ba5b] | 49 | * |
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| 50 | * As of gcc 2.8.1 and egcs 1.1, there is no distinction made between |
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| 51 | * the CPU32 and CPU32+. The option -mcpu32 generates code which can |
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| 52 | * be run on either core. RTEMS distinguishes between these two cores |
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| 53 | * because they have different alignment rules which impact performance. |
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| 54 | * If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should |
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| 55 | * be defined in your custom file (see make/custom/gen68360.cfg for an |
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| 56 | * example of how to do this. If gcc ever distinguishes between these |
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| 57 | * two cores, then RTEMS__mcpu32p__ usage will be replaced with the |
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| 58 | * appropriate compiler defined predefine. |
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| 59 | * |
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| 60 | * Here is some information on the 040 variants (courtesy of Doug McBride, |
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| 61 | * mcbride@rodin.colorado.edu): |
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| 62 | * |
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| 63 | * "The 68040 is a superset of the 68EC040 and the 68LC040. The |
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| 64 | * 68EC040 and 68LC040 do not have FPU's. The 68LC040 and the |
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| 65 | * 68EC040 have renamed the DLE pin as JS0 which must be tied to |
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| 66 | * Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1. The |
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| 67 | * 68EC040 has access control units instead of memory management units. |
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| 68 | * The 68EC040 should not have the PFLUSH or PTEST instructions executed |
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| 69 | * (cause an indeterminate result). The 68EC040 and 68LC040 do not |
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| 70 | * implement the DLE or multiplexed bus modes. The 68EC040 does not |
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| 71 | * implement the output buffer impedance selection mode of operation." |
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| 72 | * |
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| 73 | * M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction |
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| 74 | * which is not available for 68000 or 68ec000 cores (68000, 68001, 68008, |
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| 75 | * 68010, 68302, 68306, 68307). This instruction is available on the 68020 |
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| 76 | * up and the cpu32 based models. |
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| 77 | * |
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| 78 | * M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned |
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| 79 | * data access (68020, 68030, 68040, 68060, CPU32+). |
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| 80 | * |
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| 81 | * NOTE: |
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| 82 | * Eventually it would be nice to evaluate doing a lot of this section |
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| 83 | * by having each model specify which core it uses and then go from there. |
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| 84 | */ |
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| 85 | |
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[df49c60] | 86 | /* |
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| 87 | * Figure out all CPU Model Feature Flags based upon compiler |
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| 88 | * predefines. Notice the only exception to this is that |
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| 89 | * gcc does not distinguish between CPU32 and CPU32+. This |
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| 90 | * feature selection logic is setup such that if RTEMS__mcpu32p__ |
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| 91 | * is defined, then CPU32+ rules are used. Otherwise, the safe |
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| 92 | * but less efficient CPU32 rules are used for the CPU32+. |
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| 93 | */ |
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| 94 | |
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[ff60424] | 95 | #if (defined(__mc68020__) && !defined(__mcpu32__)) |
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[7908ba5b] | 96 | |
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| 97 | #define CPU_MODEL_NAME "m68020" |
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| 98 | #define M68K_HAS_VBR 1 |
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| 99 | #define M68K_HAS_SEPARATE_STACKS 1 |
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| 100 | #define M68K_HAS_BFFFO 1 |
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| 101 | #define M68K_HAS_PREINDEXING 1 |
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| 102 | #define M68K_HAS_EXTB_L 1 |
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| 103 | #define M68K_HAS_MISALIGNED 1 |
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| 104 | # if defined (__HAVE_68881__) |
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| 105 | # define M68K_HAS_FPU 1 |
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| 106 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 107 | # else |
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| 108 | # define M68K_HAS_FPU 0 |
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| 109 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 110 | # endif |
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| 111 | |
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| 112 | #elif defined(__mc68030__) |
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| 113 | |
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| 114 | #define CPU_MODEL_NAME "m68030" |
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| 115 | #define M68K_HAS_VBR 1 |
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| 116 | #define M68K_HAS_SEPARATE_STACKS 1 |
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| 117 | #define M68K_HAS_BFFFO 1 |
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| 118 | #define M68K_HAS_PREINDEXING 1 |
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| 119 | #define M68K_HAS_EXTB_L 1 |
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| 120 | #define M68K_HAS_MISALIGNED 1 |
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| 121 | # if defined (__HAVE_68881__) |
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| 122 | # define M68K_HAS_FPU 1 |
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| 123 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 124 | # else |
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| 125 | # define M68K_HAS_FPU 0 |
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| 126 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 127 | # endif |
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| 128 | |
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| 129 | #elif defined(__mc68040__) |
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| 130 | |
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| 131 | #define CPU_MODEL_NAME "m68040" |
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| 132 | #define M68K_HAS_VBR 1 |
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| 133 | #define M68K_HAS_SEPARATE_STACKS 1 |
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| 134 | #define M68K_HAS_BFFFO 1 |
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| 135 | #define M68K_HAS_PREINDEXING 1 |
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| 136 | #define M68K_HAS_EXTB_L 1 |
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| 137 | #define M68K_HAS_MISALIGNED 1 |
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| 138 | # if defined (__HAVE_68881__) |
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| 139 | # define M68K_HAS_FPU 1 |
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| 140 | # define M68K_HAS_FPSP_PACKAGE 1 |
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| 141 | # else |
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| 142 | # define M68K_HAS_FPU 0 |
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| 143 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 144 | # endif |
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| 145 | |
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| 146 | #elif defined(__mc68060__) |
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| 147 | |
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| 148 | #define CPU_MODEL_NAME "m68060" |
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| 149 | #define M68K_HAS_VBR 1 |
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| 150 | #define M68K_HAS_SEPARATE_STACKS 0 |
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| 151 | #define M68K_HAS_BFFFO 1 |
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| 152 | #define M68K_HAS_PREINDEXING 1 |
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| 153 | #define M68K_HAS_EXTB_L 1 |
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| 154 | #define M68K_HAS_MISALIGNED 1 |
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| 155 | # if defined (__HAVE_68881__) |
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| 156 | # define M68K_HAS_FPU 1 |
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[2c7e8e51] | 157 | # define M68K_HAS_FPSP_PACKAGE 0 |
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[7908ba5b] | 158 | # else |
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| 159 | # define M68K_HAS_FPU 0 |
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| 160 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 161 | # endif |
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| 162 | |
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| 163 | #elif defined(__mc68302__) |
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[8ef3818] | 164 | |
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[7908ba5b] | 165 | #define CPU_MODEL_NAME "m68302" |
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| 166 | #define M68K_HAS_VBR 0 |
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| 167 | #define M68K_HAS_SEPARATE_STACKS 0 |
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| 168 | #define M68K_HAS_BFFFO 0 |
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| 169 | #define M68K_HAS_PREINDEXING 0 |
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| 170 | #define M68K_HAS_EXTB_L 0 |
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| 171 | #define M68K_HAS_MISALIGNED 0 |
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| 172 | #define M68K_HAS_FPU 0 |
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| 173 | #define M68K_HAS_FPSP_PACKAGE 0 |
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| 174 | |
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| 175 | /* gcc and egcs do not distinguish between CPU32 and CPU32+ */ |
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| 176 | #elif defined(RTEMS__mcpu32p__) |
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| 177 | |
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| 178 | #define CPU_MODEL_NAME "mcpu32+" |
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| 179 | #define M68K_HAS_VBR 1 |
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| 180 | #define M68K_HAS_SEPARATE_STACKS 0 |
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| 181 | #define M68K_HAS_BFFFO 0 |
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| 182 | #define M68K_HAS_PREINDEXING 1 |
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| 183 | #define M68K_HAS_EXTB_L 1 |
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| 184 | #define M68K_HAS_MISALIGNED 1 |
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| 185 | #define M68K_HAS_FPU 0 |
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| 186 | #define M68K_HAS_FPSP_PACKAGE 0 |
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| 187 | |
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| 188 | #elif defined(__mcpu32__) |
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| 189 | |
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| 190 | #define CPU_MODEL_NAME "mcpu32" |
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| 191 | #define M68K_HAS_VBR 1 |
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| 192 | #define M68K_HAS_SEPARATE_STACKS 0 |
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| 193 | #define M68K_HAS_BFFFO 0 |
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| 194 | #define M68K_HAS_PREINDEXING 1 |
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| 195 | #define M68K_HAS_EXTB_L 1 |
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| 196 | #define M68K_HAS_MISALIGNED 0 |
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| 197 | #define M68K_HAS_FPU 0 |
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| 198 | #define M68K_HAS_FPSP_PACKAGE 0 |
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| 199 | |
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[fa9fa1e4] | 200 | #elif defined(__mcf528x__) |
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| 201 | /* Motorola ColdFire ISA A+ - RISC/68020 hybrid */ |
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| 202 | #define CPU_MODEL_NAME "m528x" |
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| 203 | #define M68K_HAS_VBR 1 |
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| 204 | #define M68K_HAS_BFFFO 0 |
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| 205 | #define M68K_HAS_SEPARATE_STACKS 0 |
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| 206 | #define M68K_HAS_PREINDEXING 0 |
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| 207 | #define M68K_HAS_EXTB_L 1 |
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| 208 | #define M68K_HAS_MISALIGNED 1 |
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| 209 | #define M68K_HAS_FPU 0 |
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| 210 | #define M68K_HAS_FPSP_PACKAGE 0 |
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| 211 | #define M68K_COLDFIRE_ARCH 1 |
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| 212 | #define M68K_HAS_ISA_APLUS 1 |
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| 213 | |
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[7908ba5b] | 214 | #elif defined(__mcf5200__) |
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| 215 | /* Motorola ColdFire V2 core - RISC/68020 hybrid */ |
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| 216 | #define CPU_MODEL_NAME "m5200" |
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| 217 | #define M68K_HAS_VBR 1 |
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| 218 | #define M68K_HAS_BFFFO 0 |
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| 219 | #define M68K_HAS_SEPARATE_STACKS 0 |
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| 220 | #define M68K_HAS_PREINDEXING 0 |
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| 221 | #define M68K_HAS_EXTB_L 1 |
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| 222 | #define M68K_HAS_MISALIGNED 1 |
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| 223 | #define M68K_HAS_FPU 0 |
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| 224 | #define M68K_HAS_FPSP_PACKAGE 0 |
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| 225 | #define M68K_COLDFIRE_ARCH 1 |
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[fa9fa1e4] | 226 | #define M68K_HAS_ISA_APLUS 0 |
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[7908ba5b] | 227 | |
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| 228 | #elif defined(__mc68000__) |
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| 229 | |
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| 230 | #define CPU_MODEL_NAME "m68000" |
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| 231 | #define M68K_HAS_VBR 0 |
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| 232 | #define M68K_HAS_SEPARATE_STACKS 0 |
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| 233 | #define M68K_HAS_BFFFO 0 |
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| 234 | #define M68K_HAS_PREINDEXING 0 |
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| 235 | #define M68K_HAS_EXTB_L 0 |
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| 236 | #define M68K_HAS_MISALIGNED 0 |
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| 237 | # if defined (__HAVE_68881__) |
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| 238 | # define M68K_HAS_FPU 1 |
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| 239 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 240 | # else |
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| 241 | # define M68K_HAS_FPU 0 |
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| 242 | # define M68K_HAS_FPSP_PACKAGE 0 |
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| 243 | # endif |
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| 244 | |
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| 245 | #else |
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| 246 | |
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| 247 | #error "Unsupported CPU model -- are you sure you're running a 68k compiler?" |
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| 248 | |
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| 249 | #endif |
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| 250 | |
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[9f9871f] | 251 | #ifndef ASM |
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[ce3c6f3e] | 252 | #include <rtems/score/types.h> |
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[0cc9d277] | 253 | #include <stdint.h> |
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[9f9871f] | 254 | #endif |
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| 255 | |
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[7908ba5b] | 256 | /* |
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| 257 | * If the above did not specify a ColdFire architecture, then set |
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| 258 | * this flag to indicate that it is not a ColdFire CPU. |
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| 259 | */ |
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| 260 | |
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| 261 | #if !defined(M68K_COLDFIRE_ARCH) |
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| 262 | #define M68K_COLDFIRE_ARCH 0 |
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| 263 | #endif |
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| 264 | |
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| 265 | /* |
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| 266 | * Define the name of the CPU family. |
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| 267 | */ |
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| 268 | |
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| 269 | #if ( M68K_COLDFIRE_ARCH == 1 ) |
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| 270 | #define CPU_NAME "Motorola ColdFire" |
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| 271 | #else |
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| 272 | #define CPU_NAME "Motorola MC68xxx" |
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| 273 | #endif |
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| 274 | |
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| 275 | #ifndef ASM |
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| 276 | |
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| 277 | #if ( M68K_COLDFIRE_ARCH == 1 ) |
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| 278 | #define m68k_disable_interrupts( _level ) \ |
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[d86bae8] | 279 | do { register uint32_t _tmpsr = 0x0700; \ |
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[7908ba5b] | 280 | asm volatile ( "move.w %%sr,%0\n\t" \ |
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| 281 | "or.l %0,%1\n\t" \ |
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| 282 | "move.w %1,%%sr" \ |
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| 283 | : "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) ); \ |
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| 284 | } while( 0 ) |
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| 285 | #else |
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| 286 | #define m68k_disable_interrupts( _level ) \ |
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| 287 | asm volatile ( "move.w %%sr,%0\n\t" \ |
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| 288 | "or.w #0x0700,%%sr" \ |
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| 289 | : "=d" (_level)) |
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| 290 | #endif |
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| 291 | |
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| 292 | #define m68k_enable_interrupts( _level ) \ |
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| 293 | asm volatile ( "move.w %0,%%sr " : : "d" (_level)); |
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| 294 | |
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| 295 | #if ( M68K_COLDFIRE_ARCH == 1 ) |
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| 296 | #define m68k_flash_interrupts( _level ) \ |
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[d86bae8] | 297 | do { register uint32_t _tmpsr = 0x0700; \ |
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[7908ba5b] | 298 | asm volatile ( "move.w %2,%%sr\n\t" \ |
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| 299 | "or.l %2,%1\n\t" \ |
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| 300 | "move.w %1,%%sr" \ |
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| 301 | : "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) ); \ |
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| 302 | } while( 0 ) |
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| 303 | #else |
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| 304 | #define m68k_flash_interrupts( _level ) \ |
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| 305 | asm volatile ( "move.w %0,%%sr\n\t" \ |
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| 306 | "or.w #0x0700,%%sr" \ |
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| 307 | : : "d" (_level)) |
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| 308 | #endif |
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| 309 | |
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| 310 | #define m68k_get_interrupt_level( _level ) \ |
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| 311 | do { \ |
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[d86bae8] | 312 | register uint32_t _tmpsr; \ |
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[7908ba5b] | 313 | \ |
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| 314 | asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ |
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| 315 | _level = (_tmpsr & 0x0700) >> 8; \ |
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| 316 | } while (0) |
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| 317 | |
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| 318 | #define m68k_set_interrupt_level( _newlevel ) \ |
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| 319 | do { \ |
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[d86bae8] | 320 | register uint32_t _tmpsr; \ |
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[7908ba5b] | 321 | \ |
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| 322 | asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ |
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| 323 | _tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \ |
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| 324 | asm volatile( "move.w %0,%%sr" : : "d" (_tmpsr)); \ |
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| 325 | } while (0) |
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| 326 | |
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| 327 | #if ( M68K_HAS_VBR == 1 && M68K_COLDFIRE_ARCH == 0 ) |
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| 328 | #define m68k_get_vbr( vbr ) \ |
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| 329 | asm volatile ( "movec %%vbr,%0 " : "=r" (vbr)) |
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| 330 | |
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| 331 | #define m68k_set_vbr( vbr ) \ |
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| 332 | asm volatile ( "movec %0,%%vbr " : : "r" (vbr)) |
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| 333 | |
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| 334 | #elif ( M68K_COLDFIRE_ARCH == 1 ) |
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[ac64416] | 335 | extern void *_VBR; |
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| 336 | #define m68k_get_vbr( _vbr ) _vbr = _VBR |
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[7908ba5b] | 337 | |
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[fa9fa1e4] | 338 | #define m68k_set_vbr( vbr ) \ |
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| 339 | do { \ |
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| 340 | asm volatile ( "movec %0,%%vbr " : : "r" (vbr)); \ |
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[7111268] | 341 | _VBR = (void *)vbr; \ |
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[fa9fa1e4] | 342 | } while(0) |
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[7908ba5b] | 343 | |
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| 344 | #else |
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| 345 | #define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR |
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| 346 | #define m68k_set_vbr( _vbr ) |
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| 347 | #endif |
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| 348 | |
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| 349 | /* |
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| 350 | * The following routine swaps the endian format of an unsigned int. |
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| 351 | * It must be static because it is referenced indirectly. |
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| 352 | */ |
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[9f9871f] | 353 | #if ( M68K_COLDFIRE_ARCH == 1 ) |
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| 354 | |
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| 355 | /* There are no rotate commands in Coldfire architecture. We will use |
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| 356 | * generic implementation of endian swapping for Coldfire. |
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| 357 | */ |
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[a04f371] | 358 | static inline uint32_t m68k_swap_u32( |
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| 359 | uint32_t value |
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[9f9871f] | 360 | ) |
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| 361 | { |
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[d86bae8] | 362 | uint32_t byte1, byte2, byte3, byte4, swapped; |
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[9f9871f] | 363 | |
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| 364 | byte4 = (value >> 24) & 0xff; |
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| 365 | byte3 = (value >> 16) & 0xff; |
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| 366 | byte2 = (value >> 8) & 0xff; |
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| 367 | byte1 = value & 0xff; |
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| 368 | |
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| 369 | swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; |
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| 370 | return( swapped ); |
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| 371 | } |
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| 372 | |
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[6d48403] | 373 | static inline uint16_t m68k_swap_u16( |
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| 374 | uint16_t value |
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[9f9871f] | 375 | ) |
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| 376 | { |
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| 377 | return (((value & 0xff) << 8) | ((value >> 8) & 0xff)); |
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| 378 | } |
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| 379 | |
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| 380 | #else |
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[7908ba5b] | 381 | |
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[a04f371] | 382 | static inline uint32_t m68k_swap_u32( |
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| 383 | uint32_t value |
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[7908ba5b] | 384 | ) |
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| 385 | { |
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[a04f371] | 386 | uint32_t swapped = value; |
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[7908ba5b] | 387 | |
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| 388 | asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); |
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| 389 | asm volatile( "swap %0" : "=d" (swapped) : "0" (swapped) ); |
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| 390 | asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); |
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| 391 | |
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| 392 | return( swapped ); |
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| 393 | } |
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| 394 | |
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[6d48403] | 395 | static inline uint16_t m68k_swap_u16( |
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| 396 | uint16_t value |
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[7908ba5b] | 397 | ) |
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| 398 | { |
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[6d48403] | 399 | uint16_t swapped = value; |
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[7908ba5b] | 400 | |
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| 401 | asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) ); |
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| 402 | |
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| 403 | return( swapped ); |
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| 404 | } |
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[9f9871f] | 405 | #endif |
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[7908ba5b] | 406 | |
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[8ef3818] | 407 | #define CPU_swap_u32( value ) m68k_swap_u32( value ) |
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| 408 | #define CPU_swap_u16( value ) m68k_swap_u16( value ) |
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| 409 | |
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| 410 | |
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| 411 | /* |
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| 412 | * _CPU_virtual_to_physical |
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| 413 | * |
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| 414 | * DESCRIPTION: |
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| 415 | * |
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| 416 | * This function is used to map virtual addresses to physical |
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| 417 | * addresses. |
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| 418 | * |
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| 419 | * FIXME: ASSUMES THAT VIRTUAL ADDRESSES ARE THE SAME AS THE |
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| 420 | * PHYSICAL ADDRESSES |
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| 421 | */ |
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| 422 | static inline void * _CPU_virtual_to_physical ( |
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| 423 | const void * d_addr ) |
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| 424 | { |
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| 425 | return (void *) d_addr; |
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| 426 | } |
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| 427 | |
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| 428 | |
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[7908ba5b] | 429 | #endif /* !ASM */ |
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| 430 | |
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| 431 | #ifdef __cplusplus |
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| 432 | } |
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| 433 | #endif |
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| 434 | |
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[fa6b0f5] | 435 | #endif /* _RTEMS_SCORE_M68K_H */ |
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