source: rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h @ f82752a4

4.115
Last change on this file since f82752a4 was f82752a4, checked in by Daniel Hellstrom <daniel@…>, on Jun 4, 2014 at 9:23:34 AM

Let CPU/BSP Fatal handler have access to source

Without the source the error code does not say that much.
Let it be up to the CPU/BSP to determine the error code
reported on fatal shutdown.

This patch does not change the current behaviour, just
adds the option to handle the source of the fatal halt.

  • Property mode set to 100644
File size: 20.1 KB
Line 
1/**
2 * @file
3 *
4 * @brief Motorola M68K CPU Dependent Source
5 *
6 * This include file contains information pertaining to the Motorola
7 * m68xxx processor family.
8 */
9
10/*
11 *  COPYRIGHT (c) 1989-2011.
12 *  On-Line Applications Research Corporation (OAR).
13 *
14 *  The license and distribution terms for this file may be
15 *  found in the file LICENSE in this distribution or at
16 *  http://www.rtems.org/license/LICENSE.
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/types.h>
27#include <rtems/score/m68k.h>
28
29/* conditional compilation parameters */
30
31#define CPU_INLINE_ENABLE_DISPATCH       TRUE
32#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
33
34/*
35 *  Does the CPU follow the simple vectored interrupt model?
36 *
37 *  If TRUE, then RTEMS allocates the vector table it internally manages.
38 *  If FALSE, then the BSP is assumed to allocate and manage the vector
39 *  table
40 *
41 *  M68K Specific Information:
42 *
43 *  XXX document implementation including references if appropriate
44 */
45#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
46
47/*
48 *  Use the m68k's hardware interrupt stack support and have the
49 *  interrupt manager allocate the memory for it.
50 */
51
52#if ( M68K_HAS_SEPARATE_STACKS == 1)
53#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
54#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
55#else
56#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
57#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
58#endif
59#define CPU_ALLOCATE_INTERRUPT_STACK     1
60
61/*
62 *  Does the RTEMS invoke the user's ISR with the vector number and
63 *  a pointer to the saved interrupt frame (1) or just the vector
64 *  number (0)?
65 */
66
67#define CPU_ISR_PASSES_FRAME_POINTER 0
68
69/*
70 *  Some family members have no FP, some have an FPU such as the
71 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
72 *
73 *  NOTE:  If on a CPU without hardware FP, then one can use software
74 *         emulation.  The gcc software FP emulation code has data which
75 *         must be contexted switched on a per task basis.
76 */
77
78#if ( M68K_HAS_FPU == 1 ) || ( M68K_HAS_EMAC == 1 )
79  #define CPU_HARDWARE_FP TRUE
80  #define CPU_SOFTWARE_FP FALSE
81#else
82  #define CPU_HARDWARE_FP FALSE
83  #if defined( __GNUC__ )
84    #define CPU_SOFTWARE_FP TRUE
85  #else
86    #define CPU_SOFTWARE_FP FALSE
87  #endif
88#endif
89
90/*
91 *  All tasks are not by default floating point tasks on this CPU.
92 *  The IDLE task does not have a floating point context on this CPU.
93 *  It is safe to use the deferred floating point context switch
94 *  algorithm on this CPU.
95 */
96
97#define CPU_ALL_TASKS_ARE_FP             FALSE
98#define CPU_IDLE_TASK_IS_FP              FALSE
99#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
100
101#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
102#define CPU_STACK_GROWS_UP               FALSE
103#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (4)))
104
105#define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
106
107/*
108 *  Define what is required to specify how the network to host conversion
109 *  routines are handled.
110 */
111
112#define CPU_BIG_ENDIAN                           TRUE
113#define CPU_LITTLE_ENDIAN                        FALSE
114
115#define CPU_PER_CPU_CONTROL_SIZE 0
116
117#if ( CPU_HARDWARE_FP == TRUE ) && !defined( __mcoldfire__ )
118  #if defined( __mc68060__ )
119    #define M68K_FP_STATE_SIZE 16
120  #else
121    #define M68K_FP_STATE_SIZE 216
122  #endif
123#endif
124
125#ifndef ASM
126
127/* structures */
128
129typedef struct {
130  /* There is no CPU specific per-CPU state */
131} CPU_Per_CPU_control;
132
133/*
134 *  Basic integer context for the m68k family.
135 */
136
137typedef struct {
138  uint32_t    sr;                /* (sr) status register */
139  uint32_t    d2;                /* (d2) data register 2 */
140  uint32_t    d3;                /* (d3) data register 3 */
141  uint32_t    d4;                /* (d4) data register 4 */
142  uint32_t    d5;                /* (d5) data register 5 */
143  uint32_t    d6;                /* (d6) data register 6 */
144  uint32_t    d7;                /* (d7) data register 7 */
145  void       *a2;                /* (a2) address register 2 */
146  void       *a3;                /* (a3) address register 3 */
147  void       *a4;                /* (a4) address register 4 */
148  void       *a5;                /* (a5) address register 5 */
149  void       *a6;                /* (a6) address register 6 */
150  void       *a7_msp;            /* (a7) master stack pointer */
151  #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
152    uint8_t   fpu_dis;
153  #endif
154} Context_Control;
155
156#define _CPU_Context_Get_SP( _context ) \
157  (_context)->a7_msp
158
159/*
160 *  Floating point context areas and support routines
161 */
162
163#if ( CPU_SOFTWARE_FP == TRUE )
164  /*
165   *  This is the same as gcc's view of the software FP condition code
166   *  register _fpCCR.  The implementation of the emulation code is
167   *  in the gcc-VERSION/config/m68k directory.  This structure is
168   *  correct as of gcc 2.7.2.2.
169   */
170  typedef struct {
171    uint16_t _exception_bits;
172    uint16_t _trap_enable_bits;
173    uint16_t _sticky_bits;
174    uint16_t _rounding_mode;
175    uint16_t _format;
176    uint16_t _last_operation;
177    union {
178      float sf;
179      double df;
180    } _operand1;
181    union {
182      float sf;
183      double df;
184    } _operand2;
185  } Context_Control_fp;
186
187  /*
188   *  This software FP implementation is only for GCC.
189   */
190  #define _CPU_Context_Fp_start( _base, _offset ) \
191     ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
192
193  #define _CPU_Context_Initialize_fp( _fp_area ) \
194     { \
195       Context_Control_fp *_fp; \
196       _fp = *(Context_Control_fp **)_fp_area; \
197       _fp->_exception_bits = 0; \
198       _fp->_trap_enable_bits = 0; \
199       _fp->_sticky_bits = 0; \
200       _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
201       _fp->_format = 0;         /* NIL */ \
202       _fp->_last_operation = 0; /* NOOP */ \
203       _fp->_operand1.df = 0; \
204       _fp->_operand2.df = 0; \
205     }
206#endif
207
208#if ( CPU_HARDWARE_FP == TRUE )
209  #if defined( __mcoldfire__ )
210    /* We need memset() to initialize the FP context */
211    #include <string.h>
212
213    #if ( M68K_HAS_FPU == 1 )
214      /*
215       * The Cache Control Register (CACR) has write-only access.  It is also
216       * used to enable and disable the FPU.  We need to maintain a copy of
217       * this register to allow per thread values.
218       */
219      extern uint32_t _CPU_cacr_shadow;
220    #endif
221
222    /* We assume that each ColdFire core with a FPU has also an EMAC unit */
223    typedef struct {
224      uint32_t emac_macsr;
225      uint32_t emac_acc0;
226      uint32_t emac_acc1;
227      uint32_t emac_acc2;
228      uint32_t emac_acc3;
229      uint32_t emac_accext01;
230      uint32_t emac_accext23;
231      uint32_t emac_mask;
232      #if ( M68K_HAS_FPU == 1 )
233        uint16_t fp_state_format;
234        uint16_t fp_state_fpcr;
235        double fp_state_op;
236        uint32_t fp_state_fpsr;
237
238        /*
239         * We need to save the FP Instruction Address Register (FPIAR), because
240         * a context switch can occur within a FP exception before the handler
241         * was able to save this register.
242         */
243        uint32_t fp_fpiar;
244
245        double fp_data [8];
246      #endif
247    } Context_Control_fp;
248
249    #define _CPU_Context_Fp_start( _base, _offset ) \
250      ((void *) _Addresses_Add_offset( (_base), (_offset) ))
251
252    /*
253     * The reset value for all context relevant registers except the FP data
254     * registers is zero.  The reset value of the FP data register is NAN.  The
255     * restore of the reset FP state will reset the FP data registers, so the
256     * initial value of them can be arbitrary here.
257     */
258    #define _CPU_Context_Initialize_fp( _fp_area ) \
259      memset( *(_fp_area), 0, sizeof( Context_Control_fp ) )
260  #else
261    /*
262     *  FP context save area for the M68881/M68882 and 68060 numeric
263     *  coprocessors.
264     */
265    typedef struct {
266      /*
267       * M68K_FP_STATE_SIZE bytes for FSAVE/FRESTORE
268       * 96 bytes for FMOVEM FP0-7
269       * 12 bytes for FMOVEM CREGS
270       * 4 bytes for non-null flag
271       */
272      uint8_t fp_save_area [M68K_FP_STATE_SIZE + 112];
273    } Context_Control_fp;
274
275    #define _CPU_Context_Fp_start( _base, _offset ) \
276       ( \
277         (void *) _Addresses_Add_offset( \
278            (_base), \
279            (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
280         ) \
281       )
282
283    #define _CPU_Context_Initialize_fp( _fp_area ) \
284       { \
285         uint32_t   *_fp_context = (uint32_t *)*(_fp_area); \
286         *(--(_fp_context)) = 0; \
287         *(_fp_area) = (void *)(_fp_context); \
288       }
289  #endif
290#endif
291
292/*
293 *  The following structures define the set of information saved
294 *  on the current stack by RTEMS upon receipt of each exc/interrupt.
295 *  These are not used by m68k handlers.
296 *  The exception frame is for rdbg.
297 */
298
299typedef struct {
300  uint32_t   vecnum; /* vector number */
301} CPU_Interrupt_frame;
302
303typedef struct {
304  uint32_t   vecnum; /* vector number */
305  uint32_t   sr; /* status register */
306  uint32_t   pc; /* program counter */
307  uint32_t   d0, d1, d2, d3, d4, d5, d6, d7;
308  uint32_t   a0, a1, a2, a3, a4, a5, a6, a7;
309} CPU_Exception_frame;
310
311/* variables */
312
313extern void*                     _VBR;
314
315#if ( M68K_HAS_VBR == 0 )
316
317/*
318 * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
319 * pushed onto the stack. This is not is the same order as VBR processors.
320 * The ISR handler takes the format and uses it for dispatching the user
321 * handler.
322 *
323 * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
324 *
325 */
326
327typedef struct {
328  uint16_t   move_a7;            /* move #FORMAT_ID,%a7@- */
329  uint16_t   format_id;
330  uint16_t   jmp;                /* jmp  _ISR_Handlers */
331  uint32_t   isr_handler;
332} _CPU_ISR_handler_entry;
333
334#define M68K_MOVE_A7 0x3F3C
335#define M68K_JMP     0x4EF9
336
337      /* points to jsr-exception-table in targets wo/ VBR register */
338SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
339
340#endif /* M68K_HAS_VBR */
341
342#endif /* ASM */
343
344/* constants */
345
346/*
347 *  This defines the number of levels and the mask used to pick those
348 *  bits out of a thread mode.
349 */
350
351#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
352#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
353
354/*
355 *  context size area for floating point
356 */
357
358#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
359
360/*
361 *  extra stack required by the MPCI receive server thread
362 */
363
364#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
365
366/*
367 *  m68k family supports 256 distinct vectors.
368 */
369
370#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
371#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
372
373/*
374 *  This is defined if the port has a special way to report the ISR nesting
375 *  level.  Most ports maintain the variable _ISR_Nest_level.
376 */
377
378#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
379
380/*
381 *  Minimum size of a thread's stack.
382 */
383
384#define CPU_STACK_MINIMUM_SIZE           M68K_CPU_STACK_MINIMUM_SIZE
385
386/*
387 *  Maximum priority of a thread. Note based from 0 which is the idle task.
388 */
389#define CPU_PRIORITY_MAXIMUM             M68K_CPU_PRIORITY_MAXIMUM
390
391#define CPU_SIZEOF_POINTER 4
392
393/*
394 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
395 */
396
397#define CPU_ALIGNMENT                    4
398#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
399#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
400
401/*
402 *  On m68k thread stacks require no further alignment after allocation
403 *  from the Workspace.
404 */
405
406#define CPU_STACK_ALIGNMENT        0
407
408#ifndef ASM
409
410/* macros */
411
412/*
413 *  ISR handler macros
414 *
415 *  These macros perform the following functions:
416 *     + initialize the RTEMS vector table
417 *     + disable all maskable CPU interrupts
418 *     + restore previous interrupt level (enable)
419 *     + temporarily restore interrupts (flash)
420 *     + set a particular level
421 */
422
423#define _CPU_Initialize_vectors()
424
425#define _CPU_ISR_Disable( _level ) \
426  m68k_disable_interrupts( _level )
427
428#define _CPU_ISR_Enable( _level ) \
429  m68k_enable_interrupts( _level )
430
431#define _CPU_ISR_Flash( _level ) \
432  m68k_flash_interrupts( _level )
433
434#define _CPU_ISR_Set_level( _newlevel ) \
435   m68k_set_interrupt_level( _newlevel )
436
437uint32_t   _CPU_ISR_Get_level( void );
438
439/* end of ISR handler macros */
440
441/*
442 *  Context handler macros
443 *
444 *  These macros perform the following functions:
445 *     + initialize a context area
446 *     + restart the current thread
447 *     + calculate the initial pointer into a FP context area
448 *     + initialize an FP context area
449 */
450
451void _CPU_Context_Initialize(
452  Context_Control *the_context,
453  void *stack_area_begin,
454  size_t stack_area_size,
455  uint32_t new_level,
456  void (*entry_point)( void ),
457  bool is_fp,
458  void *tls_area
459);
460
461/* end of Context handler macros */
462
463/*
464 *  _CPU_Thread_Idle_body
465 *
466 *  This routine is the CPU dependent IDLE thread body.
467 *
468 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
469 *         is TRUE.
470 */
471
472void *_CPU_Thread_Idle_body( uintptr_t ignored );
473
474/*
475 *  Fatal Error manager macros
476 *
477 *  These macros perform the following functions:
478 *    + disable interrupts and halt the CPU
479 */
480
481#if ( defined(__mcoldfire__) )
482#define _CPU_Fatal_halt( _source, _error ) \
483  { __asm__ volatile( "move.w %%sr,%%d0\n\t" \
484                  "or.l %2,%%d0\n\t" \
485                  "move.w %%d0,%%sr\n\t" \
486                  "move.l %1,%%d0\n\t" \
487                  "move.l #0xDEADBEEF,%%d1\n\t" \
488                  "halt" \
489                  : "=g" (_error) \
490                  : "0" (_error), "d"(0x0700) \
491                  : "d0", "d1" ); \
492  }
493#else
494#define _CPU_Fatal_halt( _source, _error ) \
495  { __asm__ volatile( "movl  %0,%%d0; " \
496                  "orw   #0x0700,%%sr; " \
497                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
498  }
499#endif
500
501/* end of Fatal Error manager macros */
502
503/*
504 *  Bitfield handler macros
505 *
506 *  These macros perform the following functions:
507 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
508 *
509 *  NOTE:
510 *
511 *    It appears that on the M68020 bitfield are always 32 bits wide
512 *    when in a register.  This code forces the bitfield to be in
513 *    memory (it really always is anyway). This allows us to
514 *    have a real 16 bit wide bitfield which operates "correctly."
515 */
516
517#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
518#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
519
520#if ( M68K_HAS_BFFFO != 1 )
521/*
522 *  Lookup table for BFFFO simulation
523 */
524extern const unsigned char _CPU_m68k_BFFFO_table[256];
525#endif
526
527#if ( M68K_HAS_BFFFO == 1 )
528
529#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
530  __asm__ volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
531
532#elif ( __mcfisaaplus__ )
533  /* This is simplified by the fact that RTEMS never calls it with _value=0 */
534#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
535    __asm__ volatile ( \
536       "   swap     %0\n"        \
537       "   ff1.l    %0\n"        \
538       : "=d" ((_output))        \
539       : "0" ((_value))          \
540       : "cc" ) ;
541
542#else
543/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
544   _CPU_Priority_bits_index is not needed), handles the 0 case, and
545   does not molest _value -- jsg */
546#if ( defined(__mcoldfire__) )
547
548#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
549  { \
550    register int dumby; \
551    \
552    __asm__ volatile ( \
553       "   clr.l   %1\n"         \
554       "   move.w  %2,%1\n"      \
555       "   lsr.l   #8,%1\n"      \
556       "   beq.s   1f\n"         \
557       "   move.b  (%3,%1),%0\n" \
558       "   bra.s   0f\n"         \
559       "1: move.w  %2,%1\n"      \
560       "   move.b  (%3,%1),%0\n" \
561       "   addq.l  #8,%0\n"      \
562       "0: and.l   #0xff,%0\n"   \
563       : "=&d" ((_output)), "=&d" ((dumby))    \
564       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
565       : "cc" ) ; \
566  }
567#elif ( M68K_HAS_EXTB_L == 1 )
568#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
569  { \
570    register int dumby; \
571    \
572    __asm__ volatile ( "   move.w  %2,%1\n"        \
573       "   lsr.w   #8,%1\n"        \
574       "   beq.s   1f\n"           \
575       "   move.b  (%3,%1.w),%0\n" \
576       "   extb.l  %0\n"           \
577       "   bra.s   0f\n"           \
578       "1: moveq.l #8,%0\n"        \
579       "   add.b   (%3,%2.w),%0\n" \
580       "0:\n"                      \
581       : "=&d" ((_output)), "=&d" ((dumby)) \
582       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
583       : "cc" ) ; \
584  }
585#else
586#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
587  { \
588    register int dumby; \
589    \
590    __asm__ volatile ( "   move.w  %2,%1\n"        \
591       "   lsr.w   #8,%1\n"        \
592       "   beq.s   1f\n"           \
593       "   move.b  (%3,%1.w),%0\n" \
594       "   and.l   #0x000000ff,%0\n"\
595       "   bra.s   0f\n"           \
596       "1: moveq.l #8,%0\n"        \
597       "   add.b   (%3,%2.w),%0\n" \
598       "0:\n"                      \
599       : "=&d" ((_output)), "=&d" ((dumby)) \
600       : "d" ((_value)), "ao" ((_CPU_m68k_BFFFO_table)) \
601       : "cc" ) ; \
602  }
603#endif
604
605#endif
606
607/* end of Bitfield handler macros */
608
609/*
610 *  Priority handler macros
611 *
612 *  These macros perform the following functions:
613 *    + return a mask with the bit for this major/minor portion of
614 *      of thread priority set.
615 *    + translate the bit number returned by "Bitfield_find_first_bit"
616 *      into an index into the thread ready chain bit maps
617 */
618
619#define _CPU_Priority_Mask( _bit_number ) \
620  ( 0x8000 >> (_bit_number) )
621
622#define _CPU_Priority_bits_index( _priority ) \
623  (_priority)
624
625/* end of Priority handler macros */
626
627/* functions */
628
629/*
630 *  _CPU_Initialize
631 *
632 *  This routine performs CPU dependent initialization.
633 */
634
635void _CPU_Initialize(void);
636
637/*
638 *  _CPU_ISR_install_raw_handler
639 *
640 *  This routine installs a "raw" interrupt handler directly into the
641 *  processor's vector table.
642 */
643
644void _CPU_ISR_install_raw_handler(
645  uint32_t    vector,
646  proc_ptr    new_handler,
647  proc_ptr   *old_handler
648);
649
650/*
651 *  _CPU_ISR_install_vector
652 *
653 *  This routine installs an interrupt vector.
654 */
655
656void _CPU_ISR_install_vector(
657  uint32_t         vector,
658  proc_ptr         new_handler,
659  proc_ptr        *old_handler
660);
661
662/*
663 *  _CPU_Install_interrupt_stack
664 *
665 *  This routine installs the hardware interrupt stack pointer.
666 */
667
668void _CPU_Install_interrupt_stack( void );
669
670/*
671 *  _CPU_Context_switch
672 *
673 *  This routine switches from the run context to the heir context.
674 */
675
676void _CPU_Context_switch(
677  Context_Control  *run,
678  Context_Control  *heir
679);
680
681void _CPU_Context_Restart_self(
682  Context_Control  *the_context
683);
684
685/*
686 *  _CPU_Context_save_fp
687 *
688 *  This routine saves the floating point context passed to it.
689 */
690
691void _CPU_Context_save_fp(
692  Context_Control_fp **fp_context_ptr
693);
694
695/*
696 *  _CPU_Context_restore_fp
697 *
698 *  This routine restores the floating point context passed to it.
699 */
700
701void _CPU_Context_restore_fp(
702  Context_Control_fp **fp_context_ptr
703);
704
705static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
706{
707  /* TODO */
708}
709
710static inline void _CPU_Context_validate( uintptr_t pattern )
711{
712  while (1) {
713    /* TODO */
714  }
715}
716
717/**
718 *  This method prints the CPU exception frame.
719 *
720 *  @param[in] frame points to the frame to be printed
721 */
722void _CPU_Exception_frame_print(
723  const CPU_Exception_frame *frame
724);
725
726typedef uint32_t CPU_Counter_ticks;
727
728CPU_Counter_ticks _CPU_Counter_read( void );
729
730static inline CPU_Counter_ticks _CPU_Counter_difference(
731  CPU_Counter_ticks second,
732  CPU_Counter_ticks first
733)
734{
735  return second - first;
736}
737
738#if (M68K_HAS_FPSP_PACKAGE == 1)
739/*
740 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
741 *
742 *  NOTES:
743 *
744 *  Motorola 68k family CPU's before the 68040 used a coprocessor
745 *  (68881 or 68882) to handle floating point.  The 68040 has internal
746 *  floating point support -- but *not* the complete support provided by
747 *  the 68881 or 68882.  The leftover functions are taken care of by the
748 *  M68040 Floating Point Support Package.  Quoting from the MC68040
749 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
750 *
751 *    "When used with the M68040FPSP, the MC68040 FPU is fully
752 *    compliant with IEEE floating-point standards."
753 *
754 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
755 *  is invoked early in the application code to ensure that proper FP
756 *  behavior is installed.  This is not left to the BSP to call, since
757 *  this would force all applications using that BSP to use FPSP which
758 *  is not necessarily desirable.
759 *
760 *  There is a similar package for the 68060 but RTEMS does not yet
761 *  support the 68060.
762 */
763
764void M68KFPSPInstallExceptionHandlers (void);
765
766SCORE_EXTERN int (*_FPSP_install_raw_handler)(
767  uint32_t   vector,
768  proc_ptr new_handler,
769  proc_ptr *old_handler
770);
771
772#endif
773
774
775#endif
776
777#ifdef __cplusplus
778}
779#endif
780
781#endif
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