source: rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h @ e0b8176

4.104.114.95
Last change on this file since e0b8176 was e0b8176, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on 07/11/08 at 10:05:13

added support for mcf548x

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File size: 19.6 KB
Line 
1/**
2 * @file rtems/score/cpu.h
3 */
4
5/*
6 *  This include file contains information pertaining to the Motorola
7 *  m68xxx processor family.
8 *
9 *  COPYRIGHT (c) 1989-2006.
10 *  On-Line Applications Research Corporation (OAR).
11 *
12 *  The license and distribution terms for this file may be
13 *  found in the file LICENSE in this distribution or at
14 *  http://www.rtems.com/license/LICENSE.
15 *
16 *  $Id$
17 */
18
19#ifndef _RTEMS_SCORE_CPU_H
20#define _RTEMS_SCORE_CPU_H
21
22#ifdef __cplusplus
23extern "C" {
24#endif
25
26#include <rtems/score/m68k.h>              /* pick up machine definitions */
27#ifndef ASM
28#include <rtems/score/types.h>
29#endif
30
31/* conditional compilation parameters */
32
33#define CPU_INLINE_ENABLE_DISPATCH       TRUE
34#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
35
36/*
37 *  Does the CPU follow the simple vectored interrupt model?
38 *
39 *  If TRUE, then RTEMS allocates the vector table it internally manages.
40 *  If FALSE, then the BSP is assumed to allocate and manage the vector
41 *  table
42 *
43 *  M68K Specific Information:
44 *
45 *  XXX document implementation including references if appropriate
46 */
47#define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
48
49/*
50 *  Use the m68k's hardware interrupt stack support and have the
51 *  interrupt manager allocate the memory for it.
52 */
53
54#if ( M68K_HAS_SEPARATE_STACKS == 1)
55#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
56#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
57#else
58#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
59#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
60#endif
61#define CPU_ALLOCATE_INTERRUPT_STACK     1
62
63/*
64 *  Does the RTEMS invoke the user's ISR with the vector number and
65 *  a pointer to the saved interrupt frame (1) or just the vector
66 *  number (0)?
67 */
68
69#define CPU_ISR_PASSES_FRAME_POINTER 0
70
71/*
72 *  Some family members have no FP, some have an FPU such as the
73 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
74 *
75 *  NOTE:  If on a CPU without hardware FP, then one can use software
76 *         emulation.  The gcc software FP emulation code has data which
77 *         must be contexted switched on a per task basis.
78 */
79
80#if ( M68K_HAS_FPU == 1 )
81#define CPU_HARDWARE_FP     TRUE
82#define CPU_SOFTWARE_FP     FALSE
83#else
84#define CPU_HARDWARE_FP     FALSE
85#if defined(__GNUC__)
86#define CPU_SOFTWARE_FP     TRUE
87#else
88#define CPU_SOFTWARE_FP     FALSE
89#endif
90#endif
91
92/*
93 *  All tasks are not by default floating point tasks on this CPU.
94 *  The IDLE task does not have a floating point context on this CPU.
95 *  It is safe to use the deferred floating point context switch
96 *  algorithm on this CPU.
97 */
98
99#define CPU_ALL_TASKS_ARE_FP             FALSE
100#define CPU_IDLE_TASK_IS_FP              FALSE
101#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
102
103#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
104#define CPU_STACK_GROWS_UP               FALSE
105#define CPU_STRUCTURE_ALIGNMENT
106
107/*
108 *  Define what is required to specify how the network to host conversion
109 *  routines are handled.
110 */
111
112#define CPU_BIG_ENDIAN                           TRUE
113#define CPU_LITTLE_ENDIAN                        FALSE
114
115#ifndef ASM
116/* structures */
117
118/*
119 *  Basic integer context for the m68k family.
120 */
121
122typedef struct {
123  uint32_t    sr;                /* (sr) status register */
124  uint32_t    d2;                /* (d2) data register 2 */
125  uint32_t    d3;                /* (d3) data register 3 */
126  uint32_t    d4;                /* (d4) data register 4 */
127  uint32_t    d5;                /* (d5) data register 5 */
128  uint32_t    d6;                /* (d6) data register 6 */
129  uint32_t    d7;                /* (d7) data register 7 */
130  void       *a2;                /* (a2) address register 2 */
131  void       *a3;                /* (a3) address register 3 */
132  void       *a4;                /* (a4) address register 4 */
133  void       *a5;                /* (a5) address register 5 */
134  void       *a6;                /* (a6) address register 6 */
135  void       *a7_msp;            /* (a7) master stack pointer */
136
137#if (defined(__mcoldfire__))
138#if ( M68K_HAS_FPU == 1 )
139  uint8_t   fpu_dis;
140#endif
141#endif
142
143}   Context_Control;
144
145#define _CPU_Context_Get_SP( _context ) \
146  (_context)->a7_msp
147
148/*
149 *  Floating point context ares
150 */
151
152#if (CPU_SOFTWARE_FP == TRUE)
153
154/*
155 *  This is the same as gcc's view of the software FP condition code
156 *  register _fpCCR.  The implementation of the emulation code is
157 *  in the gcc-VERSION/config/m68k directory.  This structure is
158 *  correct as of gcc 2.7.2.2.
159 */
160
161typedef struct {
162  uint16_t     _exception_bits;
163  uint16_t     _trap_enable_bits;
164  uint16_t     _sticky_bits;
165  uint16_t     _rounding_mode;
166  uint16_t     _format;
167  uint16_t     _last_operation;
168  union {
169    float sf;
170    double df;
171  } _operand1;
172  union {
173    float sf;
174    double df;
175  } _operand2;
176} Context_Control_fp;
177
178#elif (defined(__mcoldfire__))
179
180/*
181 *  FP context save area for the ColdFire core numeric coprocessors
182 */
183typedef struct {
184  uint8_t     fp_save_area[84];     /*    16 bytes for FSAVE/FRESTORE    */
185                                    /*    64 bytes for FMOVEM FP0-7      */
186                                    /*     4 bytes for non-null flag     */
187
188#if (M68K_HAS_EMAC == 1)
189
190/*
191 *  EMAC context save area for the ColdFire core
192 */
193  uint8_t     emac_save_area[32];   /*  32 bytes for EMAC registers      */
194
195#endif
196
197} Context_Control_fp;
198
199#if ( M68K_HAS_FPU == 1 )
200extern uint32_t _CPU_cacr_shadow;
201#endif
202
203#else
204/*
205 *  FP context save area for the M68881/M68882 numeric coprocessors.
206 */
207typedef struct {
208  uint8_t     fp_save_area[332];    /*   216 bytes for FSAVE/FRESTORE    */
209                                    /*    96 bytes for FMOVEM FP0-7      */
210                                    /*    12 bytes for FMOVEM CREGS      */
211                                    /*     4 bytes for non-null flag     */
212} Context_Control_fp;
213#endif
214
215/*
216 *  The following structures define the set of information saved
217 *  on the current stack by RTEMS upon receipt of each exc/interrupt.
218 *  These are not used by m68k handlers.
219 *  The exception frame is for rdbg.
220 */
221
222typedef struct {
223  uint32_t   vecnum; /* vector number */
224} CPU_Interrupt_frame;
225
226typedef struct {
227  uint32_t   vecnum; /* vector number */
228  uint32_t   sr; /* status register */
229  uint32_t   pc; /* program counter */
230  uint32_t   d0, d1, d2, d3, d4, d5, d6, d7;
231  uint32_t   a0, a1, a2, a3, a4, a5, a6, a7;
232} CPU_Exception_frame;
233
234/* variables */
235
236SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
237SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
238
239extern void*                     _VBR;
240
241#if ( M68K_HAS_VBR == 0 )
242
243/*
244 * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
245 * pushed onto the stack. This is not is the same order as VBR processors.
246 * The ISR handler takes the format and uses it for dispatching the user
247 * handler.
248 *
249 * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
250 *
251 */
252
253typedef struct {
254  uint16_t   move_a7;            /* move #FORMAT_ID,%a7@- */
255  uint16_t   format_id;
256  uint16_t   jmp;                /* jmp  _ISR_Handlers */
257  uint32_t   isr_handler;
258} _CPU_ISR_handler_entry;
259
260#define M68K_MOVE_A7 0x3F3C
261#define M68K_JMP     0x4EF9
262
263      /* points to jsr-exception-table in targets wo/ VBR register */
264SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
265
266#endif /* M68K_HAS_VBR */
267#endif /* ASM */
268
269/* constants */
270
271/*
272 *  This defines the number of levels and the mask used to pick those
273 *  bits out of a thread mode.
274 */
275
276#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
277#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
278
279/*
280 *  context size area for floating point
281 */
282
283#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
284
285/*
286 *  extra stack required by the MPCI receive server thread
287 */
288
289#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
290
291/*
292 *  m68k family supports 256 distinct vectors.
293 */
294
295#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
296#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
297
298/*
299 *  This is defined if the port has a special way to report the ISR nesting
300 *  level.  Most ports maintain the variable _ISR_Nest_level.
301 */
302
303#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
304
305/*
306 *  Minimum size of a thread's stack.
307 */
308
309#define CPU_STACK_MINIMUM_SIZE           M68K_CPU_STACK_MINIMUM_SIZE
310
311/*
312 *  Maximum priority of a thread. Note based from 0 which is the idle task.
313 */
314#define CPU_PRIORITY_MAXIMUM             M68K_CPU_PRIORITY_MAXIMUM
315
316/*
317 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
318 */
319
320#define CPU_ALIGNMENT                    4
321#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
322#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
323
324/*
325 *  On m68k thread stacks require no further alignment after allocation
326 *  from the Workspace.
327 */
328
329#define CPU_STACK_ALIGNMENT        0
330
331#ifndef ASM
332
333/* macros */
334
335/*
336 *  ISR handler macros
337 *
338 *  These macros perform the following functions:
339 *     + initialize the RTEMS vector table
340 *     + disable all maskable CPU interrupts
341 *     + restore previous interrupt level (enable)
342 *     + temporarily restore interrupts (flash)
343 *     + set a particular level
344 */
345
346#define _CPU_Initialize_vectors()
347
348#define _CPU_ISR_Disable( _level ) \
349  m68k_disable_interrupts( _level )
350
351#define _CPU_ISR_Enable( _level ) \
352  m68k_enable_interrupts( _level )
353
354#define _CPU_ISR_Flash( _level ) \
355  m68k_flash_interrupts( _level )
356
357#define _CPU_ISR_Set_level( _newlevel ) \
358   m68k_set_interrupt_level( _newlevel )
359
360uint32_t   _CPU_ISR_Get_level( void );
361
362/* end of ISR handler macros */
363
364/*
365 *  Context handler macros
366 *
367 *  These macros perform the following functions:
368 *     + initialize a context area
369 *     + restart the current thread
370 *     + calculate the initial pointer into a FP context area
371 *     + initialize an FP context area
372 */
373
374#if (defined(__mcoldfire__) && ( M68K_HAS_FPU == 1 ))
375#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
376                                 _isr, _entry_point, _is_fp ) \
377   do { \
378     uint32_t   _stack; \
379     \
380     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
381     _stack                  = (uint32_t  )(_stack_base) + (_size) - 4; \
382     (_the_context)->a7_msp  = (void *)_stack; \
383     *(void **)_stack        = (void *)(_entry_point); \
384     (_the_context)->fpu_dis = (_is_fp == TRUE) ? 0x00 : 0x10;          \
385   } while ( 0 )
386#else
387#define _CPU_Context_Initialize( _the_context, _stack_base, _size,      \
388                                 _isr, _entry_point, _is_fp )           \
389   do {                                                                 \
390     uint32_t   _stack;                                                 \
391                                                                        \
392     (_the_context)->sr      = 0x3000 | ((_isr) << 8);                  \
393     _stack                  = (uint32_t  )(_stack_base) + (_size) - 4; \
394     (_the_context)->a7_msp  = (void *)_stack;                          \
395     *(void **)_stack        = (void *)(_entry_point);                  \
396   } while ( 0 )
397#endif
398
399#define _CPU_Context_Restart_self( _the_context ) \
400  { asm volatile( "movew %0,%%sr ; " \
401                  "moval %1,%%a7 ; " \
402                  "rts"  \
403        : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
404        : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
405  }
406
407/*
408 *  Floating Point Context Area Support routines
409 */
410
411#if (CPU_SOFTWARE_FP == TRUE)
412
413/*
414 *  This software FP implementation is only for GCC.
415 */
416
417#define _CPU_Context_Fp_start( _base, _offset ) \
418   ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
419
420
421#define _CPU_Context_Initialize_fp( _fp_area ) \
422   { \
423   Context_Control_fp *_fp; \
424   _fp = *(Context_Control_fp **)_fp_area; \
425   _fp->_exception_bits = 0; \
426   _fp->_trap_enable_bits = 0; \
427   _fp->_sticky_bits = 0; \
428   _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
429   _fp->_format = 0;         /* NIL */ \
430   _fp->_last_operation = 0;  /* NOOP */ \
431   _fp->_operand1.df = 0; \
432   _fp->_operand2.df = 0; \
433   }
434#else
435#define _CPU_Context_Fp_start( _base, _offset ) \
436   ((void *) \
437     _Addresses_Add_offset( \
438        (_base), \
439        (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
440     ) \
441   )
442
443#if (defined(__mcoldfire__) && ( M68K_HAS_FPU == 1 ))
444#define _CPU_Context_Initialize_fp( _fp_area ) \
445   { uint32_t   *_fp_context = (uint32_t   *)*(_fp_area); \
446     \
447     *(--(_fp_context)) = 0; \
448     *(_fp_area) = (uint8_t   *)(_fp_context); \
449     asm volatile("movl %0,%%macsr": : "d" (0) ); \
450   }
451#else
452#define _CPU_Context_Initialize_fp( _fp_area ) \
453   { uint32_t   *_fp_context = (uint32_t   *)*(_fp_area); \
454     \
455     *(--(_fp_context)) = 0; \
456     *(_fp_area) = (uint8_t   *)(_fp_context); \
457   }
458#endif
459#endif
460
461/* end of Context handler macros */
462
463/*
464 *  _CPU_Thread_Idle_body
465 *
466 *  This routine is the CPU dependent IDLE thread body.
467 *
468 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
469 *         is TRUE.
470 */
471
472void _CPU_Thread_Idle_body( void );
473
474/*
475 *  Fatal Error manager macros
476 *
477 *  These macros perform the following functions:
478 *    + disable interrupts and halt the CPU
479 */
480
481#if ( defined(__mcoldfire__) )
482#define _CPU_Fatal_halt( _error ) \
483  { asm volatile( "move.w %%sr,%%d0\n\t" \
484                  "or.l %2,%%d0\n\t" \
485                  "move.w %%d0,%%sr\n\t" \
486                  "move.l %1,%%d0\n\t" \
487                  "move.l #0xDEADBEEF,%%d1\n\t" \
488                  "halt" \
489                  : "=g" (_error) \
490                  : "0" (_error), "d"(0x0700) \
491                  : "d0", "d1" ); \
492  }
493#else
494#define _CPU_Fatal_halt( _error ) \
495  { asm volatile( "movl  %0,%%d0; " \
496                  "orw   #0x0700,%%sr; " \
497                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
498  }
499#endif
500
501/* end of Fatal Error manager macros */
502
503/*
504 *  Bitfield handler macros
505 *
506 *  These macros perform the following functions:
507 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
508 *
509 *  NOTE:
510 *
511 *    It appears that on the M68020 bitfield are always 32 bits wide
512 *    when in a register.  This code forces the bitfield to be in
513 *    memory (it really always is anyway). This allows us to
514 *    have a real 16 bit wide bitfield which operates "correctly."
515 */
516
517#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
518#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
519
520#if ( M68K_HAS_BFFFO == 1 )
521
522#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
523  asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
524
525#elif ( __mcfisaaplus__ )
526  /* This is simplified by the fact that RTEMS never calls it with _value=0 */
527#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
528    asm volatile ( \
529       "   swap     %0\n"        \
530       "   ff1.l    %0\n"        \
531       : "=d" ((_output))        \
532       : "0" ((_value))          \
533       : "cc" ) ;
534
535#else
536/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
537   _CPU_Priority_bits_index is not needed), handles the 0 case, and
538   does not molest _value -- jsg */
539#if ( defined(__mcoldfire__) )
540#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
541  { \
542    extern const unsigned char __BFFFOtable[256]; \
543    register int dumby; \
544    \
545    asm volatile ( \
546       "   clr.l   %1\n"         \
547       "   move.w  %2,%1\n"      \
548       "   lsr.l   #8,%1\n"      \
549       "   beq.s   1f\n"         \
550       "   move.b  (%3,%1),%0\n" \
551       "   bra.s   0f\n"         \
552       "1: move.w  %2,%1\n"      \
553       "   move.b  (%3,%1),%0\n" \
554       "   addq.l  #8,%0\n"      \
555       "0: and.l   #0xff,%0\n"   \
556       : "=&d" ((_output)), "=&d" ((dumby))    \
557       : "d" ((_value)), "ao" ((__BFFFOtable)) \
558       : "cc" ) ; \
559  }
560#elif ( M68K_HAS_EXTB_L == 1 )
561#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
562  { \
563    extern const unsigned char __BFFFOtable[256]; \
564    register int dumby; \
565    \
566    asm volatile ( "   move.w  %2,%1\n"        \
567       "   lsr.w   #8,%1\n"        \
568       "   beq.s   1f\n"           \
569       "   move.b  (%3,%1.w),%0\n" \
570       "   extb.l  %0\n"           \
571       "   bra.s   0f\n"           \
572       "1: moveq.l #8,%0\n"        \
573       "   add.b   (%3,%2.w),%0\n" \
574       "0:\n"                      \
575       : "=&d" ((_output)), "=&d" ((dumby)) \
576       : "d" ((_value)), "ao" ((__BFFFOtable)) \
577       : "cc" ) ; \
578  }
579#else
580#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
581  { \
582    extern const unsigned char __BFFFOtable[256]; \
583    register int dumby; \
584    \
585    asm volatile ( "   move.w  %2,%1\n"        \
586       "   lsr.w   #8,%1\n"        \
587       "   beq.s   1f\n"           \
588       "   move.b  (%3,%1.w),%0\n" \
589       "   and.l   #0x000000ff,%0\n"\
590       "   bra.s   0f\n"           \
591       "1: moveq.l #8,%0\n"        \
592       "   add.b   (%3,%2.w),%0\n" \
593       "0:\n"                      \
594       : "=&d" ((_output)), "=&d" ((dumby)) \
595       : "d" ((_value)), "ao" ((__BFFFOtable)) \
596       : "cc" ) ; \
597  }
598#endif
599
600#endif
601
602/* end of Bitfield handler macros */
603
604/*
605 *  Priority handler macros
606 *
607 *  These macros perform the following functions:
608 *    + return a mask with the bit for this major/minor portion of
609 *      of thread priority set.
610 *    + translate the bit number returned by "Bitfield_find_first_bit"
611 *      into an index into the thread ready chain bit maps
612 */
613
614#define _CPU_Priority_Mask( _bit_number ) \
615  ( 0x8000 >> (_bit_number) )
616
617#define _CPU_Priority_bits_index( _priority ) \
618  (_priority)
619
620/* end of Priority handler macros */
621
622/* functions */
623
624/*
625 *  _CPU_Initialize
626 *
627 *  This routine performs CPU dependent initialization.
628 */
629
630void _CPU_Initialize(
631  void      (*thread_dispatch)
632);
633
634/*
635 *  _CPU_ISR_install_raw_handler
636 *
637 *  This routine installs a "raw" interrupt handler directly into the
638 *  processor's vector table.
639 */
640 
641void _CPU_ISR_install_raw_handler(
642  uint32_t    vector,
643  proc_ptr    new_handler,
644  proc_ptr   *old_handler
645);
646
647/*
648 *  _CPU_ISR_install_vector
649 *
650 *  This routine installs an interrupt vector.
651 */
652
653void _CPU_ISR_install_vector(
654  uint32_t         vector,
655  proc_ptr         new_handler,
656  proc_ptr        *old_handler
657);
658
659/*
660 *  _CPU_Install_interrupt_stack
661 *
662 *  This routine installs the hardware interrupt stack pointer.
663 */
664
665void _CPU_Install_interrupt_stack( void );
666
667/*
668 *  _CPU_Context_switch
669 *
670 *  This routine switches from the run context to the heir context.
671 */
672
673void _CPU_Context_switch(
674  Context_Control  *run,
675  Context_Control  *heir
676);
677
678/*
679 *  _CPU_Context_save_fp
680 *
681 *  This routine saves the floating point context passed to it.
682 */
683
684void _CPU_Context_save_fp(
685  Context_Control_fp **fp_context_ptr
686);
687
688/*
689 *  _CPU_Context_restore_fp
690 *
691 *  This routine restores the floating point context passed to it.
692 */
693
694void _CPU_Context_restore_fp(
695  Context_Control_fp **fp_context_ptr
696);
697
698#if (M68K_HAS_FPSP_PACKAGE == 1)
699/*
700 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
701 *
702 *  NOTES: 
703 *
704 *  Motorola 68k family CPU's before the 68040 used a coprocessor
705 *  (68881 or 68882) to handle floating point.  The 68040 has internal
706 *  floating point support -- but *not* the complete support provided by
707 *  the 68881 or 68882.  The leftover functions are taken care of by the
708 *  M68040 Floating Point Support Package.  Quoting from the MC68040
709 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
710 *
711 *    "When used with the M68040FPSP, the MC68040 FPU is fully
712 *    compliant with IEEE floating-point standards."
713 *
714 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
715 *  is invoked early in the application code to ensure that proper FP
716 *  behavior is installed.  This is not left to the BSP to call, since
717 *  this would force all applications using that BSP to use FPSP which
718 *  is not necessarily desirable.
719 *
720 *  There is a similar package for the 68060 but RTEMS does not yet
721 *  support the 68060.
722 */
723
724void M68KFPSPInstallExceptionHandlers (void);
725
726SCORE_EXTERN int (*_FPSP_install_raw_handler)(
727  uint32_t   vector,
728  proc_ptr new_handler,
729  proc_ptr *old_handler
730);
731
732#endif
733
734
735#endif
736
737#ifdef __cplusplus
738}
739#endif
740
741#endif
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