source: rtems/cpukit/score/cpu/m68k/rtems/score/cpu.h @ e065e8ae

4.104.114.84.95
Last change on this file since e065e8ae was e065e8ae, checked in by Joel Sherrill <joel.sherrill@…>, on Jan 3, 2000 at 4:52:50 PM

Increased stack size to 4K per Eric Norum.

  • Property mode set to 100644
File size: 17.1 KB
Line 
1/*  cpu.h
2 *
3 *  This include file contains information pertaining to the Motorola
4 *  m68xxx processor family.
5 *
6 *  COPYRIGHT (c) 1989-1999.
7 *  On-Line Applications Research Corporation (OAR).
8 *
9 *  The license and distribution terms for this file may be
10 *  found in the file LICENSE in this distribution or at
11 *  http://www.OARcorp.com/rtems/license.html.
12 *
13 *  $Id$
14 */
15
16#ifndef __CPU_h
17#define __CPU_h
18
19#ifdef __cplusplus
20extern "C" {
21#endif
22
23#include <rtems/score/m68k.h>              /* pick up machine definitions */
24#ifndef ASM
25#include <rtems/score/m68ktypes.h>
26#endif
27
28/* conditional compilation parameters */
29
30#define CPU_INLINE_ENABLE_DISPATCH       TRUE
31#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
32
33/*
34 *  Use the m68k's hardware interrupt stack support and have the
35 *  interrupt manager allocate the memory for it.
36 */
37
38#if ( M68K_HAS_SEPARATE_STACKS == 1)
39#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 0
40#define CPU_HAS_HARDWARE_INTERRUPT_STACK 1
41#else
42#define CPU_HAS_SOFTWARE_INTERRUPT_STACK 1
43#define CPU_HAS_HARDWARE_INTERRUPT_STACK 0
44#endif
45#define CPU_ALLOCATE_INTERRUPT_STACK     1
46
47/*
48 *  Does the RTEMS invoke the user's ISR with the vector number and
49 *  a pointer to the saved interrupt frame (1) or just the vector
50 *  number (0)?
51 */
52
53#define CPU_ISR_PASSES_FRAME_POINTER 0
54
55/*
56 *  Some family members have no FP, some have an FPU such as the
57 *  MC68881/MC68882 for the MC68020, others have it built in (MC68030, 040).
58 *
59 *  NOTE:  If on a CPU without hardware FP, then one can use software
60 *         emulation.  The gcc software FP emulation code has data which
61 *         must be contexted switched on a per task basis.
62 */
63
64#if ( M68K_HAS_FPU == 1 )
65#define CPU_HARDWARE_FP     TRUE
66#define CPU_SOFTWARE_FP     FALSE
67#else
68#define CPU_HARDWARE_FP     FALSE
69#if defined(__GNUC__)
70#define CPU_SOFTWARE_FP     TRUE
71#else
72#define CPU_SOFTWARE_FP     FALSE
73#endif
74#endif
75
76/*
77 *  All tasks are not by default floating point tasks on this CPU.
78 *  The IDLE task does not have a floating point context on this CPU.
79 *  It is safe to use the deferred floating point context switch
80 *  algorithm on this CPU.
81 */
82
83#define CPU_ALL_TASKS_ARE_FP             FALSE
84#define CPU_IDLE_TASK_IS_FP              FALSE
85#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
86
87#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
88#define CPU_STACK_GROWS_UP               FALSE
89#define CPU_STRUCTURE_ALIGNMENT
90
91/*
92 *  Define what is required to specify how the network to host conversion
93 *  routines are handled.
94 */
95
96#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
97#define CPU_BIG_ENDIAN                           TRUE
98#define CPU_LITTLE_ENDIAN                        FALSE
99
100#ifndef ASM
101/* structures */
102
103/*
104 *  Basic integer context for the m68k family.
105 */
106
107typedef struct {
108  unsigned32  sr;                /* (sr) status register */
109  unsigned32  d2;                /* (d2) data register 2 */
110  unsigned32  d3;                /* (d3) data register 3 */
111  unsigned32  d4;                /* (d4) data register 4 */
112  unsigned32  d5;                /* (d5) data register 5 */
113  unsigned32  d6;                /* (d6) data register 6 */
114  unsigned32  d7;                /* (d7) data register 7 */
115  void       *a2;                /* (a2) address register 2 */
116  void       *a3;                /* (a3) address register 3 */
117  void       *a4;                /* (a4) address register 4 */
118  void       *a5;                /* (a5) address register 5 */
119  void       *a6;                /* (a6) address register 6 */
120  void       *a7_msp;            /* (a7) master stack pointer */
121}   Context_Control;
122
123/*
124 *  Floating point context ares
125 */
126
127#if (CPU_SOFTWARE_FP == TRUE)
128
129/*
130 *  This is the same as gcc's view of the software FP condition code
131 *  register _fpCCR.  The implementation of the emulation code is
132 *  in the gcc-VERSION/config/m68k directory.  This structure is
133 *  correct as of gcc 2.7.2.2.
134 */
135
136typedef struct {
137  unsigned16   _exception_bits;
138  unsigned16   _trap_enable_bits;
139  unsigned16   _sticky_bits;
140  unsigned16   _rounding_mode;
141  unsigned16   _format;
142  unsigned16   _last_operation;
143  union {
144    float sf;
145    double df;
146  } _operand1;
147  union {
148    float sf;
149    double df;
150  } _operand2;
151} Context_Control_fp;
152
153#else
154
155/*
156 *  FP context save area for the M68881/M68882 numeric coprocessors.
157 */
158
159typedef struct {
160  unsigned8   fp_save_area[332];    /*   216 bytes for FSAVE/FRESTORE    */
161                                    /*    96 bytes for FMOVEM FP0-7      */
162                                    /*    12 bytes for FMOVEM CREGS      */
163                                    /*     4 bytes for non-null flag     */
164} Context_Control_fp;
165#endif
166
167/*
168 *  The following structure defines the set of information saved
169 *  on the current stack by RTEMS upon receipt of each interrupt.
170 */
171
172typedef struct {
173  unsigned32   TBD;   /* XXX Fix for this CPU */
174} CPU_Interrupt_frame;
175
176/*
177 *  The following table contains the information required to configure
178 *  the m68k specific parameters.
179 */
180
181typedef struct {
182  void       (*pretasking_hook)( void );
183  void       (*predriver_hook)( void );
184  void       (*postdriver_hook)( void );
185  void       (*idle_task)( void );
186  boolean      do_zero_of_workspace;
187  unsigned32   idle_task_stack_size;
188  unsigned32   interrupt_stack_size;
189  unsigned32   extra_mpci_receive_server_stack;
190  void *     (*stack_allocate_hook)( unsigned32 );
191  void       (*stack_free_hook)( void* );
192  /* end of fields required on all CPUs */
193
194  m68k_isr    *interrupt_vector_table;
195}   rtems_cpu_table;
196
197/*
198 *  Macros to access required entires in the CPU Table are in
199 *  the file rtems/system.h.
200 */
201
202/*
203 *  Macros to access M68K specific additions to the CPU Table
204 */
205
206#define rtems_cpu_configuration_get_interrupt_vector_table() \
207   (_CPU_Table.interrupt_vector_table)
208
209/* variables */
210
211SCORE_EXTERN void                   *_CPU_Interrupt_stack_low;
212SCORE_EXTERN void                   *_CPU_Interrupt_stack_high;
213
214extern char                         _VBR[]; 
215
216#if ( M68K_HAS_VBR == 0 )
217
218/*
219 * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
220 * pushed onto the stack. This is not is the same order as VBR processors.
221 * The ISR handler takes the format and uses it for dispatching the user
222 * handler.
223 *
224 * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
225 *
226 */
227
228typedef struct {
229  unsigned16 move_a7;            /* move #FORMAT_ID,%a7@- */
230  unsigned16 format_id;
231  unsigned16 jmp;                /* jmp  _ISR_Handlers */
232  unsigned32 isr_handler;
233} _CPU_ISR_handler_entry;
234
235#define M68K_MOVE_A7 0x3F3C
236#define M68K_JMP     0x4EF9
237
238      /* points to jsr-exception-table in targets wo/ VBR register */
239SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; 
240
241#endif /* M68K_HAS_VBR */
242#endif /* ASM */
243
244/* constants */
245
246/*
247 *  This defines the number of levels and the mask used to pick those
248 *  bits out of a thread mode.
249 */
250
251#define CPU_MODES_INTERRUPT_LEVEL  0x00000007 /* interrupt level in mode */
252#define CPU_MODES_INTERRUPT_MASK   0x00000007 /* interrupt level in mode */
253
254/*
255 *  context size area for floating point
256 */
257
258#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
259
260/*
261 *  extra stack required by the MPCI receive server thread
262 */
263
264#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
265
266/*
267 *  m68k family supports 256 distinct vectors.
268 */
269
270#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
271#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
272
273/*
274 *  Minimum size of a thread's stack.
275 */
276
277#define CPU_STACK_MINIMUM_SIZE           4096
278
279/*
280 *  m68k is pretty tolerant of alignment.  Just put things on 4 byte boundaries.
281 */
282
283#define CPU_ALIGNMENT                    4
284#define CPU_HEAP_ALIGNMENT               CPU_ALIGNMENT
285#define CPU_PARTITION_ALIGNMENT          CPU_ALIGNMENT
286
287/*
288 *  On m68k thread stacks require no further alignment after allocation
289 *  from the Workspace.
290 */
291
292#define CPU_STACK_ALIGNMENT        0
293
294#ifndef ASM
295
296/* macros */
297
298/*
299 *  ISR handler macros
300 *
301 *  These macros perform the following functions:
302 *     + disable all maskable CPU interrupts
303 *     + restore previous interrupt level (enable)
304 *     + temporarily restore interrupts (flash)
305 *     + set a particular level
306 */
307
308#define _CPU_ISR_Disable( _level ) \
309  m68k_disable_interrupts( _level )
310
311#define _CPU_ISR_Enable( _level ) \
312  m68k_enable_interrupts( _level )
313
314#define _CPU_ISR_Flash( _level ) \
315  m68k_flash_interrupts( _level )
316
317#define _CPU_ISR_Set_level( _newlevel ) \
318   m68k_set_interrupt_level( _newlevel )
319
320unsigned32 _CPU_ISR_Get_level( void );
321
322/* end of ISR handler macros */
323
324/*
325 *  Context handler macros
326 *
327 *  These macros perform the following functions:
328 *     + initialize a context area
329 *     + restart the current thread
330 *     + calculate the initial pointer into a FP context area
331 *     + initialize an FP context area
332 */
333
334#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
335                                 _isr, _entry_point, _is_fp ) \
336   do { \
337     unsigned32 _stack; \
338     \
339     (_the_context)->sr      = 0x3000 | ((_isr) << 8); \
340     _stack                  = (unsigned32)(_stack_base) + (_size) - 4; \
341     (_the_context)->a7_msp  = (void *)_stack; \
342     *(void **)_stack        = (void *)(_entry_point); \
343   } while ( 0 )
344
345#define _CPU_Context_Restart_self( _the_context ) \
346  { asm volatile( "movew %0,%%sr ; " \
347                  "moval %1,%%a7 ; " \
348                  "rts"  \
349        : "=d" ((_the_context)->sr), "=d" ((_the_context)->a7_msp) \
350        : "0" ((_the_context)->sr), "1" ((_the_context)->a7_msp) ); \
351  }
352
353/*
354 *  Floating Point Context Area Support routines
355 */
356
357#if (CPU_SOFTWARE_FP == TRUE)
358
359/*
360 *  This software FP implementation is only for GCC.
361 */
362
363#define _CPU_Context_Fp_start( _base, _offset ) \
364   ((void *) _Addresses_Add_offset( (_base), (_offset) ) )
365
366
367#define _CPU_Context_Initialize_fp( _fp_area ) \
368   { \
369   Context_Control_fp *_fp; \
370   _fp = *(Context_Control_fp **)_fp_area; \
371   _fp->_exception_bits = 0; \
372   _fp->_trap_enable_bits = 0; \
373   _fp->_sticky_bits = 0; \
374   _fp->_rounding_mode = 0;  /* ROUND_TO_NEAREST */ \
375   _fp->_format = 0;         /* NIL */ \
376   _fp->_last_operation = 0;  /* NOOP */ \
377   _fp->_operand1.df = 0; \
378   _fp->_operand2.df = 0; \
379   }
380#else
381#define _CPU_Context_Fp_start( _base, _offset ) \
382   ((void *) \
383     _Addresses_Add_offset( \
384        (_base), \
385        (_offset) + CPU_CONTEXT_FP_SIZE - 4 \
386     ) \
387   )
388
389#define _CPU_Context_Initialize_fp( _fp_area ) \
390   { unsigned32 *_fp_context = (unsigned32 *)*(_fp_area); \
391     \
392     *(--(_fp_context)) = 0; \
393     *(_fp_area) = (unsigned8 *)(_fp_context); \
394   }
395#endif
396
397/* end of Context handler macros */
398
399/*
400 *  Fatal Error manager macros
401 *
402 *  These macros perform the following functions:
403 *    + disable interrupts and halt the CPU
404 */
405
406#if ( M68K_COLDFIRE_ARCH == 1 )
407#define _CPU_Fatal_halt( _error ) \
408  { asm volatile( "move.w %%sr,%%d0\n\t" \
409                  "or.l %2,%%d0\n\t" \
410                  "move.w %%d0,%%sr\n\t" \
411                  "move.l %1,%%d0\n\t" \
412                  "move.l #0xDEADBEEF,%%d1\n\t" \
413                  "halt" \
414                  : "=g" (_error) \
415                  : "0" (_error), "d"(0x0700) \
416                  : "d0", "d1" ); \
417  }
418#else
419#define _CPU_Fatal_halt( _error ) \
420  { asm volatile( "movl  %0,%%d0; " \
421                  "orw   #0x0700,%%sr; " \
422                  "stop  #0x2700" : "=d" ((_error)) : "0" ((_error)) ); \
423  }
424#endif
425
426/* end of Fatal Error manager macros */
427
428/*
429 *  Bitfield handler macros
430 *
431 *  These macros perform the following functions:
432 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
433 *
434 *  NOTE:
435 *
436 *    It appears that on the M68020 bitfield are always 32 bits wide
437 *    when in a register.  This code forces the bitfield to be in
438 *    memory (it really always is anyway). This allows us to
439 *    have a real 16 bit wide bitfield which operates "correctly."
440 */
441
442#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
443#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
444
445#if ( M68K_HAS_BFFFO == 1 )
446
447#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
448  asm volatile( "bfffo (%1),#0,#16,%0" : "=d" (_output) : "a" (&_value));
449#else
450
451/* duplicates BFFFO results for 16 bits (i.e., 15-(_priority) in
452   _CPU_Priority_bits_index is not needed), handles the 0 case, and
453   does not molest _value -- jsg */
454#if ( M68K_COLDFIRE_ARCH == 1 )
455#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
456  { \
457    extern const unsigned char __BFFFOtable[256]; \
458    register int dumby; \
459    \
460    asm volatile ( \
461       "   clr.l   %1\n"         \
462       "   move.w  %2,%1\n"      \
463       "   lsr.l   #8,%1\n"      \
464       "   beq.s   1f\n"         \
465       "   move.b  (%3,%1),%0\n" \
466       "   bra.s   0f\n"         \
467       "1: move.w  %2,%1\n"      \
468       "   move.b  (%3,%1),%0\n" \
469       "   addq.l  #8,%0\n"      \
470       "0: and.l   #0xff,%0\n"   \
471       : "=&d" ((_output)), "=&d" ((dumby))    \
472       : "d" ((_value)), "ao" ((__BFFFOtable)) \
473       : "cc" ) ; \
474  }
475#elif ( M68K_HAS_EXTB_L == 1 )
476#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
477  { \
478    extern const unsigned char __BFFFOtable[256]; \
479    register int dumby; \
480    \
481    asm volatile ( "   move.w  %2,%1\n"        \
482       "   lsr.w   #8,%1\n"        \
483       "   beq.s   1f\n"           \
484       "   move.b  (%3,%1.w),%0\n" \
485       "   extb.l  %0\n"           \
486       "   bra.s   0f\n"           \
487       "1: moveq.l #8,%0\n"        \
488       "   add.b   (%3,%2.w),%0\n" \
489       "0:\n"                      \
490       : "=&d" ((_output)), "=&d" ((dumby)) \
491       : "d" ((_value)), "ao" ((__BFFFOtable)) \
492       : "cc" ) ; \
493  }
494#else
495#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
496  { \
497    extern const unsigned char __BFFFOtable[256]; \
498    register int dumby; \
499    \
500    asm volatile ( "   move.w  %2,%1\n"        \
501       "   lsr.w   #8,%1\n"        \
502       "   beq.s   1f\n"           \
503       "   move.b  (%3,%1.w),%0\n" \
504       "   and.l   #0x000000ff,%0\n"\
505       "   bra.s   0f\n"           \
506       "1: moveq.l #8,%0\n"        \
507       "   add.b   (%3,%2.w),%0\n" \
508       "0:\n"                      \
509       : "=&d" ((_output)), "=&d" ((dumby)) \
510       : "d" ((_value)), "ao" ((__BFFFOtable)) \
511       : "cc" ) ; \
512  }
513#endif
514
515#endif
516
517/* end of Bitfield handler macros */
518
519/*
520 *  Priority handler macros
521 *
522 *  These macros perform the following functions:
523 *    + return a mask with the bit for this major/minor portion of
524 *      of thread priority set.
525 *    + translate the bit number returned by "Bitfield_find_first_bit"
526 *      into an index into the thread ready chain bit maps
527 */
528
529#define _CPU_Priority_Mask( _bit_number ) \
530  ( 0x8000 >> (_bit_number) )
531
532#define _CPU_Priority_bits_index( _priority ) \
533  (_priority)
534
535/* end of Priority handler macros */
536
537/* functions */
538
539/*
540 *  _CPU_Initialize
541 *
542 *  This routine performs CPU dependent initialization.
543 */
544
545void _CPU_Initialize(
546  rtems_cpu_table  *cpu_table,
547  void      (*thread_dispatch)
548);
549
550/*
551 *  _CPU_ISR_install_raw_handler
552 *
553 *  This routine installs a "raw" interrupt handler directly into the
554 *  processor's vector table.
555 */
556 
557void _CPU_ISR_install_raw_handler(
558  unsigned32  vector,
559  proc_ptr    new_handler,
560  proc_ptr   *old_handler
561);
562
563/*
564 *  _CPU_ISR_install_vector
565 *
566 *  This routine installs an interrupt vector.
567 */
568
569void _CPU_ISR_install_vector(
570  unsigned32       vector,
571  proc_ptr         new_handler,
572  proc_ptr        *old_handler
573);
574
575/*
576 *  _CPU_Install_interrupt_stack
577 *
578 *  This routine installs the hardware interrupt stack pointer.
579 */
580
581void _CPU_Install_interrupt_stack( void );
582
583/*
584 *  _CPU_Context_switch
585 *
586 *  This routine switches from the run context to the heir context.
587 */
588
589void _CPU_Context_switch(
590  Context_Control  *run,
591  Context_Control  *heir
592);
593
594/*
595 *  _CPU_Context_save_fp
596 *
597 *  This routine saves the floating point context passed to it.
598 */
599
600void _CPU_Context_save_fp(
601  void **fp_context_ptr
602);
603
604/*
605 *  _CPU_Context_restore_fp
606 *
607 *  This routine restores the floating point context passed to it.
608 */
609
610void _CPU_Context_restore_fp(
611  void **fp_context_ptr
612);
613
614#if (M68K_HAS_FPSP_PACKAGE == 1)
615/*
616 *  Hooks for the Floating Point Support Package (FPSP) provided by Motorola
617 *
618 *  NOTES: 
619 *
620 *  Motorola 68k family CPU's before the 68040 used a coprocessor
621 *  (68881 or 68882) to handle floating point.  The 68040 has internal
622 *  floating point support -- but *not* the complete support provided by
623 *  the 68881 or 68882.  The leftover functions are taken care of by the
624 *  M68040 Floating Point Support Package.  Quoting from the MC68040
625 *  Microprocessors User's Manual, Section 9, Floating-Point Unit (MC68040):
626 *
627 *    "When used with the M68040FPSP, the MC68040 FPU is fully
628 *    compliant with IEEE floating-point standards."
629 *
630 *  M68KFPSPInstallExceptionHandlers is in libcpu/m68k/MODEL/fpsp and
631 *  is invoked early in the application code to insure that proper FP
632 *  behavior is installed.  This is not left to the BSP to call, since
633 *  this would force all applications using that BSP to use FPSP which
634 *  is not necessarily desirable.
635 *
636 *  There is a similar package for the 68060 but RTEMS does not yet
637 *  support the 68060.
638 */
639
640void M68KFPSPInstallExceptionHandlers (void);
641
642SCORE_EXTERN int (*_FPSP_install_raw_handler)(
643  unsigned32 vector,
644  proc_ptr new_handler,
645  proc_ptr *old_handler
646);
647
648#endif
649
650
651#endif
652
653#ifdef __cplusplus
654}
655#endif
656
657#endif
658/* end of include file */
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